JP5123575B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring board in which a substrate such as glass is bonded to a semiconductor substrate such as a silicon wafer provided with a functional element, and a manufacturing method thereof, and more specifically, for example, a charge coupled device (CCD) or a CMOS (CMOS) An optical semiconductor device provided with a functional element such as a solid-state imaging element (Complementary Metal-oxide Semiconductor) is manufactured in a wafer level package, and the mounting reliability of bumps after mounting on a mounting substrate is improved.

  As a structure of a wafer level package of a semiconductor substrate such as a silicon wafer on which a semiconductor device is formed, for example, a semiconductor package as shown in FIG. 10 is known. This package is obtained by bonding a semiconductor substrate 111 and a mounting substrate 121. The semiconductor substrate 111 includes a functional element 112 on one surface, a conductive layer 113 that outputs a signal from the functional element 112, and a surface protective film 114 that covers the one surface except for the conductive layer 113. Is provided. On the other hand, the mounting substrate 121 is provided with a conductive layer 123 on one surface. Then, the conductive layer 113 of the semiconductor substrate 111 and the conductive layer 123 of the mounting substrate 121 are arranged so as to face each other, and the conductive layer 113 and the conductive layer 123 are electrically connected via the solder bump 119. .

In such a semiconductor device package, as a mounting reliability evaluation or a reliability improvement measure by the package structure, a bump height is increased or a discarded bump is provided, or a resin post is provided between the bump and the substrate. Etc. are done.
For example, as a means to solve the problem of cracks at the junction between the semiconductor package and the printed wiring board, a resist layer is provided on the wiring drawn from the electrode pads arranged on the semiconductor substrate, and formed on this resist layer. There has been proposed a semiconductor package having a conductive resin columnar member filling a groove and a bump made of a conductive resin provided integrally on the columnar member (see Patent Document 1).

  Further, as a wafer level package structure in which a glass substrate or the like is bonded to a semiconductor substrate such as a silicon wafer on which an optical semiconductor device is formed, for example, a semiconductor package as shown in FIG. 11 is known. In this package, a Si (silicon) / glass bonded substrate 140 in which a semiconductor substrate 141 and a glass substrate 146 are bonded through a sealing portion 147 and a mounting substrate 151 are bonded. The semiconductor substrate 141 has a functional element 142 arranged on one surface, a through wiring 145 that outputs a signal from the functional element 142 from one surface to the other surface, and a through wiring arranged on the other surface. A conductive layer 143 electrically connected to 145, and a surface protective film 144 covering the one surface except for the conductive layer 143. On the other hand, the mounting substrate 151 is provided with a conductive layer 153 on one surface. Then, the conductive layer 143 of the semiconductor substrate 141 and the conductive layer 153 of the mounting substrate 151 are disposed so as to face each other, and the conductive layer 143 and the conductive layer 153 are electrically connected through the solder bump 149. . In the optical semiconductor package as shown in FIG. 11, the cavity 148 is formed in the image area of the functional element 142, but there is a case where there is no cavity.

In addition, as a package for a semiconductor substrate such as a silicon wafer on which such an optical semiconductor device is formed, one having the following structure has been proposed.
For example, as a means for solving the problem of downsizing and simplifying the manufacturing process and reducing the manufacturing cost, a semiconductor wafer in which a plurality of semiconductor chips each having a device to be sealed formed are arranged, and the semiconductor chip And a cap array wafer comprising a plurality of sealing caps that are bonded to the surface of the semiconductor chip and seal the device to be sealed in a cavity formed in the space between the semiconductor chip and the semiconductor chip. . Then, a plurality of via holes are provided through the semiconductor wafer to form embedded electrodes, and bump electrodes are further formed. Then, what is divided | segmented into each package is proposed by cut | disconnecting this structure along a scribe line (refer patent document 2).

  Further, as a means for solving the problems of preventing the inclination of the lid member, the damage of the semiconductor substrate or each part provided on the semiconductor substrate by the lid member, and the damage of the semiconductor substrate at the time of manufacture, the imaging device and the micro A lens part is formed, a penetrating electrode penetrating the semiconductor substrate is formed, a protruding part protruding from the surface toward the glass lid is formed on the penetrating electrode thicker than the thickness of the microlens part, and the protruding part is formed between the semiconductor substrate and the glass lid. Has been proposed (see Patent Document 3).

  In the optical semiconductor device package described above, there are few examples of mounting reliability evaluation, and the same mounting reliability evaluation and reliability improvement measures as those of the wafer level package of the semiconductor substrate can be applied. In addition, in a Si / glass bonded substrate such as a wafer level package of an optical semiconductor device, it is considered that the mounting reliability can be improved by means different from the mounting reliability of the Si substrate. .

  That is, the failure factor of the mounting reliability in the Si / glass bonded substrate is mainly the failure of the bump, and how to relieve the stress affecting the bump is important. For example, as shown in FIG. 12, the failure of the bump 149 is caused by the expanded mounting board 151 due to the difference between the expansion coefficient of the package (Si / glass bonded substrate 140) and the expansion coefficient of the mounting board 151 such as epoxy resin. Stress is applied to the bump 149, leading to failure of the bump 149. Therefore, in a package using a bonded substrate, it is necessary to have a structure that can relieve stress on the bump 149.

However, when a substrate such as glass is bonded to a semiconductor substrate provided with a functional element, a structure in which a sealing portion 147 is provided at a position avoiding the functional element as shown in FIG. When considering the mounting reliability in the package structure of such an optical semiconductor device, the glass substrate and the Si substrate are not bonded in the image area 163 and the cavity area 162 of the functional element, and therefore when the mounting substrate is thermally expanded. However, the Si substrate on the package side is easily deformed, and the stress on the bump can be relieved. However, in the Si / glass bonding area 161 where the glass substrate and the Si substrate are bonded, the package side is not easily deformed when the mounting substrate is thermally expanded. The stress is concentrated on the bump, which is not preferable in terms of mounting reliability.
JP 2004-119574 A JP 2005-019966 A JP 2005-209967 A

The present invention has been made in view of the above circumstances, and in a wiring board having a bonded structure, it is possible to relieve stress applied to a bump after being mounted on a mounting board, and to obtain a wiring board that improves mounting reliability. Is the primary purpose.
It is a second object of the present invention to provide a method for manufacturing a wiring board with improved mounting reliability at the wafer level.

A wiring board according to claim 1 of the present invention includes a first board provided with a functional element on one side, and a second board provided on one side of the first board via a first sealing portion. And a plurality of bumps provided on the other surface side of the first substrate and electrically connected to the functional element, wherein the first sealing portion is an outer periphery of the first substrate And is disposed at a position that does not overlap the bump bonding portion when viewed from the direction in which the first substrate and the second substrate overlap, and the functional element is provided on the first substrate. A second sealing portion is further provided in a second region that is provided in the inner envelope and surrounds the functional element, and the second sealing portion is viewed from a direction in which the first substrate and the second substrate overlap. The first substrate and the second substrate are arranged at positions that do not overlap the bump bonding portion. In the direction of the overlapping plane, a first cavity area is an area where the functional element is not present, and a second cavity area is an area where the functional element is present, said second sealing portion so as to divide The bump connection portions are provided in both areas.

A wiring board according to a second aspect of the present invention is the wiring board according to the first aspect, wherein a plurality of the first and second substrates are arranged in the second cavity area in a direction in an overlapping surface of the first board and the second board. The bump bonding portion is characterized in that each bump bonding portion is isolated by the second sealing portion.
A wiring board according to a third aspect of the present invention is the wiring board according to the second aspect, wherein the second sealing portion has a lattice shape.

The wiring board according to a fourth aspect of the present invention is the wiring board according to the first aspect , wherein the second sealing portion is a bump bonding portion in a direction in a plane where the first substrate and the second substrate overlap. It is arranged in a region that is not related to each other, and each second sealing portion is in an isolated state.

A method for manufacturing a wiring board according to claim 5 of the present invention is a method for manufacturing a wiring board according to any one of claims 1 to 4 , wherein the wiring board is in a second region surrounding the functional element. And the process C which forms a 2nd sealing part in the position which does not overlap with the said bump junction part seeing from the direction where said 1st board and said 2nd board overlap, and said 1st sealing part and said And a step D for joining the first substrate and the second substrate through a second sealing portion.

A method for manufacturing a wiring board according to claim 6 of the present invention is the method for manufacturing a wiring board according to claim 5, wherein the step C is performed in the direction in which the first substrate and the second substrate overlap. The second sealing portion is formed such that each of the plurality of bump bonding portions arranged in the second cavity area is in an isolated state.

According to a first aspect of the present invention, there is provided a wiring board including a functional board on one side and a first board having a plurality of bumps on the other side, and a second board arranged on one side of the first board. Is provided in a first region that forms the outer periphery of the first substrate, and is disposed in a position that does not overlap the bump bonding portion when viewed from the direction in which the first substrate and the second substrate overlap. It is joined by the part.
Further, the functional element is provided in an inner envelope of the first substrate, a second region surrounding the functional element is further provided with a second sealing portion, and the second sealing portion is When viewed from the direction in which one substrate and the second substrate overlap, the functional element is disposed in a position in which the first substrate and the second substrate overlap in a direction that does not overlap with the bump bonding portion. The second sealing portion is arranged to divide the first cavity area, which is a non-performing area, and the second cavity area, which is an area where the functional element is present, in both areas, There is a bump connection.
Therefore, when the mounting substrate is deformed by thermal expansion, the bonded portion of the first substrate and the second substrate is not easily deformed when viewed from the overlapping direction of the first substrate and the second substrate. The location where the first substrate and the second substrate, which are arranged at positions where they do not overlap and the mounting substrate easily deforms due to thermal expansion, is not bonded, is bump bonding as seen from the direction in which the first substrate and the second substrate overlap. It exists in the position which overlaps with the part. As a result, the stress applied to the bump bonding portion due to the deformation due to the thermal expansion of the mounting substrate can be dispersed in the portion where the first substrate and the second substrate are not bonded.
In particular, the second sealing portion is arranged to divide a first cavity area that is a region where the functional element does not exist and a second cavity area that is a region where the functional element exists. Therefore, in consideration of the deformation due to the thermal expansion of the mounting substrate described above, it is possible to use the bump connecting portions arranged in both areas separately.
Therefore, in the wiring board having the bonding structure, the stress applied to the bump after being mounted on the mounting board can be relaxed, and a wiring board with improved mounting reliability can be obtained. In addition, since the wiring board inner enclosure is sealed by the first sealing portion and the second sealing portion, the functional element can be protected and stable operation of the functional element can be obtained.

According to a fifth aspect of the present invention, there is provided a method for manufacturing a wiring board, wherein the wiring board is located in a second region surrounding the functional element and does not overlap the bump bonding portion when viewed from the direction in which the first board and the second board overlap. A second sealing portion is formed on the first substrate (step C), and the first sealing portion provided in the first region forming the outer periphery of the first substrate and the first sealing portion via the second sealing portion. The substrate and the second substrate are bonded (step D). Therefore, it is possible to disperse the stress applied to the bump bonding portion due to the deformation due to the thermal expansion of the mounting substrate, and to improve the mounting reliability of the wiring substrate and to perform the bonding between the first substrate and the second substrate. The sealing portion and the second sealing portion can be easily provided.
Therefore, it is possible to easily provide a method for manufacturing a wiring board with improved mounting reliability at the wafer level.

(First embodiment)
Hereinafter, based on the best mode, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view schematically showing an example of a wiring board according to the present invention, and FIG. 2 is a cross-sectional view schematically showing a state in which the wiring board is mounted on a mounting board. In other embodiments to be described later, the same reference numerals are used for the same components as in the present embodiment, and the description thereof will be omitted.

  A wiring board (wafer level package) 10 according to this embodiment overlaps a first substrate 11 having a functional element 12 on one surface and a functional element 12 of the first substrate 11 as shown in FIGS. As described above, the second substrate 16 disposed on one surface, the first substrate 11 and the second substrate 16 are sandwiched between the functional elements 12 so as to form a cavity 18. The first sealing portion 17 is provided.

  Further, in the wiring board 10 according to the present embodiment, the first substrate 11 is disposed on the other surface, and contacts (hereinafter referred to as “bumps”) for electrically accessing (connecting) the functional element 12. 19 and a conductive layer 13 connected thereto. A through-wiring 15 for electrically connecting the functional element 12 and the conductive layer 13 is formed between one surface and the other surface of the first substrate 11. Further, a sealing resin layer 14 is formed on the other surface of the first substrate 11 except for the region where the bumps 19 are disposed.

  In the wiring board 10 according to the present embodiment, the first sealing portion 17 is in the first region forming the outer periphery of the first substrate 11, and the first substrate 11 and the second substrate 16. When viewed from the overlapping direction, it is characterized in that it is arranged at a position that does not overlap with the bump bonding portion, specifically, outside the bump position provided on the outermost periphery of the plurality of bumps provided. Here, the bump bonding portion means a portion where the bump 19 is in contact with the conductive layer 13.

The first substrate 11 has a passivation film (not shown) and a functional element 12 formed on the surface of a base material made of a semiconductor material such as Si or GaAs. The passivation film is an insulating film formed by passivation made of SiN, SiO ₂ or the like.
Further, the first substrate 11 preferably has a smaller substrate thickness, for example, a thickness of 100 to 200 μm. If the thickness is 100 μm or less, the strength of the substrate cannot be maintained if it is too thin. On the other hand, if the thickness is 200 μm or more, the stress relaxation to the bumps is inferior.

  The functional element 12 is a place responsible for the central function of the device, corresponds to an area for converting a physical change applied to the first substrate 11 into an electrical signal, and has a fine three-dimensional structure, For example, a solid-state image sensor that functions as an image sensor such as a CCD or a CMOS.

  The conductive portion 13 is a surface wiring layer for transmitting an electrical signal from the functional element 12, and for example, a conductive material such as Cu is preferably used. The conductive portion 13 is electrically connected to a through wiring 15 described later.

  The sealing resin layer 14 covers the other surface of the first substrate 11 except for the region where the bumps 19 are disposed. Examples of the material forming the sealing resin layer 14 include resins such as epoxy and polyimide.

  The through wiring 15 is a wiring penetrating the first substrate 11 and is preferably made of a conductive material such as Cu, Al, AuSn, for example. The through wiring 15 is formed by, for example, applying the conductive material into a hole formed through one surface of the first substrate 11 from the other surface by a molten metal suction method, a printing method, a plating method, or the like. Can be formed.

  The second substrate 16 is a member for protecting the functional element 12 provided on the first substrate 11, and is supported by the first substrate 11 via the first sealing portion 17. A cavity 18 is formed around the periphery. The second substrate 16 may be formed of an insulator such as glass.

The first sealing portion 17 is a member that joins the first substrate 11 and the second substrate 16 at the wafer level, and is also a member that separates the functional element 12 and the second substrate 16. The first sealing portion 17 is formed of a resin, metal, glass, silicon, or the like having a thickness of about 1 to 100 μm, for example. Further, the first substrate 11 and the second substrate 16 are joined via the first sealing portion 17 by, for example, adhesive bonding such as epoxy, polyimide and BCB, glass frit bonding, eutectic bonding such as Au and Sn. Various bonding methods such as solder bonding and anodic bonding can be employed.
The region on the wiring board 10 provided with the first sealing portion 17 constitutes an adhesive area 31 that is not easily deformed when a mounting board 21 described later thermally expands.
In addition, since the 1st sealing part 17 is not distribute | arranged on the surface of the functional element 12, you may not have a light transmittance.

The cavity 18 is formed by joining the first substrate 11 and the second substrate 16 with the first sealing portion 17 interposed between the first substrate 11 and the second substrate 16. A space surrounded by 17.
The area on the wiring board 10 in which the cavity 18 is formed constitutes a cavity area 32 that easily deforms when a mounting board 21 to be described later thermally expands and disperses and relaxes the stress applied to the bump bonding portion. The photoelectric conversion portion of the functional element 12 constitutes an image area 33.

  The bump 19 electrically connects the conductive portion 13 of the first substrate 11 and a conductive portion 23 of the mounting substrate 21 described later, and can be formed by a known method such as solder paste printing or solder ball mounting. it can.

The mounting substrate 21 includes a conductive layer 23 for electrically connecting to the bumps 19 provided on the wiring substrate 10 on one surface thereof.
The conductive portion 23 is a rewiring layer disposed on one surface of the mounting substrate 21. For example, a conductive material such as Cu, Ni, or Au is preferably used.

In this way, the first bonding portion 17 is in the first region that forms the outer periphery of the first substrate 11, and the bump bonding portion is viewed from the direction in which the first substrate 11 and the second substrate 16 overlap. By being arranged in a position that does not overlap, the bonding area 31 that is difficult to be deformed on the package side when the mounting substrate 21 is thermally expanded is present to avoid a bump bonding portion that tends to cause a decrease in mounting reliability. On the other hand, in the image area 33 and the cavity area 32 where the bump bonding portion is present, the first substrate 11 and the second substrate 16 are not bonded. Therefore, when the mounting substrate 21 is thermally expanded, the Si on the package side Can be easily deformed, and the stress applied to the bump joint can be dispersed and relaxed.
Therefore, it is possible to improve the mounting reliability in the wiring board having the bonding structure.

  Further, by bonding the first substrate 11 and the second substrate 16 by the first sealing portion 17, it is possible to make the wiring substrate inclusion area in which the functional element is formed isolated from other areas. Therefore, it is possible to ensure good sealing performance, prevent deterioration of the functional element, and obtain a stable operation and long life of the functional element.

Next, a method for manufacturing the wiring board 10 having the above configuration will be described. 3 and 4 are explanatory views showing the manufacturing method step by step. Hereinafter, the first substrate 11 will be described as an Si substrate, and the second substrate 16 as a glass substrate.
First, in manufacturing the wiring substrate 10, as shown in FIG. 3A, a functional element 12 such as a solid-state imaging device that functions as an image sensor such as a CCD or CMOS is formed on one surface of the Si substrate 11. .

Next, as shown in FIG. 3 (b), it is in the first region that forms the outer periphery of one surface of the Si substrate 11, and is viewed from the direction in which the glass substrate 16 to be bonded later to the Si substrate 11 overlaps. The first sealing portion 17 is formed at a position that does not overlap with a bump bonding portion to be formed later.
Next, as shown in FIG. 3C, the glass substrate 16 is disposed on the first sealing portion 17, the Si substrate 11 and the glass substrate 16 are overlapped, and the first sealing portion 17 is interposed therebetween. The Si substrate 11 and the glass substrate 16 are bonded together. This bonding can be performed, for example, by performing a hot press process while the Si substrate 11 and the glass substrate 16 are overlapped and melting the first sealing portion 17.

Thereafter, as illustrated in FIG. 3D, the through wiring 15 that is electrically connected to the functional element 12 is formed in the Si substrate 11. Such a through wiring 15 may be, for example, a conductive material filled in the through hole.
Next, as shown in FIG. 4A, the conductive layer 13 connected to the through wiring 15 is formed on the other surface of the Si substrate 11, and then the insulating layer is covered with an insulating sealing resin layer 14. . However, an opening is provided in the sealing resin layer 14 at a portion to be a bump bonding portion to be formed later.

Further, as shown in FIG. 4B, a bump material is disposed on the conductive layer 13 on the other surface of the Si substrate 11 and exposed to the sealing resin layer 14 through the opening, and the bump material is melted. In addition, the wiring board 10 can be formed by forming the bumps 19.
Thereafter, as shown in FIG. 4C, the bumps 19 of the wiring substrate 10 are arranged toward the conductive layer 23 formed on one surface of the mounting substrate 21, and the bumps 19 are melted to be electrically connected to the conductive layer 23. By connecting, the wiring board 10 can be mounted on the mounting board 21 as shown in FIG.

  Thus, in the manufacturing method according to the present invention, the first sealing portion capable of bonding the Si substrate and the glass substrate can be easily provided, and bump bonding is performed by deformation due to thermal expansion of the mounting substrate after mounting. It is possible to easily provide a method of manufacturing a wiring board that can disperse the stress applied to the portion and improve the mounting reliability of the wiring board.

(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 5 is a plan view schematically showing another example of the wiring board according to the present invention, and FIG. 6 is a cross-sectional view schematically showing a state in which the wiring board is mounted on the mounting board.
As shown in FIGS. 5 and 6, the wiring board (wafer level package) 40 in the present embodiment further includes the functional element 12 provided in the inclusion of the first board 11 in addition to the wiring board 10 in the first embodiment. A second sealing portion 47 is provided in the second region to be surrounded.

  In the wiring board 40 according to the present embodiment, the second sealing portion 47 is disposed at a position where the second sealing portion 47 does not overlap the bump bonding portion when viewed from the direction in which the first substrate 11 and the second substrate 16 overlap. And

The second sealing portion 47 is a member that joins the first substrate 11 and the second substrate 16 at the wafer level and also a member that ensures better airtight sealing of the functional element 12. The second sealing portion 47 is formed of, for example, a resin, metal, glass, silicon or the like having a thickness of about 1 to 100 μm. Moreover, when the 2nd sealing part 47 consists of the same material as said 1st sealing part 17, you may distribute | arrange separately, but can also distribute | arrange together. Since the second sealing portion 47 is arranged so as to surround the functional element 12, a material having low moisture permeability and low hygroscopicity is desirable.
The area on the wiring board 40 provided with the second sealing portion 47 is similar to the bonding area 31 on the wiring board 40 provided with the first sealing portion 17 and the mounting board 21 described later is heated. An adhesive area 34 that does not easily deform when expanded is formed.

Further, by forming the second sealing portion 47, a first cavity 48 surrounded by the first sealing portion 17 and a second cavity 58 surrounded by the second sealing portion 47 are produced. The A region on the wiring substrate 40 in which the cavities 48 and 58 are formed is easily deformed when a mounting substrate 21 to be described later thermally expands, and a first cavity area 32 that disperses and relaxes stress applied to the bump bonding portion. A second cavity area 35 is formed.
That is, the second sealing portion 47 is arranged so as to separate the first cavity area 32 that is a region where the functional element 12 is not present and the second cavity area 35 that is a region where the functional element 12 is present. ing. Thus, FIG. 5 shows that there are a plurality of bump connecting portions in both areas (first cavity area 32 and second cavity area 35).
Further, as apparent from FIG. 5, the bump connection portion in the second cavity area 35 is arranged at a position overlapping the image area 33 when viewed from the direction in which the first substrate 11 and the second substrate 16 overlap. On the other hand, the bump connection portion in the first cavity area 32 is at a position not overlapping the image area 33.
Therefore, the bump connection portion in the first cavity area 32 that is disposed at a position not overlapping the image area 33 is thermally expanded in comparison with the bump connection portion in the second cavity area 35. It is hard to be affected by the deformation.
In the present embodiment, only two cavities are produced. However, a configuration may be adopted in which a third cavity or a larger number of cavities are produced in a portion other than the image area 33 described later.

FIG. 9 is a model diagram illustrating a configuration example in which a large number of cavities are provided. In FIG. 9A to FIG. 9G, basically, a small white circle region represents a bump joint, a sand pattern region represents a sealing portion, and the other region represents a cavity area. ing.
In FIG. 9A, a plurality (9 in the figure) of bump joints are individually arranged in an isolated state by a lattice-shaped sealing part, and between each bump joint part and the sealing part. This is a configuration example in which a cavity area is provided. Here, the lattice-shaped sealing portions are arranged so as to partition the individual bump bonding portions in the vertical and horizontal directions.
FIG. 9B basically has the same configuration as FIG. 9A. However, this is a configuration example different from FIG. 9A in that the cavity area is arranged substantially concentrically only along the outer peripheral area of the bump bonding portion.
FIG. 9C basically has the same configuration as FIG. However, the configuration in which the intersecting portion of the lattice-shaped sealing portion is replaced with a cavity area is a configuration example different from FIG.
FIG. 9D basically has almost the same configuration as FIG. However, the configuration example is different from FIG. 9B in that a cavity area is additionally provided in a region of the sealing portion that is not related to the bump bonding portion. Here, the added cavity area is represented by a white square mark.
FIG. 9E shows a configuration example in which a sealing portion is arranged in a region unrelated to the position of the bump bonding portion, and each sealing portion is isolated. The sealing portion in FIG. 9 (e) is particularly represented by a square mark with a sand pattern. That is, it shows that the sealing part is a rectangular pattern.
FIG. 9 (f) basically has the same configuration as FIG. 9 (e). However, the sealing portion in FIG. 9 (f) is particularly indicated by a sand pattern circle. That is, the sealing part has a circular pattern. Therefore, FIG. 9F is a configuration example in which the pattern of the sealing portion is different from that in FIG.
FIG. 9G basically has the same configuration as FIG. 9A. However, this is a configuration example different from FIG. 9A in that the lattice-shaped sealing portions are arranged so as to divide the individual bump bonding portions in an oblique direction.

As described above, the second bonding portion 47 is disposed at a position where the second bonding portion 47 does not overlap with the bump bonding portion when viewed from the direction in which the first substrate 11 and the second substrate 16 overlap with each other. The intrusion of gas or the like can be prevented, the sealing performance of the wiring board can be improved, and the bonding area 34 in which the package side is less likely to be deformed when the mounting board 21 is thermally expanded reduces the mounting reliability. The bump joints that are easily rubbed are avoided to exist. On the other hand, in the image area 33, the first cavity area 32, and the second cavity area 35 where the bump bonding portion exists, the mounting substrate 21 is thermally expanded because the first substrate 11 and the second substrate 16 are not bonded. In this case, the Si substrate on the package side is easily deformed, and the stress applied to the bump bonding portion can be dispersed and relaxed.
Therefore, it is possible to improve the mounting reliability in the wiring board having the bonding structure.

  Further, the bonding of the first substrate 11 and the second substrate 16 by the second sealing portion 47 improves the sealing performance of the functional element, and the first substrate (for example, Si substrate) 11 and the second substrate. By increasing the number of adhesion portions (for example, glass substrate) 16, damage to the thinned Si substrate due to impact or the like can be suppressed. Therefore, deterioration of the functional element can be prevented, and more stable operation and long life of the functional element can be obtained.

Next, a method for manufacturing the wiring board 40 having the above configuration will be described. FIG. 7 is explanatory drawing which shows the manufacturing method in steps. Hereinafter, also in this embodiment, the 1st board | substrate 11 is demonstrated as a Si substrate and the 2nd board | substrate 16 is demonstrated as a glass substrate.
First, as shown in FIG. 7A, the process up to the step of forming the functional element 12 such as a solid-state imaging element functioning as an image sensor such as a CCD or CMOS on one surface of the Si substrate 11 is performed in the first embodiment. This is the same as the wiring board 10 in FIG.

Next, as shown in FIG. 7 (b), it is in the first region that forms the outer periphery of one surface of the Si substrate 11, and is viewed from the direction in which the glass substrate 16 to be bonded later to the Si substrate 11 overlaps. The first sealing portion 17 is formed at a position that does not overlap with a bump bonding portion to be formed later. Further, the second sealing portion 47 is formed at a position in the second region surrounding the functional element 12 and not overlapping with the bump bonding portion when viewed from the direction in which the Si substrate 11 and the glass substrate 16 overlap. . The formation of the first sealing portion 17 and the second sealing portion 47 may be performed together or separately.
Next, as shown in FIG. 7C, the glass substrate 16 is disposed on the first sealing portion 17 and the second sealing portion 47, and the Si substrate 11 and the glass substrate 16 are overlapped, The Si substrate 11 and the glass substrate 16 are bonded via the first sealing portion 17 and the second sealing portion 47. This bonding can be performed, for example, by performing a hot press process while the Si substrate 11 and the glass substrate 16 are overlapped and melting the first sealing portion 17 and the second sealing portion 47.

Thereafter, as illustrated in FIG. 7D, the through wiring 15 that is electrically connected to the functional element 12 is formed in the Si substrate 11. Such a through wiring 15 may be, for example, a conductive material filled in the through hole.
Next, as shown in FIG. 8A, the conductive layer 13 connected to the through wiring 15 is formed on the other surface of the Si substrate 11, and then the insulating layer is covered with an insulating sealing resin layer 14. . However, an opening is provided in the sealing resin layer 14 at a portion to be a bump bonding portion to be formed later.

Further, as shown in FIG. 8B, a bump material is disposed on the conductive layer 13 on the other surface of the Si substrate 11 and exposed to the sealing resin layer 14 through the opening, and the bump material is melted. In addition, the wiring board 40 can be formed by forming the bumps 19.
Thereafter, as shown in FIG. 8C, the bumps 19 of the wiring board 40 are arranged toward the conductive layer 23 formed on one surface of the mounting substrate 21, and the bumps 19 are melted to be electrically connected to the conductive layer 23. By connecting, the wiring board 40 can be mounted on the mounting board 21 as shown in FIG.

  Thereby, in the manufacturing method by this invention, while being able to provide easily the 1st sealing part and the 2nd sealing part which can join a Si substrate and a glass substrate, the mounting board | substrate after mounting is mounted. To easily provide a method of manufacturing a wiring board that can disperse stress applied to the bump joint due to deformation caused by thermal expansion, improve the mounting reliability of the wiring board, and further improve the hermetic sealing performance of the functional element. Can do.

  In addition, the gas generated during the hot press process for bonding the Si substrate and the glass substrate can be prevented from entering the image area and the second cavity area, and a package structure without deterioration in characteristics can be obtained.

  The present invention can be applied to a wiring board having a structure in which a substrate such as glass is bonded to an optical semiconductor device including a functional element such as a solid-state imaging element that functions as an image sensor such as a CCD or CMOS.

It is a figure which shows an example of the wiring board which concerns on this invention. It is a figure which shows the cross section of the state which mounted the wiring board shown in FIG. It is a figure which shows an example of the manufacturing method of the wiring board which concerns on this invention in process order. It is a figure which shows each process following FIG. It is a figure which shows the other example of the wiring board which concerns on this invention. It is a figure which shows the cross section of the state which mounted the wiring board shown in FIG. It is a figure which shows an example of the other manufacturing method of the wiring board which concerns on this invention in process order. It is a figure which shows each process following FIG. It is a model figure which shows the structural example which provides many cavities. It is a figure which shows the cross section of the state which mounted the conventional semiconductor substrate. It is a figure which shows the cross section of the state which mounted the conventional wiring board. It is a figure which shows the cross section of the state which mounted the conventional wiring board. It is a figure which shows the plane of the state which mounted the conventional wiring board.

Explanation of symbols

  10, 40 Wiring substrate, 11 First substrate (semiconductor substrate), 12 Functional element, 13 Conductive layer, 14 Sealing resin layer, 15 Through wiring, 16 Second substrate (glass substrate), 17 First sealing portion, 47 Second sealing portion, 18, 48, 58 cavity, 19 bump, 21 mounting substrate, 23 conductive layer, 31, 34 bonding area, 32, 35 cavity area, 33 image area.

Claims (6)

A first substrate with functional elements on one side;
A second substrate provided on one surface side of the first substrate via a first sealing portion;
In the wiring board comprising a plurality of bumps provided on the other surface side of the first substrate and electrically connected to the functional element,
The first sealing portion is provided in a first region that forms an outer periphery of the first substrate, and is disposed at a position that does not overlap the bump bonding portion when viewed from the direction in which the first substrate and the second substrate overlap. As well as
The functional element is provided in an inner package of the first substrate,
A second sealing portion is further provided in the second region surrounding the functional element, and the second sealing portion is formed by the bump bonding as viewed from the direction in which the first substrate and the second substrate overlap. It is arranged in a position that does not overlap the part,
In a direction in a plane where the first substrate and the second substrate overlap, a first cavity area that is a region where the functional element does not exist and a second cavity area that is a region where the functional element exists are separated. Thus, the second sealing portion is arranged, and the bump connection portion is provided in each of both areas. In the direction in the plane where the first substrate and the second substrate overlap , the plurality of bump bonding portions arranged in the second cavity area are isolated from each other by the second sealing portion. The wiring board according to claim 1, wherein the wiring board is in a finished state.   The wiring board according to claim 2, wherein the second sealing portion has a lattice shape. In the direction in the plane where the first substrate and the second substrate overlap, the second sealing portion is arranged in a region not related to the bump bonding portion, and each second sealing portion is isolated. The wiring board according to claim 1, wherein the wiring board is in a finished state. A method for manufacturing a wiring board according to any one of claims 1 to 4,
Forming a second sealing portion at a position in the second region surrounding the functional element and not overlapping with the bump bonding portion when viewed from the overlapping direction of the first substrate and the second substrate; C
Step D for joining the first substrate and the second substrate through the first sealing portion and the second sealing portion;
A method for manufacturing a wiring board, comprising:   In the step C, in the direction in which the first substrate and the second substrate overlap, the second sealing is performed so that the plurality of bump bonding portions arranged in the second cavity area are in an isolated state. The method for manufacturing a wiring board according to claim 5, wherein a portion is formed.

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