JP5111342B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP5111342B2 JP5111342B2 JP2008306900A JP2008306900A JP5111342B2 JP 5111342 B2 JP5111342 B2 JP 5111342B2 JP 2008306900 A JP2008306900 A JP 2008306900A JP 2008306900 A JP2008306900 A JP 2008306900A JP 5111342 B2 JP5111342 B2 JP 5111342B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- conductor layer
- wiring board
- conductor
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
11…コア材
11a…収容穴部
12…第1配線積層部
13…第2配線積層部
14、15、16、17…樹脂絶縁層
18、19…ソルダーレジスト層
21、22、23、24…導体層
25…端子パッド
26…BGA用パッド
30…スルーホール導体
31…樹脂
32、33、34、35…ビア導体
40…半田バンプ
41…半田ボール
50…樹脂充填材
60、60a…グランド配線
61…信号配線
62…ギャップ部
63…ダミー配線
100…チップコンデンサ
200…半導体チップ
201…パッド
R1…充填領域
Claims (9)
- 搭載部品を載置し、当該搭載部品と外部基板との間を電気的に接続する配線基板であって、
上面及び下面を貫通する収容穴部を開口したコア材と、
前記コア材の上面側に絶縁層及び導体層を交互に積層形成し、前記搭載部品に接続される複数の接続端子を有する第1配線積層部と、
前記コア材の下面側に導体層及び絶縁層を交互に積層形成し、外部接続用の複数の電極パッドを有する第2配線積層部と、
前記収容穴部に収容されたチップ部品と、
前記収容穴部と前記チップ部品の側面との間隙に充填された樹脂充填材と、
を備え、前記第1配線積層部は、他の導体層に比べて厚さが厚い少なくとも1つの第1導体層を含み、前記第2配線積層部は、他の導体層に比べて厚さが厚い少なくとも1つの第2導体層を含み、前記第1導体層及び前記第2導体層には、前記樹脂充填材の充填領域と積層方向で対向する領域に配線が形成されていることを特徴とする配線基板。 - 前記第1導体層及び前記第2導体層は、前記樹脂充填材の充填領域と積層方向で対向する領域のうち部分的に配線が形成されないギャップ部を有し、前記充填領域の長手方向で前記ギャップ部のサイズが十分小さくなるように形成されることを特徴とする請求項1に記載の配線基板。
- 前記第1導体層及び前記第2導体層は、厚さ25μm以上の銅層であることを特徴とする請求項1又は2に記載の配線基板。
- 前記第1導体層及び前記第2導体層のうち、前記樹脂充填材の充填領域と積層方向で対向する領域に形成された配線は、電源又はグランドに接続されることを特徴とする請求項1から3のいずれかに記載の配線基板。
- 前記第1導体層及び前記第2導体層のうち、前記樹脂充填材の充填領域と積層方向で対向する領域には、フローティング状態のダミー配線が形成されることを特徴とする請求項1から3のいずれかに記載の配線基板。
- 前記チップ部品は、前記樹脂充填材に比べて剛性が高い材料を用いて形成されていることを特徴とする請求項1から5のいずれかに記載の配線基板。
- 前記チップ部品は、セラミック焼結体を用いて構成されたチップコンデンサであることを特徴とする請求項6に記載の配線基板。
- 前記チップコンデンサの上面には前記第1配線積層部の導体層に接続される複数の電極が形成され、前記チップコンデンサの下面には前記第2配線積層部の導体層に接続される複数の電極が形成されることを特徴とする請求項7に記載の配線基板。
- 前記搭載部品は、半導体チップであることを特徴とする請求項1に記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008306900A JP5111342B2 (ja) | 2008-12-01 | 2008-12-01 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008306900A JP5111342B2 (ja) | 2008-12-01 | 2008-12-01 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010129992A JP2010129992A (ja) | 2010-06-10 |
JP5111342B2 true JP5111342B2 (ja) | 2013-01-09 |
Family
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JP2008306900A Expired - Fee Related JP5111342B2 (ja) | 2008-12-01 | 2008-12-01 | 配線基板 |
Country Status (1)
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Cited By (13)
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US10886232B2 (en) | 2019-05-10 | 2021-01-05 | Applied Materials, Inc. | Package structure and fabrication methods |
US10937726B1 (en) | 2019-11-27 | 2021-03-02 | Applied Materials, Inc. | Package structure with embedded core |
US11063169B2 (en) | 2019-05-10 | 2021-07-13 | Applied Materials, Inc. | Substrate structuring methods |
US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9704793B2 (en) | 2011-01-04 | 2017-07-11 | Napra Co., Ltd. | Substrate for electronic device and electronic device |
JP2012204831A (ja) | 2011-03-23 | 2012-10-22 | Ibiden Co Ltd | 電子部品内蔵配線板及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
JP2007318089A (ja) * | 2006-04-25 | 2007-12-06 | Ngk Spark Plug Co Ltd | 配線基板 |
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2008
- 2008-12-01 JP JP2008306900A patent/JP5111342B2/ja not_active Expired - Fee Related
Cited By (28)
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US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
US11476202B2 (en) | 2019-05-10 | 2022-10-18 | Applied Materials, Inc. | Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration |
US11063169B2 (en) | 2019-05-10 | 2021-07-13 | Applied Materials, Inc. | Substrate structuring methods |
US10886232B2 (en) | 2019-05-10 | 2021-01-05 | Applied Materials, Inc. | Package structure and fabrication methods |
US12051653B2 (en) | 2019-05-10 | 2024-07-30 | Applied Materials, Inc. | Reconstituted substrate for radio frequency applications |
US11264331B2 (en) | 2019-05-10 | 2022-03-01 | Applied Materials, Inc. | Package structure and fabrication methods |
US11264333B2 (en) | 2019-05-10 | 2022-03-01 | Applied Materials, Inc. | Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration |
US11362235B2 (en) | 2019-05-10 | 2022-06-14 | Applied Materials, Inc. | Substrate structuring methods |
US11398433B2 (en) | 2019-05-10 | 2022-07-26 | Applied Materials, Inc. | Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration |
US11887934B2 (en) | 2019-05-10 | 2024-01-30 | Applied Materials, Inc. | Package structure and fabrication methods |
US11715700B2 (en) | 2019-05-10 | 2023-08-01 | Applied Materials, Inc. | Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration |
US11417605B2 (en) | 2019-05-10 | 2022-08-16 | Applied Materials, Inc. | Reconstituted substrate for radio frequency applications |
US11521935B2 (en) | 2019-05-10 | 2022-12-06 | Applied Materials, Inc. | Package structure and fabrication methods |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
US12087679B2 (en) | 2019-11-27 | 2024-09-10 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US10937726B1 (en) | 2019-11-27 | 2021-03-02 | Applied Materials, Inc. | Package structure with embedded core |
US11881447B2 (en) | 2019-11-27 | 2024-01-23 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11742330B2 (en) | 2020-03-10 | 2023-08-29 | Applied Materials, Inc. | High connectivity device stacking |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11927885B2 (en) | 2020-04-15 | 2024-03-12 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
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JP2010129992A (ja) | 2010-06-10 |
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