JP5110445B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device whose electrical characteristics are improved by forming a semiconductor device in an epitaxial phase on a silicon carbide substrate in which the crystal plane orientation of the substrate is defined and fine surface irregularities are suppressed. .

  Regarding the semiconductor device formed in the silicon carbide region of the semiconductor substrate and the manufacturing method thereof, several presentations have already been made or inventions have been disclosed, as will be described below. These conventional semiconductor devices using a substrate having a silicon carbide region usually have a structure in which a gate electrode is formed on the (0001) plane of the silicon carbide region. In general, when a P-type or N-type region is formed by ion implantation in the (0001) plane of a silicon carbide region, after ion implantation of a P-type or N-type impurity, activation is performed at a high temperature of 1500 ° C. or higher. Heat treatment is performed. At this time, it is known that silicon evaporates from the silicon carbide surface, and fine irregularities on the silicon carbide surface increase.

  As a result, Schottky barrier diodes (metal-insulator-semiconductor field-effect transistors (MISFETs) and metal-semiconductor field-effect transistors (MESFETs)) due to a decrease in channel mobility and an increase in crystal defects in the ion implantation region ( SBD) and junction field effect transistors (JFETs) have a large leakage current, and there is a problem that they cannot be used in practice. Up to now, the formation of the epitaxial layer on the SiC substrate has been mainly performed on the (0001) plane, but on the substrate which is off by 3.5 ° for 6H-SiC and 8 ° for 4H-SiC. Otherwise, an epitaxial layer could not be formed. In addition, when an epitaxial layer is formed on the (0001) just plane, the supersaturation degree of molecular species including Si and C is increased, two-dimensional nuclei are generated, and 3C-SiC, which is a stable polytype at a low temperature, is formed. As a result, an epitaxial layer could not be formed on the hexagonal bulk substrate. When there is an off-angle of 3.5 ° or 8 °, the unevenness of the interface between the electrode or gate insulating film and the silicon carbide is large, and there is a problem of deteriorating the electrical characteristics of the semiconductor element.

For example, in Non-Patent Document 1, since the impurity activation heat treatment is performed at a high temperature, step bunching occurs, the surface unevenness increases, and the on-resistance value of the 4H-SiC power MOSFET decreases to the theoretical value. Describes that channel mobility of 100 cm ² / Vs or more is required, but it can only be 1 cm ² / Vs or less.

Further, in Non-Patent Document 2, in a DiMOSFET type SiC power MOSFET, a channel mobility is set to 22 cm ² / Vs at room temperature in order to perform heat treatment at around 1600 ° C. after ion implantation of a P-type impurity (aluminum). It is described that this is only possible.

Further, in Non-Patent Document 3, in a lateral DMOSFET type SiC power MOSFET, channel activation is performed from 4 in order to perform activation heat treatment at 1600 ° C. for 40 minutes after ion implantation of P-type impurities (aluminum). It is described that it can only be about 5 cm ² / Vs.

  On the other hand, Non-Patent Document 4 reports that a MOSFET is formed and operated using channel doping in which impurities are implanted under the gate oxide film on the (000-1) plane of 6H—SiC. Only the N-type semiconductor region is formed by ion implantation, and the gate oxide film is formed by dry oxidation, which is different in structure from the semiconductor device described in the following embodiments.

Patent Document 1 discloses a technique for forming an epitaxial layer on a bulk substrate inclined at 3 ° or more in the <11-20> direction. Patent Document 2 discloses a technique for forming an epitaxial layer on a bulk substrate tilted by 1 ° or more. Patent Document 3 describes a technique for forming an epitaxial layer on a substrate inclined at 2 ° or more in the <1-100> direction. In any case, a large inclination is required, and the unevenness of the interface between the electrode or the gate insulating film and the silicon carbide becomes large, thereby deteriorating the reliability of the gate insulating film and increasing the leakage current of the electrode.

J.A.Cooper, Jr., M.R.Melloch, R.Singh, A.Agarawal, J.W.Palmour, Statusand Prospects for SiC Power MOSFETs, IEEE Transaction on electron devices, vol.49, No.4, April 2002, p.658 SHRyu, A. Agarwal, J. Richmond, J. Palmour, N. Saks, and J. Williams, 10A, 2.4kV Power DiMOSFETs in 4H-SiC, IEEE Electron device letters, vol. 23, No. 6, June 2002, p .321 J.Spitz, M.R.Melloch, J.A.Cooper, Jr., M.A.Capano, 2.6kV 4H-SiC Lateral DMOSFET's, IEEE Electron device letters, vol.19, No.4, April1998, p.100 S.Ogino, T.Oikawa, K.Ueno, Channel Doped SiC-MOSFETs, Mat.Sci.Forum, 338-342, (2000), p.1101

US Pat. No. 4,912,064 US Pat. No. 5,011,549 US Pat. No. 6,329,088

  Thus, from the description of each of the above documents, a semiconductor device having a P-type region and an N-type region in which impurities are formed by ion implantation on a silicon carbide semiconductor substrate is formed on the (0001) plane. However, silicon carbide substrates have various plane orientations, and by devising the plane orientation and the heat treatment method of the impurities in the plane orientation, the state of the substrate before forming the epitaxial layer, and the method of forming the epitaxial layer, the impurity There is a possibility that the electrical characteristics of the semiconductor device can be improved by suppressing the unevenness of the silicon carbide substrate surface after the activation heat treatment.

  The present invention has been proposed in view of the above, and in a semiconductor device using a silicon carbide semiconductor substrate having P-type and N-type impurity semiconductor regions formed by ion implantation, the surface roughness of the silicon carbide semiconductor substrate is reduced. Thus, it is an object to finally improve the electrical characteristics of the semiconductor device.

In order to achieve the above object, a first feature of the present invention relates to a diode,
A semiconductor device formed on a silicon carbide semiconductor substrate, the substrate being grown on a surface inclined by less than 1 ° and more than 0 ° from a (000-1) plane of a silicon carbide semiconductor substrate having a 4H crystal structure In the epitaxial layer, at least one of the P-type semiconductor region and the N-type semiconductor region is selectively formed by ion implantation, and contacts the surface layer of the P-type semiconductor region or the N-type semiconductor region. a metal electrode to be formed, showing the rectifying action between the metal electrode and the epitaxial layer, a Schottky barrier diode door Rui is that it is P N-type diode.

In addition, since a transistor with improved performance can be realized, a second feature is a semiconductor device formed on a silicon carbide semiconductor substrate having a 4H crystal structure , and the substrate is a silicon carbide semiconductor. It has an epitaxial layer grown on a surface tilted by more than 0 ° and less than 1 ° from the (000-1) plane of the substrate, and at least one of the P-type semiconductor region and the N-type semiconductor region is ion-implanted in the epitaxial layer. And a metal electrode is formed so as to be in contact with the surface layer of the P-type semiconductor region or the N-type semiconductor region, and the metal electrode constitutes a gate electrode and is adjacent to the gate electrode. A MES type field effect transistor or a junction type field effect transistor in which a source region and a drain region are formed at a position sandwiching the gate electrode , It is that it is. When the inclination is 1 ° or more, the unevenness between the electrode and the silicon carbide substrate is large, the stability of the electrode is deteriorated, and the leakage current increases. Therefore, the tilt angle is limited to more than 0 ° and less than 1 °.

Since the gate insulating film can be modified by containing hydrogen, the third feature is a semiconductor device formed on a silicon carbide semiconductor substrate having a 4H crystal structure , and the substrate is made of silicon carbide. An epitaxial layer grown on a plane inclined by more than 0 ° and less than 1 ° from the (000-1) plane of the semiconductor substrate, and at least one of the P-type semiconductor region and the N-type semiconductor region is an ion in the epitaxial layer. A gate insulating film is formed selectively by implantation and formed on the surface layer of the P-type semiconductor region or the N-type semiconductor region, and the gate insulating film is a silicon oxide film, and the silicon carbide substrate of the silicon oxide film The layer in contact with the gate electrode is formed by thermally oxidizing the above epitaxial layer in an atmosphere containing water, and the hydrogen density in the gate insulating film has a maximum cubic centimeter. And a 1.0 × ^{10 19} or more per meter, is to comprise a MOS-type structure. When the inclination is 1 ° or more, the unevenness between the gate insulating film and the silicon carbide substrate is large, and the reliability of the gate insulating film is deteriorated. Therefore, the tilt angle is limited to more than 0 ° and less than 1 °.

  The fourth feature relates to a transistor having a modified gate insulating film. In addition to the third feature, the semiconductor device is located near the gate electrode and sandwiches the gate electrode. This is a lateral MIS field effect transistor in which a source region and a drain region are formed.

  The fifth feature relates to a transistor with improved on-resistance. In addition to the third feature, the semiconductor device has a gate insulating film and a gate electrode on the surface of the silicon carbide semiconductor region. A current having a source region in the vicinity of the gate electrode, a drain on the back surface of the silicon carbide semiconductor substrate, and flowing in the C-axis direction perpendicular to the surface of the epitaxial layer due to a change in voltage applied to the gate electrode It is a vertical MIS field-effect transistor that can control the current.

  In addition, when the silicon carbide semiconductor substrate is used as an electrode or a part of a semiconductor device, a semiconductor device other than the semiconductor device can be realized. Therefore, the sixth feature is any one of the first to fifth features. In addition, the silicon carbide semiconductor substrate is P-type or N-type.

  Further, since the electrical characteristics can be improved by optimizing the impurity activation heat treatment, the seventh feature is the above-described P-type semiconductor region or N-type in addition to any of the first to sixth features. The type semiconductor region is previously implanted for 10 seconds to 10 minutes in an inert gas atmosphere at a temperature of 1500 ° C. to 2000 ° C. after ion implantation of impurities for forming the P type or N type semiconductor region in the epitaxial layer. The impurity activation heat treatment has been performed for a predetermined time.

  In order to reduce an inappropriate impurity diffusion profile in the temperature rising process during the impurity activation heat treatment, the eighth feature includes the P-type in addition to any of the first to seventh features. The semiconductor region or the N-type semiconductor region is formed by ion-implanting impurities for forming a P-type or N-type semiconductor region into the epitaxial layer, and then in a inert gas atmosphere from a temperature of 1200 ° C. or lower to 1500 ° C. or higher and 2000 ° C. The temperature is raised to one of the following temperatures within 1 minute and subjected to impurity activation heat treatment at a temperature of 1500 ° C. to 2000 ° C. for a predetermined time of 10 seconds to 10 minutes. That is.

  In addition to the first to eleventh features described above, the tenth feature is that the epitaxial layer reacts with silane gas and propane gas under a pressure of 250 mbar (25 kPascal) or less. It is formed.

  In addition to the first to twelfth features described above, the eleventh feature is that the epitaxial layer is formed by a gas phase reaction between silane and propane gas. In the atmosphere, the composition ratio of the atomic density of carbon (C) to the atomic density of silicon (Si) is 1 or less.

  In the semiconductor device of the present invention, at least the outermost layer has a semiconductor region made of silicon carbide having a (000-1) plane, and at least one of a P-type semiconductor region and an N-type semiconductor region is ion-implanted into the silicon carbide semiconductor region. Since it is selectively formed, unevenness on the surface of the silicon carbide semiconductor region can be reduced, thereby improving electrical characteristics such as on-resistance and withstand voltage of the semiconductor device. In addition, since the impurity activation heat treatment is performed after the P-type semiconductor region and the N-type semiconductor region are formed by ion implantation, the outermost layer of the silicon carbide semiconductor region can be made even more uneven, and accordingly The electrical characteristics of the semiconductor device can be further improved.

It is a figure which shows the cross-sectional schematic diagram of the Schottky barrier diode as an example of the semiconductor device of this invention. It is a figure which shows the cross-sectional schematic diagram of the horizontal MIS field effect transistor as an example of the semiconductor device of this invention. It is a cross-sectional schematic diagram of a lateral MIS field effect transistor as an example of the semiconductor device of the present invention. It is a cross-sectional schematic diagram of a vertical MIS field effect transistor as an example of the semiconductor device of the present invention. Optical micrograph of the surface of the epitaxial layer when the pressure during the formation of the epitaxial layer by gas phase chemical reaction of silane and propane is changed (magnification: 200 times) Optical micrograph of the surface of the epitaxial layer when the ratio of C and Si is changed when the epitaxial layer is formed by a gas phase chemical reaction of silane and propane (magnification: 200 times) It is a circuit diagram which shows the example which used the semiconductor device of this invention for the inverter. It is a graph which shows the measured value by SIMS of the hydrogen density near a gate oxide film.

  In the following, first, as an example of a semiconductor device formed using a (000-1) plane silicon carbide substrate, a manufacturing method of a Shottky barrier diode, a lateral MIS field effect transistor, and a vertical MIS field effect transistor will be described. To do. Next, the surface roughness of the substrate after heat-treating the (0001) plane normally used in a semiconductor device using a silicon carbide semiconductor substrate and the (000-1) plane proposed in the present invention is described. The result measured with an atomic force microscope is shown. Furthermore, the effect that the pressure and the C / Si ratio give to the surface roughness when forming an epitaxial layer on a surface that is off by more than 0 ° and less than 1 ° from the (000-1) plane will be described.

Example 1
FIG. 1 is a schematic sectional view of a Schottky barrier diode as an example of the semiconductor device of the present invention. This Schottky barrier diode was manufactured by the following procedure.

(1) First, nitrogen is used as an impurity by chemical vapor deposition on the (000-1) plane of an N-type 4H—SiC bulk substrate 1 (resistivity: 0.002 Ωcm, thickness: 300 μm), and the concentration is 1 × 10 ^16. A cm ⁻³ N type epitaxial layer 2 was grown by 10 μm. The bulk substrate 1 and the epitaxial layer 2 form a silicon carbide semiconductor region, and the outermost layer of the epitaxial layer 2 is also a (000-1) plane.

(2) In order to form a guard ring in the peripheral portion of the Schottky electrode 6, 1 × 10 ¹⁷ cm ⁻³ ions of aluminum or boron P-type impurities are implanted into the region of the epitaxial layer 2 where the guard ring is to be formed. Then, a guard ring P-type impurity region (P-type semiconductor region) 3 was formed. At this time, a silicon dioxide film formed by a low pressure chemical vapor deposition method was used as a mask for ion implantation. A portion of the silicon dioxide film to be ion-implanted is opened with hydrofluoric acid and then ion-implanted at a temperature ranging from room temperature to 1000 ° C. In this embodiment, the ion-implantation is performed at room temperature.

(3) Next, in an argon atmosphere, the temperature is raised from 1200 ° C. or lower to 1500 ° C. to 2000 ° C., preferably 1700 ° C. within 1 minute, and an activation heat treatment is performed for 10 seconds to 10 minutes. In this example, heat treatment was performed at 1500 ° C. for 5 minutes.

(4) Subsequently, a Ni layer or a Ti layer (back electrode 4) is formed on the (0001) surface on the back surface side of the bulk substrate 1 by sputtering, and then heat-treated at about 1000 ° C. in an inert atmosphere. The electrode 4 is formed. An evaporation method may be used instead of the sputtering method.

(5) Next, a passivation oxide film 5 is formed on the ion-implanted epitaxial layer 2 side, a portion of the oxide film 5 where the Schottky electrode is to be formed is opened, and a Ni film or a Ti film is formed by sputtering. Form. This Ni film or Ti film is a Schottky electrode (metal electrode) 6 and forms a Schottky junction in a contact region with the ion-implanted epitaxial layer 2. Here, vapor deposition may be used instead of sputtering.

(6) Then, a metal wiring 7 made of an aluminum alloy is formed by sputtering to complete the semiconductor device. Here, vapor deposition may be used instead of sputtering. This semiconductor device has a gate (Schottky electrode) on the (000-1) plane of the silicon carbide semiconductor region, a drain (back electrode) on the (0001) plane, and an alternating voltage is applied between the drain and the gate. By doing so, it functions as a rectifying element that controls the direction of the current flowing in the C-axis direction perpendicular to the (000-1) plane.

  Thus, when the Schottky barrier diode is manufactured, the P-type semiconductor region 3 is formed by ion implantation in the silicon carbide semiconductor regions 1 and 2 having the (000-1) surface as the outermost layer. The fine irregularities on the surfaces of the silicon semiconductor substrates 1 and 2 can be reduced, thereby improving the electrical characteristics such as on-resistance and withstand voltage of the Schottky barrier diode.

  In addition, since the impurity activation heat treatment is performed after the P-type semiconductor region 3 is formed by ion implantation, the outermost surface layer of the silicon carbide semiconductor regions 1 and 2 can be made even more uneven, and accordingly The electrical characteristics of the Schottky barrier diode could be further improved.

  In the above description, the present invention is applied to the Schottky barrier diode that controls the direction of the current flowing in the C-axis direction perpendicular to the (000-1) plane. After forming the P-type semiconductor region 3 by ion implantation, an N-type semiconductor region is formed by ion implantation. By using the same process as described above, the C-axis direction perpendicular to the (000-1) plane is similarly used. You may make it apply to the PN type diode which controls the direction of the electric current which flows into.

(Example 2)
FIG. 2 is a schematic cross-sectional view of a lateral (Lateral resurf MOS structure) semiconductor device as an example of the lateral MIS field effect type of the present invention.
(1) First, on a (000-1) plane of a P-type 4H—SiC bulk substrate 11 (resistivity: 2 Ωcm, thickness: 300 μm), a P-type epitaxial of 10 to 15 μm using aluminum as an impurity by a chemical vapor deposition method. Layer 12 was formed. The P-type impurity concentration is 5 × 10 ¹⁵ cm ⁻³ . Here, the SiC bulk substrate 11 may be N-type. Bulk substrate 11 and epitaxial layer 12 form a silicon carbide semiconductor region, and the outermost layer of epitaxial layer 12 is also a (000-1) plane.

(2) Next, an ion implantation mask for forming the source region and the drain region is formed by a thermal oxide film or a SiO2 film by CVD (Chemical Vapor Deposition). In this embodiment, an LTO (Low Temperature Oxide) film is used as an ion implantation mask.
The LTO film was formed by reacting silane and oxygen at 400 to 800 ° C. to deposit silicon dioxide.

(3) Subsequently, after forming the source region and the drain region by photolithography, the LTO film is etched with HF (hydrofluoric acid) to open the source region and the drain region to be ion-implanted. Then, nitrogen, phosphorus, or arsenic is ion-implanted to form an N-type impurity region, which is a source 131 and a drain 132.

(4) Next, ions were implanted in the same manner as the source 131 and drain 132 to form the N − -type impurity region 14 for increasing the breakdown voltage. This layer may be divided into two or more regions, and the concentration may increase as it approaches the drain from the gate. Further, in order to make an ohmic contact to the P-type epitaxial layer 12, as in the case of the source 131, the drain 132, and the N − -type impurity region 14, an ion implantation mask is formed, and then aluminum or boron is ion-implanted. ^{A +} type impurity region 15 was formed. Here, the N ⁻ type “−” indicates that the concentration is lower than the N type impurity concentration of the N type region, and the P ⁺ type “+” indicates a concentration higher than the P type impurity concentration of the P type region. It is shown that.

(5) Thereafter, a heat treatment was performed at 1500 ° C. for 5 minutes in an argon atmosphere to perform an impurity activation heat treatment. This temperature can be selected in the range of 1500 ° C. to 2000 ° C., and the time can be selected from 10 seconds to 10 minutes. Thereafter, cooling was performed to a temperature of 1200 ° C. or less in 1 minute. This time can be selected between 1 and 5 minutes. At this time, it is better to raise the temperature from 1200 ° C. or lower to the heat treatment temperature within 1 minute.

(6) Subsequently, a passivation SiO ₂ film 16 is formed on the epitaxial layer 12 with a thermal oxide film or an LTO film. In this embodiment, an LTO film is used.

(7) Further, a portion where the gate insulating film is formed is opened and oxidized with O ₂ gas or O ₂ gas containing H ₂ O (water) at 800 ° C. to 1200 ° C., so that the gate insulating film 17 of about 50 nm is formed. Formed. The gate insulating film 17 is formed by thermally oxidizing silicon carbide as a whole or at least a layer in contact with the epitaxial layer 12. When the gate insulating film 17 is thermally oxidized in an O ₂ gas atmosphere containing water, the formed gate insulating film is formed. It contains hydrogen.

(8) A gate electrode (metal electrode) 18 was formed on the gate insulating film 17. The gate electrode 18 may be formed of aluminum or any of N-type and P-type polysilicon. The gate insulating film 17 and the gate electrode 18 are referred to as gates.

(9) Subsequently, the SiO ₂ film 16 on the source 131 and the drain 132 was etched to open contact holes.

(10) Next, after forming a metal containing nickel, titanium, aluminum or a laminated film thereof by vapor deposition or sputtering, a contact electrode (metal electrode) 19 is formed by reactive ion etching (RIE) or wet etching. Then, an ohmic contact was made by heat treatment at around 1000 ° C. in an inert atmosphere.

(11) Finally, after a metal containing aluminum was formed by vapor deposition or sputtering, the metal wiring 10 was formed by RIE or wet etching to complete.

(Example 3)
FIG. 3 is a schematic cross-sectional view of a lateral (Lateral resurf MOS structure) semiconductor device as an example of the lateral MIS field effect transistor of the present invention, having a structure different from that of FIG. 2 is basically the same as FIG. 2, except that a P-type impurity region 122 is provided in the epitaxial layer 12, and the source 131 and the P ⁺ -type impurity region 15 are formed in the epitaxial layer 122. Is different.

  The lateral lateral resurf MOSFET semiconductor device shown in FIGS. 2 and 3 has a gate (consisting of a gate insulating film and a gate electrode), a source and a drain on the (000-1) plane of the silicon carbide semiconductor region. It is a switching element that controls energization / cutoff of a current flowing between the source and the drain in the (000-1) plane by applying a voltage.

  In addition, as an example of the lateral semiconductor device, there is a MES field effect transistor. This is because a lateral Lateral is provided in that it has a gate, source and drain on the (000-1) plane, and controls the energization / cutoff of the current flowing in the (000-1) plane by applying a voltage to the gate. Although it is the same as the resurf MOSFET semiconductor device, there is no gate insulating film under the gate electrode, and the gate electrode made of metal is formed directly on the silicon carbide semiconductor.

  Thus, when manufacturing the lateral semiconductor device, the source 131, the drain 132, the N− type impurity region 14, the P + type impurity region are added to the silicon carbide semiconductor regions 11 and 12 whose outermost layer has the (000-1) plane. Since the P-type semiconductor region such as 15 and the N-type semiconductor region are formed by ion implantation, the fine irregularities on the surfaces of the silicon carbide semiconductor substrates 11 and 12 can be made smaller than the (0001) plane, and thereby the lateral semiconductor The electrical characteristics such as the on-resistance and withstand voltage of the device could be improved.

Further, after forming a P-type semiconductor region such as the source 131, the drain 132, the N ⁻ -type impurity region 14 and the P ⁺ -type impurity region 15 or an N-type semiconductor region by ion implantation, it is 1500 ° C. to 2000 ° C. in an inert atmosphere. Since the impurity activation heat treatment was performed for 10 seconds to 10 minutes at that temperature, the temperature was increased from 1500 ° C. or less to 1500 ° C. to 2000 ° C. within 1 minute in an inert atmosphere. Since the temperature is raised and the impurity activation heat treatment is performed at that temperature for 10 seconds to 10 minutes, the outermost surface layers of the silicon carbide semiconductor regions 11 and 12 can be made even more uneven, and accordingly the lateral semiconductor device It was possible to further improve the electrical characteristics.

FIG. 4 is a schematic cross-sectional view of a vertical MIS field effect transistor as an example of the semiconductor device of the present invention.
(1) In the semiconductor device of the present invention, the bulk substrate 21 is formed of a high-concentration N-type 4H—SiC substrate, and the epitaxial layer 22 made of low-concentration N-type silicon carbide is formed on the (000-1) plane. Formed. Bulk substrate 21 and epitaxial layer 22 form a silicon carbide semiconductor region, and the outermost layer of epitaxial layer 22 is also a (000-1) plane.

(2) Next, a first N-type impurity region 23 made of silicon carbide having a first concentration was epitaxially grown on the epitaxial layer 22 by a chemical vapor deposition method. Subsequently, the substrate made of silicon carbide at this stage was subjected to normal RCA cleaning, and then an alignment mark for lithography was formed by RIE (Reactive ion etching).

(3) An LTO (low temperature oxide) film was used as a mask for ion implantation. This LTO film was formed by reacting silane and oxygen at 400 ° C. to 800 ° C. to deposit silicon dioxide on the silicon carbide substrate (first N-type impurity region 23). This temperature can be selected from 400 ° C to 800 ° C.
(4) Next, after forming a region to be ion-implanted by lithography, the LTO film was etched with HF (hydrofluoric acid) to open a region to be ion-implanted.
(5) Next, aluminum or boron is ion-implanted into the first N-type impurity region 23, so that a first P-type silicon carbide region (P-type (P ⁻ ) well is adjacent to both sides of the first N-type impurity region 3. ) 24, 24 were formed.

(6) Further, in order to increase the breakdown voltage, the second P-type silicon carbide region (P ⁺ region) 24a having a higher concentration than the first P-type silicon carbide region 24 is ion-implanted to the lower portion of the first P-type silicon carbide region 24. Formed in the region. The second P-type silicon carbide region 24a was found to be able to reliably improve the pressure resistance by being formed by injecting 10 ¹⁸ cm ⁻³ to 10 ¹⁹ cm ⁻³ of aluminum or boron. .

(7) Further, if necessary, the buried channel region 25 as an N-type impurity region having a sufficient impurity concentration selectively from the surface to the inside of the first P-type silicon carbide region 24 below the region where the gate oxide film is to be formed. Formed. The buried channel region 25 was formed by ion implantation at 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ^{−3 at} a depth (L _bc ) = 0.3 μm. Then, phosphorus was implanted in multiple stages so that the total dose was 7 × 10 ¹⁵ cm ^−2, and the implantation energy was controlled in the range of 40 keV to 250 keV to form a desired depth.

(8) Next, a second N-type impurity region (N ⁺ source) having a second concentration selectively from the surface of the first P-type silicon carbide regions 24, 24 to the inside at a position away from the first N-type impurity region 23. ) 26 and 26 were formed.
(9) If necessary, in the first P-type silicon carbide region 24 between the second N-type impurity region 26 and the buried channel region 25, a third concentration of the third N-type is selectively formed from the surface to the inside. Impurity region 27 was formed by ion implantation.

(10) Thereafter, impurity activation heat treatment was performed in the range of 1500 ° C. to 2000 ° C. for 10 seconds to 10 minutes in an argon atmosphere, and then cooled to a temperature of 1200 ° C. or lower in 1 minute to 5 minutes. In this example, heat treatment was performed at 1500 ° C. for 5 minutes. At this time, it is better to raise the temperature within 1200 minutes from 1200 ° C. or lower to the heat treatment temperature.

(11) Next, oxidation was performed at 1200 ° C. in an O ₂ atmosphere or an O ₂ atmosphere containing H ₂ O to form gate oxide films 28 and 28 of about 50 nm. The gate insulating film 28 is formed by thermally oxidizing silicon carbide in its entirety or at least a layer in contact with the epitaxial layer 22. When the gate insulating film 28 is thermally oxidized in an O ₂ gas atmosphere containing water, the gate insulating film formed is formed. It contains hydrogen. FIG. 8 shows the actual measured values by this SIMS (secondary ion mass spectrometer). It can be seen that hydrogen is distributed around the interface between the silicon carbide substrate and the gate oxide film. If the maximum value at this interface is 1.0 × 10 ¹⁹ or more per cubic centimeter, the mobility is improved.

(12) Subsequently, after annealing in argon for 30 minutes, it was cooled to room temperature in argon.
(13) Thereafter, gate electrodes 29 and 29 are formed. The gate electrodes 29 and 29 were made of P ⁺ polysilicon. The method for forming the gate electrodes 29 and 29 with P ⁺ polysilicon is as follows: 1) After forming polycrystalline polysilicon by the CVD method, ion implantation of boron or boron fluoride is performed to form P-type polycrystalline silicon. 2) After forming polycrystalline polysilicon by the CVD method, a boron-containing SiO ₂ film is formed by the CVD method or spin coating, heat treated at 800 ° C. to 1100 ° C., and diffused to form boron. Implanting to form P-type polycrystalline silicon 3) Flowing silane and diborane together and performing heat treatment at 600 ° C. to inject boron into the polycrystalline silicon to form P-type polycrystalline silicon . In this embodiment, the method 2) was used.

(14) Then, the formation of the gate electrodes 29, 29 is completed by etching. In the above description, the gate electrode 29 is formed of P ⁺ polysilicon, but may be formed of aluminum, an aluminum alloy, or molybdenum metal. When the gate electrode 29 is formed of aluminum, aluminum alloy, or molybdenum metal, the interface with the gate oxide film 28 is better than the interface with the gate oxide film 28 when polysilicon is used for the gate electrode 29, The effect of increasing channel mobility was also confirmed.

  Further, a silicide film 30 made of any one of WSi2, MoSi2, or TiSi2 may be formed on the gate electrodes 29, 29.

(15) Subsequently, after the interlayer insulating film 31 is deposited by the CVD method, the interlayers on the second N-type impurity regions (N ⁺ source) 26 and 26 and the first P-type silicon carbide regions (P ⁻ wells) 24 and 24 The insulating film 31 was etched to open a contact hole.
(16) Next, after forming a laminated film made of a metal containing nickel, titanium, aluminum, or an alloy thereof by vapor deposition or sputtering,
(17) A metal wiring 32 made of polycrystalline silicon is formed by RIE or wet etching, and the first P-type silicon carbide region 24 and the second N-type impurity region 26 are short-circuited. In this embodiment, after the aluminum is deposited, the metal wiring 32 is formed by wet etching.

(18) Next, the drain electrode 33 was formed on the back side of the bulk substrate 21 by applying a necessary thickness of metal by vapor deposition or sputtering. In this embodiment, nickel is applied by sputtering.
(19) Further, if necessary, heat treatment was performed in argon at 1000 ° C. for 5 minutes, thus completing a vertical MIS field effect transistor.
In addition to this, there is a junction field effect transistor as a vertical semiconductor device. This has a structure in which there is no oxide film under the gate electrode and the metal gate electrode is in direct contact with the silicon carbide. By applying a voltage to this gate electrode, current supply / cutoff in a direction perpendicular to the (000-1) plane is controlled.

  As described above, when the vertical MIS field effect transistor and the junction field effect transistor are manufactured, the first N is formed on the silicon carbide semiconductor substrates (silicon carbide semiconductor regions) 21 and 22 having the (000-1) surface as the outermost layer. Since the P-type semiconductor region and the N-type semiconductor region such as the silicon carbide region 23, the first P-type silicon carbide region 24, and the second P-type silicon carbide region 24a are formed by ion implantation, the surface roughness of the silicon carbide semiconductor substrates 21, 22 Can be made smaller than the (0001) plane, whereby the on-resistance of the vertical MIS field effect transistor and the junction field effect transistor can be reduced to about 1/10.

  Further, after forming a P-type semiconductor region such as the first N-type silicon carbide region 23, the first P-type silicon carbide region 24, and the second P-type silicon carbide region 24a or an N-type semiconductor region by ion implantation, an impurity activation heat treatment is performed. As a result, the outermost layer of the silicon carbide semiconductor substrates 21 and 22 can be made even more uneven, and the electrical characteristics of the vertical MIS field effect transistor and the junction field effect transistor can be further improved accordingly. did it.

  The semiconductor device according to the present invention described above, for example, a Schottky barrier diode, a PN diode, a junction field effect transistor, a lateral MIS field effect transistor, and a vertical MIS field effect transistor, Power converters, drive inverters, general-purpose inverters, and MES field effect transistors contribute to improving the performance of these devices by being incorporated as components in high-frequency and high-frequency communication devices in the GHz band. be able to. FIG. 7 shows a circuit diagram in which the lateral MIS field effect transistor of the present invention is applied to the transistor at the position of A in FIG. 7 of the driving inverter.

  Next, the effect of the heat treatment time on the surface roughness (RMS) of the (0001) plane and the (000-1) plane of the silicon carbide semiconductor substrate will be described.

  In order to examine the effect of the activation heat treatment on the surface roughness, the (0001) plane silicon carbide substrate and the (000-1) plane silicon carbide substrate were heated from room temperature to 1600 ° C. in 1 minute, Activation heat treatment was performed for 1 minute and 10 minutes, and the surface was observed with an atomic force microscope to measure surface roughness (RMS). The results are shown in Table 1. As can be seen from Table 1, the surface roughness (RMS) of the (000-1) plane is smaller than that of the (0001) plane and is about half regardless of whether the heat treatment time is 1 minute or 10 minutes.

  Therefore, by forming a semiconductor device having an ion implantation region on the (000-1) plane, a gate insulating film or a gate electrode is formed thereon, and a horizontal MIS field effect transistor, a vertical MIS field effect transistor, When a semiconductor device such as a MES field effect transistor or a junction field effect transistor is manufactured, when electrons flow during energization, scattering due to unevenness on the surface of the silicon carbide substrate is reduced, and electrons flow easily and the on-resistance decreases. In addition, the high frequency characteristics of the MES field effect transistor are improved. In addition, when a junction is formed by a lateral MIS field effect transistor, a vertical MIS field effect transistor, a MES type field effect transistor, a junction type field effect transistor, a Schottky barrier diode, or a PN type diode, a crystal defect Therefore, when a reverse (negative) voltage is applied to the gate electrode, the leakage current can be reduced and at the same time the withstand voltage can be improved.

  The pressure when forming an epitaxial layer by a chemical vapor reaction of silane and propane gas on a plane inclined by 0 ° or more and less than 1 degree from the (000-1) plane is performed at 250 mbar (25 kpascal) and 500 mbar (50 kpascal). FIG. 5 shows an optical microscope photograph (200 times) of the surface of the epitaxial layer. At 500 mbar, the surface is uneven, but at 250 mbar, the surface is smooth. Therefore, by forming an epitaxial layer at a pressure of 250 mbar or less, a smooth epitaxial layer can be formed even on a plane inclined by 0 ° or more and less than 1 degree from the (000-1) plane. A semiconductor device in which an electrode or a gate insulating film is formed exhibits excellent electrical characteristics.

  Further, the ratio of the number of C and Si atoms when the epitaxial layer is formed by a chemical vapor reaction of silane and propane gas on a plane inclined by 0 ° or more and less than 1 degree from the (000-1) plane is 0.6, FIG. 6 shows an optical micrograph (200 times) of the surface of the epitaxial layer when the measurement is performed at 1, 1.5 and 3. (C) At C / Si = 1.5, there are some triangular defects. (D) When C / Si = 3, a great many defects exist. On the other hand, when C / Si = 0.6 (a) and 1.0 (b), no defect is observed and the surface is smooth. Therefore, by forming an epitaxial layer with C / Si = 1.0 or less, a smooth epitaxial layer can be formed even on a plane inclined by 0 ° or more and less than 1 degree from the (000-1) plane. It is possible to improve the electrical characteristics of a semiconductor device in which an electrode and a gate insulating film are formed on the epitaxial layer.

As described above, in the semiconductor device of the present invention, at least the outermost layer has a semiconductor region made of silicon carbide having a (000-1) plane, and the P-type semiconductor region and the N-type semiconductor region are formed in the silicon carbide semiconductor region. Since at least one of them is selectively formed by ion implantation, the surface roughness of the silicon carbide semiconductor region can be reduced, thereby improving the electrical characteristics such as on-resistance and withstand voltage of the semiconductor device. .
In addition, since the impurity activation heat treatment is performed after the P-type semiconductor region and the N-type semiconductor region are formed by ion implantation, the outermost layer of the silicon carbide semiconductor region can be made even more uneven, and accordingly The electrical characteristics of the semiconductor device can be further improved.
In addition, a power converter, a drive inverter, a general-purpose inverter, or a high-power high-frequency communication device can be configured using the semiconductor device of the present invention.

1 Bulk substrate (silicon carbide semiconductor region)
2 Epitaxial layer (silicon carbide semiconductor region)
3 P-type semiconductor region 4 Back electrode 5 Oxide film 6 Schottky electrode 7 Metal wiring 10 Metal wiring 11 Bulk substrate (silicon carbide semiconductor region)
12 Epitaxial layer (silicon carbide semiconductor region)
122 P-type impurity region 131 Source (N + type impurity region)
132 Drain (N + type impurity region)
14 N− type impurity region 15 P + type impurity region 16 SiO ₂ film 17 Gate insulating film 18 Gate electrode 21 Bulk substrate (silicon carbide semiconductor region)
22 Epitaxial layer (silicon carbide semiconductor region)
23 1st N-type silicon carbide region 24 1st P-type silicon carbide region 24a 2nd P-type silicon carbide region 25 buried channel region (N-type impurity region)
26 Second N-type impurity region 27 Third N-type impurity region 28 Gate oxide film 29 Gate electrode 30 Silicide film 31 Interlayer insulating film 32 Metal wiring

Claims (10)

A semiconductor device formed on a silicon carbide semiconductor substrate,
The substrate has an epitaxial layer grown on a surface tilted by more than 0 ° and less than 1 ° from the (000-1) plane of a silicon carbide semiconductor substrate having a 4H crystal structure ,
In the epitaxial layer, at least one of a P-type semiconductor region and an N-type semiconductor region is selectively formed by ion implantation,
A metal electrode is formed in contact with the surface layer of the P-type semiconductor region or the N-type semiconductor region,
Shows the rectification between the metal electrode and the epitaxial layer, a Schottky barrier diode door Rui P N-type diode,
A semiconductor device characterized by the above. A semiconductor device formed on a silicon carbide semiconductor substrate,
The substrate has an epitaxial layer grown on a surface tilted by more than 0 ° and less than 1 ° from the (000-1) plane of a silicon carbide semiconductor substrate having a 4H crystal structure ,
In the epitaxial layer, at least one of a P-type semiconductor region and an N-type semiconductor region is selectively formed by ion implantation,
A metal electrode is formed in contact with the surface layer of the P-type semiconductor region or the N-type semiconductor region,
The metal electrode constitutes a gate electrode, and a source region and a drain region are formed in positions adjacent to the gate electrode and sandwiching the gate electrode.
MES type field effect transistor or junction type field effect transistor,
A semiconductor device characterized by the above. A semiconductor device formed on a silicon carbide semiconductor substrate,
The substrate has an epitaxial layer grown on a plane inclined more than 0 ° and less than 1 ° from a (000-1) plane of a silicon carbide semiconductor substrate having a 4H crystal structure ,
In the epitaxial layer, at least one of a P-type semiconductor region and an N-type semiconductor region is selectively formed by ion implantation,
A gate insulating film is formed on a surface layer of the P-type semiconductor region or the N-type semiconductor region, the gate insulating film is a silicon oxide film, and a layer of the silicon oxide film in contact with the silicon carbide substrate is the epitaxial layer described above. Is formed by thermal oxidation in an atmosphere containing water, and the hydrogen density in the gate insulating film is 1.0 × 10 ¹⁹ or more per cubic centimeter,
A semiconductor device comprising a MOS structure.   4. The semiconductor device according to claim 3, wherein the semiconductor device is a lateral MIS field effect transistor in which a source region and a drain region are formed in a position close to the gate electrode and sandwiching the gate electrode. Semiconductor device.   The semiconductor device has a gate insulating film and a gate electrode on the surface of the silicon carbide semiconductor region, has a source region in the vicinity of the gate electrode, has a drain on the back surface of the silicon carbide semiconductor substrate, 4. The vertical MIS field effect transistor according to claim 3, wherein the vertical MIS field effect transistor is capable of controlling a current flowing in a C-axis direction perpendicular to a surface of the epitaxial layer by changing a voltage applied to the gate electrode. 5. Semiconductor device.   The semiconductor device according to claim 1, wherein the silicon carbide semiconductor substrate is P-type or N-type.   The P-type semiconductor region or the N-type semiconductor region is formed in an inert gas atmosphere at a temperature of 1500 ° C. to 2000 ° C. after ion implantation of impurities for forming the P-type or N-type semiconductor region into the epitaxial layer. 7. The semiconductor device according to claim 1, wherein the impurity activation heat treatment is performed for a predetermined time of 10 seconds to 10 minutes.   The P-type semiconductor region or the N-type semiconductor region is formed from a temperature of 1200 ° C. or less in an inert gas atmosphere after ion implantation of impurities for forming the P-type or N-type semiconductor region in the epitaxial layer. The temperature is raised within 1 minute to any temperature between ℃ and 2000 ℃, and the impurity activation heat treatment is performed at a temperature between 1500 ℃ and 2000 ℃ for a predetermined time of 10 seconds to 10 minutes. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. It said epitaxial layer, in the following under pressure 250 mbar (25k Pascal), the semiconductor device according to claim 1, characterized in that formed by reacting silane gas and propane gas to claim 8. The above epitaxial layer is formed by a gas phase reaction between silane and propane gas, and the composition ratio of the atomic density of carbon (C) to the atomic density of silicon (Si) in the atmosphere in which the gas phase reaction occurs is 1 or less. the semiconductor device according to any one of claims 1 to 9, characterized in that it.