JP5108193B2 - Improved test structure inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of sample inspection and analysis, and more particularly to inspection and analysis of defects in semiconductor integrated circuits.
[0002]
[Prior art]
In the semiconductor integrated circuit (IC) industry, it is always required to increase the packing density of circuits. The demand to increase packing density has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Because the manufacture of ICs with such very small dimensions complicates the circuit, there is always a need for improved methods for inspecting integrated circuits at various stages of manufacture.
[0003]
Inspection of such products at various stages of manufacture is very important and can greatly improve yield and product reliability, but as IC complexity increases, such inspections Costs increase in both cost and time. However, if a defect is detected at an early stage in manufacturing, the cause of the defect can be determined and repaired before many defective ICs are manufactured.
[0004]
In order to solve the problems caused by defective ICs, IC manufacturers may process semiconductor defect test structures. Such a defect test structure is for defect analysis. The defect test structure is processed to be sensitive to defects that occur in the product of the IC, but is designed so that the presence of defects is more easily confirmed. Such defect test structures are often formed on the same semiconductor substrate as the IC product.
[0005]
One example of a defect test structure is found in a copper CMP test mask set designed at MIT. This test mask set is designed to quantify the degree to which the resulting copper line shape depends on parameters such as line pitch, line width, and previous aspect ratio. However, the MIT mask set does not use an electron beam, but a conventional electrical test in which current is passed through the device by bringing an electric probe into contact with a predetermined pad of a large area (approximately 100 × 100 μm 2). Designed to be tested using As is well known in the art, defect detection systems frequently use charged particle beams. In such a system, a charged particle beam such as an electron beam is irradiated onto the defect test structure. The interaction between the electron beam and the shape of the circuit emits a large number of signals of various intensities, such as secondary electrons, backscattered electrons, and X-rays. Typically, electron beam methods use secondary electron signals for the well-known “voltage contrast” technique for circuit defect detection.
[0006]
Voltage contrast technology is based on the fact that potential differences at various locations in the test structure under test cause differences in the intensity of secondary electron emission. Therefore, the state of the potential of the scanned region is displayed brightly in a low potential portion such as a wiring pattern (the intensity of secondary electron emission is large), and darkly displayed in a high potential portion (secondary electrons). Is obtained as a voltage contrast image. Alternatively, the system may be configured to display low potential portions darkly and display high potential portions brightly.
[0007]
The secondary electron detector is used to measure the intensity of secondary electron emission that occurs only in the path scanned by the scanning electron beam. The defective portion can be confirmed from the potential state of the portion being inspected. In one type of inspection, the location of the defect is revealed from the mismatch between the defective voltage contrast image and the image without the defect.
[0008]
Thus, in such a system, voltage contrast is observed simultaneously for both defective and non-defective circuits for each manufactured circuit. However, given the density of currently manufactured ICs, the time required to scan the voltage contrast data to perform the comparison is considerable. Inspection and analysis of such circuits can take several days. Therefore, there is a need for a more efficient voltage contrast inspection system.
[0009]
Summary of the Invention
The present invention comprises a system for detecting defects in a test structure. The system operates to perform an efficient and effective defect test. The system further comprises a new test structure for improved defect testing, as detailed below.
[0010]
In one embodiment, the present invention relates to a method for inspecting a sample. The method comprises the step of moving to a first field associated with a first group of test structures. The first group of test structures is partially in the first field. The method further comprises scanning the first field to determine whether a defect exists in the first group of test structures. If it is determined that the first group of test structures is defective, the method further includes repeating the movement of the region to determine the location of the specific defect in the first group of test structures. Scanning. In one embodiment, the defect is located outside the first field being inspected.
[0011]
In another embodiment, a test structure is disclosed. The test structure includes a plurality of conductive lines each having a first end and a second end. The first end of the conductive line is in the scannable area, and the second end of the conductive line extends away from the scannable area. At least one of the conductive lines is floating or connected to a predetermined potential.
[0012]
In another embodiment, a semiconductor die having a scan region is disclosed. The semiconductor die comprises a first plurality of test structures. Each test structure in the first plurality of test structures is completely disposed within the scan region. The semiconductor die further comprises a second plurality of test structures. Each test structure in the first plurality of test structures is only partially disposed in the scan region. The test structure is arranged such that defects outside the scanning area are detected as a result of scanning the scanning area. In a preferred embodiment, the second plurality of test structures includes a test structure disposed primarily outside the scan area. In another aspect, the second plurality of test structures are arranged outside the scan region by performing voltage contrast on a portion of the second plurality of test structures disposed in the scan region. Arranged to detect shorts associated with some of the two test structures. In a particular embodiment, the first plurality of test structures includes a plurality of types of test structures, the test structures including a first type of test structure and a second type of test structure. The first type test structure is different from the second type test structure, and the first and second type test structures are via chain test structure, chemical mechanical polishing (CMP) test structure, contact array test structure, array It may be a test structure for measuring the misalignment, or a CMP dummy metal filling test structure.
[0013]
In another embodiment, the semiconductor die has at least one electrically isolated conductive test structure disposed adjacent to the at least one electrically non-insulated conductive test structure. The first portion of the electrically isolated test structure is disposed within the scanning region and the second portion of the electrically isolated test structure is disposed outside the scanning region, thereby providing at least one. Detecting a short circuit between the second part of the electrically isolated test structure and the electrically non-insulated test structure through the voltage contrast of the first part of the two electrically isolated test structures. Can do. In a preferred embodiment, the width of the first portion of the electrically non-insulated test structure is less than or equal to the width of the second portion of the electrically non-insulated test structure.
[0014]
In another aspect, the invention relates to a method for performing an inspection. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in the second direction with at least one particle beam. The second direction forms an angle with respect to the first direction. The number of defects per area of the sample is detected as a result of the first scan, and the position of one or more detected defects is determined from the second scan. In certain embodiments, the sample comprises a test structure having a plurality of test elements. The first portion of the test element is exposed to the beam during the first scan to identify a defective test structure. A second portion of the test element is exposed to the beam during the second scan to isolate and characterize the defect.
[0015]
In another method embodiment, a first portion of the sample is scanned in a first direction with at least one particle beam, and a second portion of the sample is scanned in a second direction with at least one particle beam. Is done. The second direction forms an angle with respect to the first direction. The approximate position of each defect in the second portion is determined from a first direction scan, and the detailed position of each defect in the second portion is determined from a second direction scan. In another method aspect, a first portion of the sample is scanned in a first direction with at least one particle beam, and a second portion of the sample is scanned in a second direction with at least one particle beam. The The second direction forms an angle with respect to the first direction. An inventory of defects in the second portion is determined from the scan in the first direction, and the characteristics of the defects in the second portion are determined from the scan in the second direction. In yet another embodiment, a method for detecting and locating electrical defects in a semiconductor die present in a vacuum is disclosed. A defect in the semiconductor die is detected. Without sacrificing the vacuum state, a focused ion beam is used to remove the structure from the semiconductor die to expose the defects and then characterize the defects.
[0016]
In another embodiment, a method for detecting electrical defects on a test structure of a semiconductor die is disclosed. The semiconductor die includes a plurality of electrically isolated test structures and a plurality of electrically non-insulated test structures. A voltage is established for a plurality of electrically isolated test structures. These voltages are different from those of a plurality of electrically non-insulated test structures. A region of the semiconductor die is continuously inspected in a first direction, thereby obtaining voltage contrast data indicating whether a defective test structure is present. The voltage contrast data is analyzed to determine if one or more defect test structures are present.
[0017]
In another embodiment, a semiconductor die having an underlayer test structure formed in a lower metal layer of the semiconductor die is disclosed. The lower conductive test structure has a first end and a second end. The first end is connected to a predetermined voltage level. The semiconductor die further comprises an insulating layer formed over the lower metal layer. The die further comprises an upper layer test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is connected to the second end of the lower conductive test structure. The upper metal layer is formed above the insulating layer. In certain embodiments, the first end of the underlying test structure is grounded. In another embodiment, the semiconductor die further comprises a substrate and a first via connected between the first end of the underlying test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line and the upper test structure is a voltage contrast element.
[0018]
In another aspect, the invention relates to a method for testing a semiconductor die. The semiconductor die includes a substrate, a first metal layer, and a second metal layer formed above the first metal layer. A first metal test structure is formed in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection. A second metal test structure is formed in the second metal layer of the semiconductor die such that the second metal test structure has a second electrical connection to the first metal test structure. The second electrical connection is formed at a distance from the first electrical connection. By evaluating the extent to which current can flow from the second metal test structure to the first connection, the first metal test structure is intact between the first electrical connection and the second electrical connection. It is determined whether or not there is.
[0019]
In another aspect, a method for processing a test structure is disclosed. A voltage contrast test structure element is formed and at least one non-conductive layer is formed on at least a portion of the test structure element. At least one conductive element is formed in the non-conductive layer. The conductive element is electrically connected to the voltage contrast test structure. In another embodiment, a method for inspecting product quality is disclosed. Data on the product quality generated by performing a voltage contrast test on the voltage contrast test structure above the product during the manufacture of the product is obtained. At least a portion of the voltage contrast structure present on the product is re-inspected prior to product acceptance, thereby generating additional data indicative of product quality.
[0020]
In another aspect, a semiconductor die is disclosed. The die includes a lower test structure element, a non-conductive layer covering at least a portion of the lower test structure element, an upper test structure element above at least a portion of the lower test structure element, and a conductive element in the non-conductive layer. With. The conductive element is electrically connected to the lower and upper test structure elements. The semiconductor die preferably further comprises a plurality of lower layer test structure elements and a plurality of upper layer test structure elements. A plurality of lower layer test structural elements are formed in the same first conductive layer, and a plurality of upper layer test structural elements are formed in the same second conductive layer. The upper and lower test structure elements are connected to each other by a plurality of conductive elements in the non-conductive layer. A method for processing and inspecting such a structure is also disclosed.
[0021]
In another embodiment, a semiconductor die having a plurality of dummy fills arranged and sized to minimize defects during a plurality of chemical mechanical polishings is disclosed. At least one dummy fill is connected to the underlying test structure. In a preferred embodiment, the semiconductor die further comprises a plurality of conductive layers and a substrate. The underlying test structure comprises a portion of a first layer formed from a first layer of a plurality of conductive layers and a via connecting a portion of the first layer to at least one dummy fill. . In another aspect, the underlying test structure further includes a via connecting a portion of the first layer to the substrate, and the underlying test structure includes a plurality of layers and vias. A multi-layer test structure is formed. In another embodiment, the present invention relates to a method for processing a semiconductor die. A plurality of conductive layers are formed, and a test structure is formed from at least one of the plurality of conductive layers. In order to minimize defects due to CMP, a dummy filling is added in the uppermost conductive layer of the plurality of conductive layers. At least one dummy fill is formed above the test structure.
[0022]
In another aspect, the present invention relates to a method for detecting electrical defects on a test structure of a semiconductor die. The test structure includes a plurality of electrically isolated test structures and a plurality of electrically non-insulated test structures. Each test structure has a portion partially disposed within the scan region. By scanning a portion of the test structure located within the scan region, a voltage contrast image of that portion of the test structure is obtained. In a multi-pixel processor, the acquired voltage contrast image is analyzed to determine if there are defects in the test structure. In a preferred embodiment, the multi-pixel processor operates with a pixel resolution size in the range of about 25 nm to 2000 nm. In another aspect, the processor operates with a pixel size nominally equal to twice the line width of the test structure to maximize throughput with optimal signal-to-noise sensitivity. A readable medium including a program instruction computer for performing the above-described method is also disclosed.
[0023]
In another embodiment, a method for inspecting a sample is disclosed. At least a portion of the sample is illuminated. A signal from the illuminated part is detected and the detected signal is processed to find defects present above the sample. The processing of the detected signal is optimized based at least in part on the results obtained from the voltage contrast test. In one embodiment, the illumination is optical illumination. In another embodiment, the process comprises automatic defect classification, and the automatic defect classification settings are optimized using the results obtained from the voltage contrast test. In another embodiment, the result relates to the possibility that the shape present above the sample is an electrical defect. In another aspect, a method for optimizing an optical measurement tool is disclosed. In step a, the test structure is examined by voltage contrast to determine the approximate location of one or more fatal defects and to generate a first map of such fatal defects. In step b, the test structure is optically inspected to generate a plurality of optical images and a second map of optical defects. In step c, the first map and the second map associate optical defects with at least some critical defects and whether the optical means is optimized for detecting critical defects. Superimposed to determine. Steps (b) and (c) are preferably repeated under various optical means until the optical means is optimized. In yet another aspect, the optical inspection is performed on a first layer of the test structure that is different from the second layer of the test structure on which the voltage contrast inspection is performed. In another embodiment, it is determined which manufacturing process is optimal for detecting critical defects. In another embodiment, steps ab are further used to periodically extract or calibrate the optimal means.
[0024]
In another aspect, a method for inspecting a sample is disclosed. The sample is illuminated by the incident beam, causing a voltage contrast in the structure that exists above the sample. Voltage contrast is detected in the structure. Information from the detected voltage contrast is stored, and position data relating to the position of the shape corresponding to at least a portion of the stored voltage contrast information is also stored. In certain embodiments, the shape represents an electrical defect present above the sample. In another embodiment, the stored location data is in the form of a two-dimensional map. In another aspect, the sample is re-examined and the stored location data is used in analyzing data from the re-examination.
[0025]
In another embodiment, a semiconductor die having an upper layer and a lower layer is disclosed. The die includes an underlayer test structure formed in a metal layer below the semiconductor die. The lower layer conductivity test structure has a first end and a second end, the first end being connected to a predetermined voltage level. The die further includes an insulating layer formed above the lower metal layer and an upper test structure formed on the upper metal layer of the semiconductor die. The upper conductive test structure is connected to the second end of the lower conductive test structure, and the upper metal layer is formed above the insulating layer. The die further comprises at least one probe pad connected to the upper test structure. The first end of the underlying test structure is preferably connected to a nominal ground potential. In another embodiment, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scan region is disclosed. The semiconductor die comprises a first plurality of test structures. Each test structure in the first plurality of test structures is completely disposed within the scan region. The die further comprises a second plurality of test structures. Each test structure in the first plurality of test structures is only partially disposed in the scan region. The first plurality of test structures or the second plurality of test structures have a probe pad connected to at least one test structure. In yet another semiconductor die embodiment, the semiconductor die includes at least one electrically isolated conductive test structure and at least one electrically isolated conductive test structure disposed adjacent to the at least one electrically isolated conductive test structure. And an electrically non-insulating conductive test structure. The first portion of the electrically isolated test structure is disposed within the scanning region, and the second portion of the electrically isolated test structure is disposed outside the scanning region, thereby providing electrical Through the voltage contrast of the first part of the electrically isolated test structure, a short circuit between the second part of the electrically isolated test structure and the electrically non-insulated test structure can be detected. The die further comprises a first probe pad connected to at least one electrically isolated test structure. In another die embodiment, the semiconductor die comprises at least one electrically non-insulating conductive test structure, and the first portion of the at least one electrically non-insulating test structure is disposed within the scan region. Has been. The die further comprises a probe pad connected to the first portion of the electrically non-insulating test structure. The second part of the electrically non-insulated test structure is arranged outside the scanning area. Thereby, open-type defects in the electrically non-insulated test structure can be detected through the voltage contrast of the first part of the electrically isolated test structure. The width of the first portion of the electrically non-insulating test structure is approximately equal to or less than the width of the second portion.
[0026]
The foregoing and other features and advantages of the invention will be more fully shown from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
As described below, preferred embodiments of the present invention provide automatic, rapid, non-contact wafer inspection to detect, isolate, and characterize defects affecting integrated circuits.
[0028]
Some embodiments of the present invention include a semiconductor structure and a metallization or other interconnect thereon, and multi-layer integration using various levels of conductors separated from other conductors and substrates by dielectric layers. The circuit structure is described as an example. However, structures formed using other semiconductor processing methods are also included within the scope of the present invention.
[0029]
One application of the present invention involves the operation of a scanning electron microscope (SEM) with a continuously moving stage. However, many of the test structures and methods described herein are also useful for other test equipment, including SEMs operated in step-and-repeat mode. Instead of moving the stage relative to the beam, the beam may be moved by deflecting the field of view with an electromagnetic lens. Alternatively, the beam train may be moved with respect to the stage.
[0030]
A. Use of a scanning electron microscope with a stage that moves continuously to scan the primary region.
The present invention, in one embodiment, uses a SEM with a stage that moves continuously. Using such an SEM has significant advantages with respect to detecting defects in semiconductor devices, as will be described in detail below.
[0031]
The SEM system may be used to perform automated inspection of wafers and other substrates. Such SEM systems are well known to those skilled in the art. For example, on November 26, 1996, Meisburger et al. U.S. Pat. No. 5,578,821, “ELECTRON BEAM INSPECTION SYSTEM AND METHOD”, issued to U.S. Pat. No. 5,849,400, includes devices for charged particle scanning and automated inspection systems, including wafers used in the manufacture of integrated circuits. It is described. The entirety of this patent is incorporated herein by reference. In the Meisburger apparatus, a charged particle beam is directed against the surface of the substrate to scan the substrate and to detect at least one of secondary charged particles, backscattered charged particles, and transmitted charged particles from the substrate. A detector is selected.
[0032]
The substrate is attached to an xy stage. When the substrate is being scanned by the charged particle beam, at least one degree of freedom of movement is provided. The substrate may be exposed to an electric field on or near the surface of the substrate to accelerate the secondary charged particles. The system facilitates inspection with a low beam energy against a charge sensitive insulating substrate and has the ability to accurately measure the position of the substrate relative to the charged particle beam.
[0033]
In addition, an optical positioning system is provided for aligning the substrate below the charged particle beam. In order to function most efficiently, a vacuum system is further provided for evacuating and repressurizing the chamber containing the substrate. The vacuum system can be used to keep the first substrate in a vacuum as the second substrate is unloaded and evacuated or repressurized. The inspection configuration further includes a comparison system for comparing the pattern on the substrate with the second pattern.
[0034]
The '821 patent further describes an automated system for automated inspection of substantially non-conductive substrates. The system includes a field emission electron source for supplying an electron beam, a charged particle beam array for scanning an electron beam from the field emission electron source to the surface of the substrate, and three types of radiation emitted from the upper and lower surfaces of the substrate. And one or more charged particle detectors for detecting one or more of the charged particles (ie, secondary charged particles, backscattered charged particles, transmitted charged particles). The system further includes a continuously moving xy stage arranged to receive the substrate and provide the substrate with at least one degree of freedom motion as the substrate is being scanned by the charged particle beam, And a multiprocessor image defect inspection computer connected to the charged particle detector to confirm the above defects. Such a system is suitable for implementing a preferred embodiment of the present invention.
[0035]
Similarly, on March 26, 1996, Meisburger et al. U.S. Pat. No. 5,502,306, “ELECTRON BEAM INSPECTION SYSTEM AND METHOD”, describes a test system suitable for the practice of the present invention. In '306, numerous embodiments of methods and apparatus for particle scanning systems and automated inspection systems suitable for implementation of preferred embodiments of the present invention are disclosed. Applicants incorporate this reference, U.S. Pat. No. 5,502,306, in its entirety.
[0036]
The inspection system used in the practice of the present invention can operate in several modes (e.g., array, die toy, die tooter based). In each of these modes, defects are detected by comparing an electron beam image obtained from scanning the substrate with a standard image. In array mode, a signal from a first portion of an array of substantially identical circuit elements is compared to a signal from a second portion of such an array. In a variation of this technique, the image of the array can be compared with an electronic modification of the same image, and repeated content can be subtracted. The difference image resulting from the comparison will indicate a defect. An example of such a system is described on 16 July 1996 by Evans et al. U.S. Pat. No. 5,537,669 issued to U.S. Pat. No. 5,537,669, “INSPECTION METHOD AND APPARATUS FOR THE INSPETION OF EITHER RANDOM OR REPEATING PATTERNS”. The entire patent is incorporated herein by reference.
[0037]
In die-to-die inspection, signals from two dies on the same substrate are compared with each other. In die-database inspection, the signal from one die obtained from the electron microscope is compared with the signal obtained from the database. The database may comprise design data that is used to create a die and to generate multiple complete images when the die is free of defects. For example, each image includes a voltage contrast signature that represents how the corresponding test image looks without defects. The complete image is compared with the corresponding image obtained from the die. Alternatively, the database may include multiple complete images themselves. In the case of die-to-die inspection, the function of the defect inspection processor is to compare the image data obtained from the first die with the image data obtained from the second die, and in the case of die-database inspection. Is to compare the image data obtained from the die with the data obtained from the database adapter. The defect inspection processor is preferably a multi-pixel image computer that allows efficient comparison to be performed. In certain embodiments, the processor operates with a pixel resolution size in the range of about 25 nm to 2000 nm. More generally, the processor operates with a pixel size nominally equal to twice the line width of the test structure to maximize throughput with optimal signal-to-noise sensitivity. The routine and basic embodiment of the defect inspection processor was described on February 17, 1987 by Sandland et al. U.S. Pat. No. 4,644,172 “ELECTRONIC CONTROL OF AN AUTOMATIC WAFER INSPECTION SYSTEM”. The entire patent is incorporated herein by reference. Other inspection techniques (eg, die-truth table and die-complete image) are described below.
[0038]
The sample to be examined can be held by a holder placed under the electron beam train on the xy stage. The sample needs to be arranged in a stage shape so that the movement of the stage in the x direction is substantially perpendicular to the x axis of the central area of the sample pattern (ie, the area to be inspected). Once the sample is properly placed, the inspection process begins.
[0039]
The beam train and analog deflection circuit direct the electron beam toward the surface of the sample, and the detector detects at least one of secondary electrons, backscattered electrons, and transmitted electrons. The position and movement of the stage during sample inspection is controlled by a stage servo.
[0040]
FIG. 1 shows an overall block diagram of an inspection system 10 suitable for implementing one embodiment of the present invention. The system 10 shows an automatic inspection device for X-ray masks, wafers, and other samples, which uses a scanning electron microscope as a sensor.
[0041]
A sample 57 to be inspected is held by a handler 34 in a holder disposed under the electron beam train 20 on the xy stage 24. This is accomplished by the system computer 36 instructing the sample handler 34 to move the subject sample 57 from the cassette. At this time, the plane or notch (see FIG. 4 a) of the sample 57 is automatically detected, and the sample 57 is placed in an appropriate direction with respect to the handler 34. The sample is then mounted under the beam train 20. The operator then visually observes the mask through the optical positioning system 22, and the x-direction movement of the stage is substantially perpendicular to the x-axis of the central area of the sample pattern (ie, the area to be inspected). As such, a positioning point on the sample (which may be any shape on the sample selected by the operator) is placed. Thereby, the rough adjustment of the position is completed.
[0042]
A fine adjustment of the position is then performed by the operator scanning the sample with an electron beam and observing the image on the image display 46. All positioning data then operates in conjunction with the system computer 36 to calculate the actual combination of x and y motion needed to scan the die along its x and y axes. It is stored in the positioning computer 21. This eliminates the need for the operator to perform a positioning operation on the same type of sample. Once the sample is properly placed, the inspection process begins.
[0043]
Next, the beam train 20, its optical positioning system 22, and the analog deflection circuit 30 (described in detail below) direct the electron beam toward the sample surface 57, and the detector 32 provides secondary electrons, Backscattered electrons and electrons passing through the sample 57 are detected. The operation and collection of data from the exposure is performed by the beam train control computer 42, the video frame buffer 44, the acquisition preprocessor 48, the deflection controller 50 and the memory block 52. The bus (VME1) 29 functions as a communication link between subsystems.
[0044]
The position and movement of stage 24 during inspection of sample 57 is controlled by stage servo 26 and interferometer 28 under the control of deflection controller 50 and positioning computer 21.
[0045]
If the comparison mode is die-database, a database adapter 54 that communicates with the memory block 52 is used as a source of signals corresponding to the expected die type.
[0046]
The actual defect processing is performed on the data in the memory block 52 by the defect inspection processor 56 together with the post processor 58. At this time, communication between these blocks is performed via the bus (VME2) 31.
[0047]
The overall operation of the system is performed by a system computer 36, a user keyboard 40, and a computer display 38 that communicate with other blocks via the data bus 23. The data bus 23 may be similar to an Ethernet bus (Ethernet is a registered trademark of Xerox Corp.).
[0048]
In one embodiment of the present invention, scanning with a continuously moving stage provides significant advantages. That is, sample measurements are obtained while the stage (or beam) is moving. Conversely, stepped systems alternate between cycles of movement and sample measurement. In addition, the stepped system requires time to remain stationary until a sample measurement can be obtained after each move. The embodiment shown in the figure provides a more efficient mechanism for obtaining measurements while the sample is moving without requiring a quiescent time.
[0049]
In the illustrated embodiment, the stage moves continuously in the x direction. More preferably, the stage continuously moves in the x direction at a constant speed. A typical speed for continuous movement of the stage is about 1.0-200 mm per second. It should be noted that the movement in the x direction can also be realized by moving the electron beam instead of the stage. However, the movement may be performed by actually moving the electron beam train or by deflecting the beam. Furthermore, the stage itself is operable to move in both x and y directions or a combination thereof.
[0050]
At the same time as the stage moves continuously in the x direction, the electron beam is repeatedly deflected to reciprocate in the y direction. In a typical application of the present invention, the electron beam can reciprocate at about 100 kHz. The deflection is preferably substantially undistorted and substantially perpendicular to the surface. In this way, the imaging characteristics are uniform over the entire scanning field.
[0051]
FIG. 2 shows a scanning pattern. In this figure, one test chip 100 is shown above the substrate. Within the test chip is included a scan swath (or “significant area” or “primary scan area”) 101 to be inspected. During die inspection, an effective scanning movement in the x direction is realized by the moving stage, and an effective movement in the y direction is realized by deflection of the electron beam.
[0052]
As a result of combining the stage and the movement of the electron beam, the beam path with respect to the substrate forms a scanning pattern 102 as shown in FIG. The scan pattern 102 is shown as a sinusoidal pattern, but other triangular patterns and other shapes are possible, and data is obtained when the beam is scanned in either or both directions. It can be collected from the resulting secondary electrons or other radiation. In the illustrated embodiment, the length of the scanning swath is the width of the test tip (eg, 7 mm for a 7 mm × 7 mm test tip, 10 mm for a 10 mm × 10 mm test tip). However, the scanning swath may be any length that is smaller than the width of the test chip and within the scope of the present invention. The scan swath width should be as large as possible. In currently marketed systems, the scan swath width is between 50 μm and 500 μm. More preferably, the scanning swath is about 200 μm.
[0053]
In one embodiment, the scanning swath includes at least a portion of each test structure on the test chip. Thus, all test structures can be tested in a single scan. Scan swaths can include a variety of different types of test structures. This allows the system to detect different types of defects by scanning one scan swath once. However, it is also possible to create a structure with a plurality of swaths, each swath having all or part of one type of test structure. The various types of test structures that can be provided for scanning swaths are described in detail below.
[0054]
FIG. 3 is a flowchart illustrating a process and test procedure according to one embodiment of the present invention. First, in operation 1, a series of initial manufacturing process steps are performed to form a test structure such as a conductive line over the substrate. In action 2, the structure is inspected by an electron beam inspection system. In operation 3, the signal detected from the electron beam inspection is processed to determine whether a potential defect such as an open or short in the conductive line has been detected. If no significant potential defects deserving the end of production have been detected, then in operation 4 the subsequent manufacturing process steps are performed. It is not uncommon for inspection to find a large number of potential defects. However, even for product wafers, significant defects are often detected, although not so many that lead to the end of the manufacturing process. If the process is still characterized and the wafer is not a product wafer, processing of such wafers and test structures can continue even though there are many serious defects.
[0055]
The number of test structures present in a lot of wafers and the relative area required for the test structures can be varied. As an example, several reticles with different areas for the test structure can be provided that can be used in the manufacturing process. A reticle having a relatively large area for the test structure is used for a particular wafer in the lot (or spans a predetermined portion of such wafer) and a reticle having a relatively small test structure is It can be used on other wafers (or span the rest of such wafers). Because the relative extent of each type of reticle determines the number of test structures in a lot, this part may vary from lot to lot depending on the test conditions of the process in which each lot is manufactured. Can do. Alternatively, a portion of the reticle containing the test structure can be “cut” to a sufficient extent to form the desired predetermined number of test structures, with the remaining portion of each wafer covered with the product structure.
[0056]
If there is no next manufacturing process step, the manufacturing process ends at 5. If there is a next manufacturing process step, the next manufacturing process step is started at 6.
[0057]
However, if a potential defect is detected in action 3, the position of the potential defect can be recorded in action 7. In action 8, the potential defects are repositioned and scanned by electron microscopy, optical microscopy, energy dispersive x-ray spectroscopy (EDS), and / or focused ion beam (FIB) techniques, or these Characterization can be performed using various characterization techniques, such as a combination of techniques. Finally, in operations 9 and 10, information from the characterization process is analyzed and the resulting data can be used to eliminate process conditions that cause defects. Of course, if the defect characterization process of the test is non-destructive, the substrate can be returned to the process line for further processing.
[0058]
C. Test chip design
Scanning the test chip with an apparatus comprising a moving stage provides a fast and efficient method for testing semiconductor device defects. It should be noted that the test structure need not fit completely within the scan swath in order to be tested, as described in detail below. For many structures, voltage contrast testing can be accomplished by scanning only a small portion of the test structure. In such a case, when a defect is detected by the voltage contrast technique, the exact position of the defect can be determined in the next operation, even if the defect is located outside the scanning swath.
[0059]
As will be described in detail below, a myriad of different types of test structures can be fabricated in a scanning swath. Some of these test structures are described in detail below. Such a structure can comprise via chains and conductive lines, which are preferably (but not necessarily) partly present in the scan swath. A preferred structure of the via chain and the conductive wire will be described in detail. Such structures can further comprise smaller test elements such as contact arrays or elements designed to detect defects caused by specific process steps such as chemical mechanical polishing. These smaller elements are preferably present (but not required) entirely within the scanning swath.
[0060]
Furthermore, it should be noted that the test structure described herein can be tested by techniques other than those described as preferred embodiments. For example, such a test structure may be inspected by a particle beam that does not include a continuously moving stage. In such a technique, for example, a step-and-repeat type stage is provided, and an electron beam scan is performed while the stage is stationary, and then the stage is moved to the next electron beam scanning step. It is supposed to be stationary before it is executed. One embodiment of the step type test structure will be described in detail with reference to FIG. It is also possible to use voltage contrast techniques that do not scan with a particle beam with many of the test structures described herein. For example, a photon beam (rather than an incident electron beam) can be used to cause voltage contrast. The photon beam can be used under conditions suitable for a photoelectron microscope (“PEEM”).
[0061]
D. Typical test chip
This section describes a representative test chip specifically designed to fully realize the advantages of the present invention. However, it should be recognized that the particular designs described herein are exemplary only and that many other designs and configurations are possible within the scope of the present invention.
[0062]
Some embodiments of the present invention include multiple layers of integration using various levels of conductors that are separated from other conductors and substrates by dielectric layers, including semiconductor structures and metal wiring or other interconnects thereon. The circuit structure is described as an example. As is well known to those skilled in the art, in such a multi-layer structure, the first conductor (M1) and the second conductor (M2) are formed by vias formed through the interlayer dielectric (ILD). Can be connected. Similarly, a contact can be formed between the conductor and the substrate. The defect detection system of the present invention is capable of detecting open, short in layer (in M1 or M2) or short in layer (between M1 and M2) caused by systematic or irregular errors during the manufacturing process. There is.
[0063]
Furthermore, certain embodiments of the present invention can detect defects caused by certain process steps such as lithography steps, dry etching steps, vapor deposition steps, chemical mechanical polishing (CMP), and the like. As is well known to those skilled in the art, the CMP process is often used to planarize structures formed during a multilayer deposition process. These structures can be used for damascene interconnects, conductive plugs, or other purposes. The CMP process is expected to become more important as the semiconductor industry moves to copper interconnects. This is because copper cannot be easily dry-etched (the etching product is non-volatile), but can be easily processed using CMP. However, the CMP process can be dishing (causing openness) or copper if the circuit layout changes significantly in terms of density, pitch, and / or horizontal aspect ratio (height: width). Circuit components that function by smearing (causing short circuit) may be removed by polishing. Defects caused by the CMP process are preferably detected during the inspection process.
[0064]
4A and 4B show a semiconductor wafer 200 with a die array 202 prepared in accordance with the principles of one embodiment of the present invention. As shown in FIG. 4B, the array 202 consists of a plurality of test dies 204 and a plurality of actual product dies 206 that include the intended integrated circuit. As will be described below, the test die 204 can perform in-line inspection during the actual manufacturing process of the integrated circuit to locate defects, identify defects, identify defect types, and identify defect densities. And
[0065]
The ability to detect defects in-line (ie, during the manufacturing process) is a significant advantage of the present invention. Unlike the semiconductor device functional test performed on a wafer completed by the wafer inspection method, the present invention can perform the test in-line. This is a better and timely information for engineers managing the manufacturing process and gives them the opportunity to repair equipment and change process conditions to improve yield before many devices are lost as scrap. give. On the other hand, if an engineer needs to wait for the device to complete processing, it can be too late and yield can be lost, resulting in millions of dollars in losses. Further, the test method of the present invention can also be used as part of an advanced process control (“APC”) system. In that system, data from the test process is sent to an automated control system that improves process yields with little or no human intervention, based on software algorithms that take into account the equipment and process technology used in the manufacturing process. . For example, a test structure designed to detect CMP overpolishing can automatically provide feedback to the CMP process and provide data that causes process changes such as reduced polishing time and reduced pressure on the polishing pad.
[0066]
The test die 204 may be regularly placed at the intersection of rows and columns as shown in FIG. 4B. Such regular placement can also be used as a map to evaluate final test data and to locate specific types of defects that occur at various locations on the wafer during the manufacturing process. In one embodiment, the test die 204 provides a set of statistically significant test data to minimize the cost of inspection and reduce the predetermined area on the wafer 200 so as not to adversely affect product yield. is occupying. Such a test die has approximately the same dimensions as the product die in that range (10 mm × 10 mm or 7 mm × 7 mm). Alternatively, when developing a new process, the entire wafer can be composed of test dies.
[0067]
As shown in FIG. 4C, each test die 204 has a quadrilateral or triangular shape defined by first, second, third and fourth edges 204A-204D, and has a number of portions: It may be configured to have a first portion 206 and a second portion 208 separated by an intermediate portion 210. Portions 206-210 define the test site where the test structure is formed. The portions 206, 208, 210 of the test die 204 are preferably rectangular in shape.
[0068]
As shown in FIG. 4C, the first portion 206 can be defined by a proximal edge 206A, a distal edge 206B, a first edge 207A, and a second edge 207B. The second portion 208 can be defined by a proximal edge 208A, a distal edge 208B, a first edge 209A, and a second edge 209B. Finally, the intermediate portion 210 can be defined by the distal edges 206A and 208A, the first edge 210A and the second edge 210B.
[0069]
As will be described in detail below, the test structure is a structure formed at various stages of the semiconductor IC manufacturing process. Once the portions 206-210 are defined above the test die 204, the portions 206-210 may be further divided into multiple portions (preferably triangular) as shown in FIG. 4C. In the plurality of parts, test structures can be arranged according to the type of test.
[0070]
In certain embodiments, the first portion may include a first section 212, a second section 214, and a third section 216. Similarly, the second portion 208 may be divided into three sections: a fourth section 218, a fifth section 220, and a sixth section 222. As will be described in detail below, not only portion 210 but also sections 212 through 222 are subject to discovery by the design of the test structure (ie, the type of functional structure to which the test structure corresponds, or the design of the test structure). A group of one or more test structures arranged in a predetermined manner according to the type of defect present). The number of each type of test structure in a given part, test structure, or entire wafer provides a statistically significant sample of such test structure, where a statistically significant number of defect areas are found. To be selected. This number varies depending on the expected yield of chips on the wafer. For example, in a low-yield process (when expected to be found in a process that is under development and not producing), the number of test structures required to obtain a reasonable sample size will be relatively small. Conversely, higher yield processes will require larger sample sizes (and thus more test structures). The number of test structures may vary according to the chip manufacturer's goals. For example, if the chip manufacturer does not want to occupy much space on the wafer for the test structure, the number of such structures may be relatively small. If a process problem occurs, the number of test structures present on each wafer can be increased (to provide more test data about the process to the manufacturer) until the problem type is identified and resolved .
[0071]
Data from such tests can also be used by circuit manufacturers that do not have factories or manufacturing companies that contract their manufacture. For example, the test structure may be inspected during the manufacturing process by the manufacturing company. Second, IC companies that do not have factories re-inspect the same test structure prior to receipt to produce acceptable results in reliability testing to determine whether the wafer lot has an acceptable yield. Or whether it has acceptable quality. The data can also be used to improve the design so that IC companies without factories can manufacture integrated circuits more easily with high yield and / or quality. This data is used as part of the purchase process so that companies without factories can make payments to manufacturers based at least in part on statistical values calculated from the testing process, such as forecast yield. Also good. For example, if payment is made based on a die that is predicted to be good, a lot with 500 dies and 80% predicted yield based on voltage contrast testing is predicted to be good. The IC manufacturer will be paid for the 400 die. Testing by a company without a factory should be facilitated by using stacked vias containing stacked conductive plugs to form a vertical conductive path that taps down to the lowest test structure, as described in detail below. Can do. Such test structures are otherwise difficult to access because they are buried under the insulator during the next process and cannot be observed with the electron beam system. However, with the addition of one or more conductive taps, these embedded shapes can be retested even after all layers of the entire wafer have been processed. This allows a semiconductor company that does not have a factory to test the wafer and verify the test data supplied by the manufacturing company. As will be described below, inspectable pads may be added to the voltage contrast test structure described above, for example, so that standard wafer inspection techniques can be further implemented without the need for expensive SEM equipment.
[0072]
Such test data can also be used to determine the need for other types of tests. For example, a reliability test is a test that is relatively time consuming and expensive. Process data from the test structure of the present invention to better predict whether reliability testing is necessary and how many chips from each lot should be tested Can do. For example, if test data from at least a particular type of test structure of the present invention indicates that there is a defect that is close to, but not reached, a significant amount or level that affects the function of the device, It is suggested that a mechanism of sexual deficiency can occur. Under such circumstances, reliability test conditions can be expected to cause unacceptable levels of failure of such devices. To verify this, it is possible to conduct a reliability test and to reduce the extent of such a predicted lack of reliability even before the reliability test is actually performed. , Can change the process (if desired).
[0073]
As described above, for example, the first section may comprise a test structure that includes an M1 interconnect level. The test structure formed in the first section 212 may be an M1 processing stage of the integrated circuit that allows testing and evaluation at this stage of manufacture. At this stage, inspection may be performed to detect an open or in-layer short in the M1 interconnect wiring in-line during the manufacturing process. Similarly, test structures for the M2 and M3 interconnect lines are formed in the third and fifth sections 216, 220, respectively. The M2 and M3 test structures also allow detection of interlayer shorts, such as open and short, shorts between M1 and M2 interconnect test structures. Via chain test structures may be formed in the second, fourth and sixth sections 214, 218, 222. The second section 214 may be, for example, a via chain formed between the M1 and M2 interconnect lines. In this regard, the fourth and sixth sections 218, 222 may have via chain test structures that are vias between the M2 and M3 interconnect lines and the M3 and M4 interconnect lines, respectively.
[0074]
As described below, the via chain test structure has two types of tests: an open-only test that detects an open in the via chain, an open in the chain, and between adjacent conductors or metal shapes. Open and short tests that detect both shorts.
[0075]
In this embodiment, various other groups of test structures are formed along the middle portion 210 of the die 204. As will be described in detail below, such a test structure group may comprise CMP test structures, overlay or misalignment structures, individual contacts, as well as dummy CMP fills. In this embodiment, the dummy CMP fill is available occupied on the product die, such as an available area along the corner of the die or an unoccupied area found between adjacent circuit placement portions. It can also be formed in a region that is not.
[0076]
As shown in FIG. 4D, sections 212-222 may be further divided into a plurality of subsections or modules, and may have test structures with different critical dimensions across such modules. However, the critical dimension often indicates a predetermined test size of the shape or a distance between the shapes. By using test structures with different critical dimensions, high quality IC shapes can be formed. In other words, if a particular acceptable critical dimension yields the best results for a particular design shape, adopt that critical dimension and change the design rules for the process or product group accordingly. Can do. More importantly, test structures implemented in various structures and critical dimensions help determine which of the device structures and dimensions tend to cause a particular defect. The distance between them can predict the defects that occur between them.
[0077]
In this regard, for example, the M1 interconnect line of section 212 may be formed in the first, second, third, fourth, and fifth modules 212A-212E. However, each module has one type of test structure group formed to have a critical dimension different from the critical dimension used in the other modules. Modules 212A-212E serve to determine which critical dimensions for the M1 interconnect are more susceptible to open, short and interlayer short type defects. Similarly, the first, second, third, fourth and fifth modules 216A through 216E of section 216 and the first, second, third, fourth and fifth modules 220A through 220E of section 220 are Provide interconnect lines with different critical dimensions for open, short and interlayer short type defects for the M2 and M3 process steps, respectively.
[0078]
According to FIG. 4D, section 214 may consist of two modules, namely a first and a second module 214A, 214B. Each module comprises a via chain test structure formed between the M1 and M2 interconnect levels. In this embodiment, the first module 214A comprises a via chain formed to detect open type defects, and the second module 214B is for detecting both open and short type defects. Provide a via chain. As described in detail below, in the second module 214B, individual via chain lines detect and observe both shorts occurring between via chains and adjacent metal lines, and open in individual chains. In order to do so, it may be arranged between adjacent metal wires. Similarly, first and second modules 218A, 218B of section 218 and first and second modules 222A, 222B of section 222 are both open and short types as described for modules 214A and 214B. A via chain test structure for detecting and observing an open in addition to the defect of FIG.
[0079]
It should be noted that the test chip described above is exemplary only. For example, the test structure may be arranged elsewhere in such a chip, or the specific test structure described here may not be provided. Many different configurations are possible within the scope of the present invention.
[0080]
E. Typical test chip test
As described above, an electron beam inspection system such as SEM can be used. This action generates a signal when the electron probe strikes the die surface at a predetermined point. The signal can be collected by a detector to give information about the point. The electron beam system moves the wafer to place the first test chip at a low magnification (60 to 500 ×) position, and linearly aligns the first line having a shape like an open / short test pattern, for example. Are programmed to draw electron beam scan lines therethrough in raster mode.
[0081]
In one embodiment, the primary signal source includes electrons. Secondary electrons are generated as a result of the incident (primary) electron beam impinging on the surface of the wafer. Secondary electrons are emitted from the wafer and collected by a detector to produce an image. In the image, for example, the emission characteristics of secondary electrons with high intensity appear visually brighter than the emission characteristics of secondary electrons with low intensity. When the variation in the intensity of secondary electron emission is plotted with respect to distance along the length of the swath that the electron beam scans, the intensity distribution of the scanned test structure is obtained.
[0082]
In the die-die or die-full image inspection mode, the system calculates the strength distribution of the defect-free test structure as shown in the database for the corresponding structure on the test chip provided by the electron beam section. Works to match against intensity plots. In one embodiment, the die under test is compared to an image showing how the die under test looks when there are no defects. For example, the array of interconnect lines may be alternately grounded and floating. In this case, a complete image with alternating dark and bright interconnect lines is generated. This comparison operation allows the detection of all defects in the test structure in the form of missing and / or protruding peaks. Alternatively, the strength peak of the test structure may be compared to a predetermined set of expected values, for example as prepared in the truth table. For example, a set of interconnect lines for a test structure under test is expected to have strength values that alternate between high and low. In one embodiment, each line is compared to a predetermined threshold to determine whether the conductive line is grounded or floating. These high and low values are then compared to the expected high and low values. The test structure itself may be configured to facilitate die-full die inspection and die-truth table inspection. In one embodiment, the length of the proximal end of the test pattern (i.e., the stub) has various lengths, and this length is taken as the corresponding full die portion or truth table value. You may match. For example, two stubs in a row may have the same length to indicate a starting or reference point for initiating the comparison procedure (other stubs have a variety of the same length). In the second example, programmed defects are incorporated at regular intervals along the scan path to form a fixed grid to help locate the defects during the next analysis.
[0083]
The generated complete image and / or a set of predetermined strength values or a truth table may be provided to the customer along with the corresponding test structure so that the corresponding test structure can be easily inspected. Of course, standard die-to-die and array inspection techniques may also be used. However, die-database, die-complete image, and die-truth table techniques are more efficient because they do not have to find a complete die or part of a die for comparison with the die under test This is an inspection procedure.
[0084]
Scanning electron microscopes, in the voltage contrast mode, allow to distinguish between a charged floating conductor shape and a shape grounded to drain charge in the form of visual or strong contrast. These shapes are visually monitored on a CRT screen and are preferably stored and analyzed electronically. This principle was used to manually locate, identify, and characterize in situ defects that previously caused unintentional breaks to ground and unintentional shorts to adjacent grounded shapes in the product chip. It was used for. However, such manual product inspection processes are extremely monotonous and slow due to the complexity of product design and the need to display high magnification information sources on CRTs with poor SEM contrast. It has become a technology.
[0085]
In FIG. 5, a representative portion 400 of the test die 204 is shown in detail in plan view. Portion 400 details the components of first portion 206, second portion 208, and intermediate portion 210 of test die 204 (eg, in FIG. 4C). One technique of the present invention includes the first test structure 402 of the first part, the second test structure 404 of the second part of the test die 204 and the third test structure 406 of the intermediate part of the test die 204. It will be exemplified. During electron beam inspection of the test die 204, it can be seen that the electron beam is scanned across the middle portion in the direction of arrow A in raster mode. The electron beam is transmitted not only at the proximal ends (referred to as “stubs”) of the first and second portion test structures that are not positioned adjacent to the proximal ends of the first and second portions, but also at the intermediate portion. It also interacts with the test structure. In the following, the first, second and third test structures will be described in more detail.
[0086]
As described in detail below and shown in FIGS. 5, 6A, 6B, and 6C, the first test structure 402 includes a row of first conductors 408 and second conductors 409. The rows extend parallel to edges 204B and 204D and are disposed between the proximal and distal edges 206A, 206B of test die 204 (see FIG. 4C). The second conductor 409 is disposed between the rows of the first connectors 408 as shown in FIG. In certain embodiments, the proximal stub end 410 of the first connector 408 (hereinafter referred to as an interconnect line) is located at the proximal edge 206A of the portion 206 of the test die 204 (see FIG. 4C). And the distal end 412 of the interconnect line 408 is disposed at the distal edge 206B of the die portion 206. It will be appreciated that the first test structure 402 illustrated in FIG. 5 may show a plan view of any metal interconnect layer, such as M1, M2, M3 or M4. As described below, the distal end 412 of the interconnect line 408 is grounded to the substrate of the die 204 and the proximal stub end 410 is not connected and is not grounded to the substrate. As will be described below, the second connector 409 (referred to as the island member) is not grounded and helps to distinguish defects that occur in the grounded interconnect line 408 in voltage contrast mode. . These proximal ends of 408 and 409 may be extended to various lengths to expose the primary scan region, as described above. It will also be appreciated that the shapes of 408 and 409 may be straight lines without corners or islands, as shown in FIG.
[0087]
In the preferred embodiment, each stub 410 has a width that is the same as or smaller than the remainder of the interconnect line 408. That is, the extended flag area is not used. Because the stub width is less than or equal to the remainder of the interconnect lines, multiple interconnect lines can be packed in a simple array at high density. In other words, the proximal end of the test structure itself can be scanned “as if” in the primary scanning region. In this embodiment, the spot size of the inspection SEM is generally configured relative to the dimensions of the stub.
[0088]
According to the example test chip shown in FIGS. 4A-D, the test chip is preferably scanned in one pass. The scanning swath preferably includes the entire intermediate portion 210. Further, the portion 210 is preferably located approximately in the center of the test chip. Further, in one embodiment, the intermediate portions 210 of the plurality of test chips are aligned so that a single scan can be performed on the plurality of intermediate portions 210 on the plurality of test chips.
[0089]
However, the scanning swath preferably includes a larger area than portion 210. In certain embodiments, all test structures on the test chip are scanned in a single pass. Therefore, when the width of the scanning swath is 200 μm, for example, the width of the portion 210 may be 190 μm. In such a case, the scanning swath may include a range extending up to 5 μm above and below the portion 210.
[0090]
In such a case, it is preferable that all the test structures of the test chip can be inspected by scanning the scan swath (for example, the primary scan region) only once. In doing so, the scan swath scan scans all of the test structures present in portion 210. Such scanning further scans a portion of the test structure of portions 212, 214, 216, 218, 220 and 222. A scan swath scan causes a defect in one of the test structures of portions 212, 214, 216, 218, 220 and 222 (typically located outside the scan swath (eg, potential secondary scan region)). ), The system according to the particular embodiment then performs the steps of locating and characterizing the defect.
[0091]
It should be noted that the scan swath need not be centered on the test chip, but may be located elsewhere on the chip. For example, the scanning swath may be located at the bottom or top of the chip. For example, if the scan swath is located at the bottom of the chip, the scan swath may include a test structure that is entirely within the scan swath, with a portion of the test structure extending upward from the scan swath.
[0092]
Furthermore, the test chip may be designed to have more than one scan swath. In other embodiments, a plurality of intermediate portions 210 are provided in one test die so that the aspect ratio of each test structure is optimized. For example, the interconnect lines 408 may be shortened to reduce resistance, capacitance, and / or the time required to locate such line defects. In another embodiment, the intermediate portions (eg, 210) and their corresponding first and second portions (eg, 206 and 208) are arranged so that a scan of the intermediate portion can be performed in array mode. Composed. Further, the scanning swath need not be the same width as the test chip, and may be located entirely within the test chip. In fact, it is possible to have several scanning swaths in one test chip, all placed completely inside the chip. However, it should be appreciated that the scan swath preferably includes a specific test structure that is entirely contained within the scan swath and other specific test structures that are only partially contained within the scan swath.
[0093]
F. Conductive wire test structure
One type of test structure that can be provided above the test tip may have a tip that projects into the primary scan swath. In a preferred embodiment, such a test structure is only partially present in the scan swath. It is preferred to scan only a small portion of the conductive lines first. Once a defect is detected, further testing and analysis can then be performed to more accurately locate the defect and characterize the defect.
[0094]
6A-6C are a detailed plan view, cross-sectional view, and side view of a portion of the test structure 402, ie, the M1 wiring test structure. 6A-6C, an M1 interconnect 408 and a floating member 409 are formed over the substrate 420 using conventional semiconductor IC process techniques such as chemical vapor deposition (CVD), patterning and etching techniques. An insulating layer 421, such as an oxide layer, is inserted between the substrate 420 and the M1 interconnect 408 to insulate the M1 interconnect 408 from the substrate 420. The island member 409 is separated from the M1 interconnect by a dielectric layer 422, and the island member 409 is configured to be elevated as shown in the side view of FIG. 6C. The interconnect line 408 is connected to the substrate 420 via a contact etched through the oxide layer 421. The interconnect line 408 is electrically grounded to the substrate 420 via the contact 424.
[0095]
The electron beam may be scanned across the exposed metal distal end 410 of the interconnect 408 and floating member 409 to detect defects such as, for example, open, shorts, and intra-layer shorts in the M1 wiring. This preferred embodiment can immediately calibrate the degree of grounded or floating shape scan during the primary scan. Tests that detect intra-layer shorts and opens are performed by scanning an electron beam across the distal end 410.
[0096]
Since the island member 409 is not grounded during the electron beam inspection, the electrons of the incoming incident electron beam charge the island member 409. Contrary to the grounded interconnect 408, the electrons cannot find a path to ground and no secondary electron emission occurs. As a result, the island member 409 charged by the beam remains nominally dark. However, assuming there are no defects, due to the connection to ground, the interconnect line 408 will leave the charge drained, causing a significant amount of secondary electron emission. The secondary electron emission is detected by a detector of an electron beam system. For a grounded interconnect line 408, if such an interconnect line 408 has not failed, electrons from the beam will find a path to ground and secondary electrons will radiate from the particular interconnect line 408. Is done. As a result, the interconnect line 408 appears brighter or shiny, indicating that the corresponding interconnect line has no open (ie, no defects). The intensity peak resulting from this secondary electron emission is recorded by the system to match the corresponding data for this particular test structure. However, if the line under test is faulty (ie, open), the emission of secondary electrons is reduced and the interconnect 408 remains dark. As described above, missing peaks are recorded by the system and will then point to potentially defective interconnects for further analysis. In another case where the interconnect line is shorted with another interconnect line for the same M1 wiring, the interconnect lines 408, 409 will shine, suggesting an electrical short between them.
[0097]
With a centralized test die, the quality of M1 wiring or other levels of wiring can be monitored throughout the manufacturing process. During fabrication of multi-layer metal structures, elevated temperatures can cause shorts and opens in already formed interconnect patterns with potential defects. This problem can be monitored using the test structure shown in FIGS. 7A and 7B. In the following, for the sake of clarity, the island member 409 is not shown in the drawing that provides the cross-section.
[0098]
FIGS. 7A and 7B show a portion of a test structure 402 having M2 interconnect wiring 430 and island elements 432 on top. That is, the M1 interconnection wiring is hidden. As shown in the cross-sectional view of FIG. 7B, the M1 interconnect line 408 is connected to the substrate 420 through the contacts 424, as also shown in FIG. 6B. Interlayer dielectric layer 433 is inserted between M2 interconnect layer 430 and M1 interconnect layer 408. A via 434 passes through the dielectric 433 and connects the proximal end 410 of the interconnect 430 to the M1 interconnect.
[0099]
However, in this embodiment, after the M2 process step, the M2 interconnect 430 forms an opening 436 adjacent to the via 434 between the interconnects 408 and 430 to monitor the quality of the M1 interconnect layer. And discontinuously formed by separating the distal portion 438 from the rest of the M2 interconnect. The opening 432 may be filled with an insulating material such as damascene oxide using techniques well known to those skilled in the art. The distal portion 438 will hereinafter be referred to as the first scanning element (further referred to as “tap” hereinafter).
[0100]
In this step of the process, the electron beam probe traverses the first scanning element 438 and island member 430 of the M2 interconnect to detect defects such as open, shorts, and intra-layer shorts in the M1 wiring. May be scanned. Tests to detect intra-layer shorts and opens are performed by scanning an electron beam across the scanning element 438. If the M1 interconnect line 408 has not failed, the electrons from the beam will find a path from the scanning element to the ground through the M1 interconnect 408 to the substrate. As a result, secondary electrons are emitted from the scanning element 438 and the M1 interconnect line 408 is shown to be in good condition even after the M2 wiring process step. On the other hand, if the M2 wiring process causes an open in the M1 interconnect 408, the first scanning element 438 remains dark because the first scanning element 438 does not emit secondary electrons. If the rest of the M2 interconnect 430 is shorted to the underlying M1 interconnect line, the electrons of the electron beam will find a path to ground, so the shorted M2 interconnect and the corresponding scanning element Shines, suggesting a short between the M1 and M2 wires in the interconnect.
[0101]
In a configuration according to the principle illustrated by FIG. 7B, it is also possible to use stacked vias (vias that extend upward through multiple layers). Thus, for example, one or more stacked vias may extend from M1 to M3 to allow testing of M1 integrity after processing of M3. Further, redundant vias (ie, multiple vias) may be provided at any single via (eg, 234, 424) location. Redundant vias tend to have fewer defects than single vias, but redundant vias have slightly more complex design requirements.
[0102]
As shown in FIGS. 8-10, the integrity of the M1 interconnect 408 can also be detected after processing of the third, fourth, and further metal interconnect layers. For example, in FIG. 8, an M3 interconnect 440 having a first scanning element 442 connected to the first scanning element 438 of the M2 interconnect 430 can be formed above the interlayer dielectric 444. In other words, the stack plug (first scanning element 442, 438) is formed to monitor the opening inside the buried metal layer M1. As shown in FIG. 9, by forming a number of vias 446 between the M3 and M2 interconnects, a second scanning element 448 is formed to monitor possible shorts between the M1 and M2 interconnects. can do. During the scanning swath electron beam inspection, the proximal end of the M3 interconnect may be scanned. Similarly, as shown in FIG. 10, after forming the first and second scanning elements 452, 454 of the M4 interconnect 456, not only a short between the M1 and M2 interconnects (through the stack plug 452). Openings in the M1 layer can also be inspected through the scanning element 454.
[0103]
As shown in FIGS. 11-13, the same aspects can be applied to testing the M2 interconnect. As shown in FIG. 10, the M2 interconnect is grounded through the cut portion 450 of the M1 interconnect. As shown in FIG. 12, the integrity of the M2 layer can be tested using the first scanning element 452 of the M3 interconnect 440. As shown in FIG. 13, a short circuit that can occur between the M3 and M2 interconnects can be detected using the second scanning element 454 of the M4 interconnect after forming the M4 interconnect.
[0104]
The stacked test structure described above may be used for inspection of buried structures. A single test structure may include a mechanism for inspecting two or more buried structures at each of the different levels. For example, when the second tap is connected to an M2 conductive line that is grounded at the distal end, the first tap may be connected to an M1 conductive line that is grounded at the distal end. . Alternatively, a dedicated area for inspecting a particular buried layer (eg, as described with reference to FIG. 4D) may be provided. For example, the first region may comprise a test structure having taps to a first buried layer, and the second region may comprise a test structure having taps to a second buried layer.
[0105]
Further, each of the taps described above may be connected to a testable pad. In this way, parameter information regarding the buried layer can be obtained. That is, standard wafer inspection techniques can be used to inspect buried structures (eg, conductive interconnect lines) on completed or partially completed wafers. For example, leakage current may be measured in a buried interconnect structure with a short. In addition, crosstalk tests may be performed on buried structures via inspectable pads. In this embodiment, parameter information and voltage contrast information can be obtained from a buried structure. Hereinafter, such an inspectable test structure will be described with reference to FIG.
[0106]
G. Beer chain
As described in detail below, the second test structure 404 is present in the first via chain 500 row that can be formed in one particular module (see FIGS. 14A-14B) and in the portion 208 of the test die 204. It is preferable to include a second chain 501 formed in another module (see FIG. 4C). Via chains 500, 501 are located between the proximal and distal ends 208A, 208B of 204 (eg, in FIG. 4C) and extend parallel to test structure edges 204B, 204D. In certain embodiments, the proximal end 502 of the via chain 500, 501 is located at the proximal edge 208A of the portion 208 of the test die 204 (eg, in FIG. 4C) and is distal to the via 500, 501. End 504 is located at the distal edge 208B of die portion 206. It can be seen that the second test structure 404 illustrated in FIG. 5 can show a plan view of any via chain formed between any metal, such as M1 and M2, M2 and M3, M3 and M4.
[0107]
14A and 14B illustrate a portion of a test structure 404 that is formed between an M1 interconnect and an M2 interconnect and that includes a row of via chains 500 having a proximal end 502 and a distal end 504. According to the cross-sectional view of FIG. 14B, the via chain 500 may be formed over the entire substrate 506 that is insulated from the M1 interconnect line 508 by the oxide layer 510. A contact 512 formed through the oxide 510 grounds the M1 interconnect 508 to the substrate 506 and thus grounds the via chain 500 to the substrate 506. A series of vias 514 formed through the interlayer dielectric 516 connect the M1 and M2 interconnects 508, 518.
[0108]
As described below, the via chain test structure 500 allows an open-only test to detect an open in the via chain. In this step of the process, the electron beam probe may be scanned across the exposed metal of the M2 interconnect at the proximal end 502 to detect defects in the test structure 404, such as, for example, an open. If the via chain does not have an open, the electrons from the beam find a path to ground, suggesting that secondary electrons are emitted from the topmost M2 interconnect, and that the via chain is good. However, if the chain is broken, the M2 interconnect remains dark and is recorded by the system as a potentially defective chain for further processing.
[0109]
The via chain 501 shown in FIG. 14C is configured so that not only an open in each chain but also a short between adjacent chains can be observed advantageously. Therefore, the via chain 501 is formed as the via chain 500 is formed as shown in FIG. 14B except that every other via chain is not grounded to the substrate. For example, in FIG. 14C, the first row 520 and the third row 524 of the via chain 501 are grounded at the distal end 504, while the second row 522 is not grounded. The via chain in column 522 is not grounded to the substrate and cannot generate secondary electrons, so it remains dark unless it is shorted with an adjacent grounded via chain. If a via chain in column 522 is shorted with an adjacent column (eg, 520), the adjacent chain 520 provides a path to ground for electrons, thereby providing a via chain in both columns 522 and 520. Secondary electrons are generated at, thereby suggesting a short-type defect. In addition, the grounded via chains in the first and second rows 520, 524 are used to observe an open in the via chain, as described for the via chain 500 in FIGS.
[0110]
H. Test structure for defects caused by chemical mechanical polishing
As described in detail below, the third test structure 406 is disposed in the middle portion of the illustrated test die 204 and is distributed along the scan direction “A” shown in FIG. As described above, the third test structure may comprise, for example, an array of insulated contact test structures, CMP test structures, overlay test structures, and CMP dummy metal test structures. Each of these structures may be included in multiple modules.
[0111]
One embodiment of the present invention can detect defects caused by a chemical mechanical polishing (CMP) process. As is well known to those skilled in the art, a CMP process is often used to planarize the profile formed during a multilayer deposition process. During the process, the various layers are patterned by etching and the surface is not flat. Such undulations are planarized by a CMP process in order to perform the next light exposure process step. However, the CMP process may polish functional circuit components or cause an undesirable increase in density, pitch, and / or horizontal aspect ratio (height: width). Therefore, it is desirable to detect defects formed by the CMP process.
[0112]
In one embodiment, several test structures are provided for detecting defects caused by the CMP process. Several different structures for detecting defects from the CMP process are described below. Typically, these test structures are present in whole or in part within the scan swath of the test chip.
[0113]
1. Test structure for detecting pitch CMP defects
The test structure shown in FIGS. 16A-C illustrates a CMP pitch test pattern 700. In this pattern 700, test elements 702, such as metal lines representing the M1 interconnect lines, have substantially the same line width 704. Each metal line 702 is separated from each other by a space 706 that is substantially equal to the line width of the test line. Thus, the test pattern 700 has a constant density of about 50% line area. The test pattern 700 is configured so that every other metal wire in the pattern is grounded (see FIG. 6C). FIG. 6B shows one of the metal lines 702 that are grounded to the substrate 704 by a contact 710 formed through the insulating layer 708. Such test patterns can be formed in multiple modules with various critical dimensions for the test die.
[0114]
When the probe is scanned across the metal line 702 of the pitch test pattern 700 during electron beam inspection, if there are no defects, the grounded metal line emits secondary electrons and all lines are Suggest good. If one of the grounded lines is open, the line will remain dark, indicating a defect. If an ungrounded line is shorted with one of the adjacent grounded lines, both lines emit secondary electrons, thereby indicating a short circuit between them.
[0115]
As mentioned above, in a preferred embodiment of the present invention, the CMP pitch test pattern is generally located in whole or in part within the scan swath of the test chip. In this way, test pattern defects can be tested during scanning swath scanning.
[0116]
The CMP pitch test structure preferably comprises a metal wire having a length of less than 20 μm. More preferably, such a test structure comprises a metal wire having a length of about 10 μm or less. More preferably, such a test structure comprises a metal wire having a length of 5 μm or less.
[0117]
The test chip may have various CMP pitch test structures, each having a different pitch. The width of the metal line of the test structure having the widest line width is typically about 2 μm to 3 μm wide. Other CMP pitch test structures on the test chip may comprise fairly thin metal lines, for example, 0.05 μm lines. Most of the CMP pitch test structures on the test chip generally comprise metal lines with a width of less than 0.5 μm. More preferably, most of the CMP pitch test structures on the test chip comprise metal lines with a width of less than 0.2 μm.
[0118]
Typically, each of the CMP pitch test structures on the test chip occupies the same area (eg, 10 μm × 10 μm or 5 μm × 5 μm) so that all of the CMP pitch test structures have lines of substantially the same length. . However, the number of lines in the CMP pitch test structure is inversely proportional to the line width in the test structure. For example, if the line width is 1 μm, the 10 μm CMP pitch test structure comprises five lines, and if the line width is 0.5 μm, the 10 μm CMP pitch test structure is 10 μm. With a line of books.
[0119]
To save test chip space, multiple CMP pitch test structures may be placed together in one row. In general, in such cases, the width of the metal lines between the plurality of test structures will vary. For example, each metal wire extending in the y direction may be provided in the test structure, and six CMP pitch test structures may be arranged in one row in the x direction. The first and sixth test structures have wide lines, the second and fifth test structures have narrower lines, and the third and fourth test structures have narrower lines. May be included. However, it should be noted that in this example, the “wide line” preferably does not exceed a width of 1.25 microns.
[0120]
2. Test structure for detecting density CMP defects
FIG. 17 shows a cross-section of a CMP density test pattern 350 for monitoring the effects of the CMP process on a pattern comprising metal lines having various line widths and various spaces between adjacent metal lines. The CMP density test pattern 350 shown in FIG. 17 has four sections (351, 352, 353, and 354). Each section has four metal wires. In section 351, the metal line occupies about 50% of the space. In section 352, the metal line occupies approximately 37% of the space. In section 353, the metal line occupies approximately 25% of the space. And in section 354, the metal wire occupies about 12% of the space. Each section line preferably has approximately equal length and width, as shown in FIG.
[0121]
Similar to the test pattern described above for the CMP pitch test, the density test pattern shown in FIG. 17 is configured such that every other metal line is grounded. Thus, the density test pattern can be tested using voltage contrast in the same manner as described for the CMP pitch test pattern.
[0122]
The dimension of each section in the example shown in FIG. 17 is 5 μm × 5 μm. Therefore, the width of each metal line in the section 351 is 0.625 μm, which is the same as the width of each space between the metal lines, for example. The length of each metal line in the pattern is 5 μm.
[0123]
In the example shown in FIG. 17, the line width of each section is substantially equal in both length and width. Furthermore, the space in each section is also substantially equal in both length and width. Furthermore, each section occupies the same space (land) on the test chip. In addition, in the pattern, the combined width of the line and the right hand space is constant (in this example, 1.25 μm).
[0124]
It should be noted that the pattern shown in FIG. 17 may have additional lines extending in both the left and right directions. For example, one or more sections in which the width of four metal lines is wider than the space separating the metal lines may be provided on the left side of the section 351. One or more sections in which the width of the four metal lines is narrower than that of the section 354 may be provided on the left side.
[0125]
It should also be noted that the metal line may be much longer than 5 μm within the scope of the present invention. However, each metal wire is preferably 10 μm or less. More preferably, each metal wire has a length of about 5 μm or less. At the same time, it should be noted that in certain sections, the metal line may be of any width that fits in the land allocated to the metal line and the space adjacent to it. For example, the metal wire may occupy 100% of the allocated land. Or, for example, it may occupy nearly 4% or less.
[0126]
Furthermore, the number of metal wires per section may vary. In a preferred embodiment, each section has an even number of metal lines, more preferably eight. However, the section may consist of an odd number of metal lines. Furthermore, it is possible to provide sections having various numbers of metal lines in one pattern.
[0127]
In certain embodiments, the density test pattern is present in the scan swath of the test chip, in whole or in part, so that the pattern can be scanned and voltage contrast analysis can be used. Each metal line of the density test pattern is preferably entirely present in the scan swath so that it can be scanned. However, as long as the metal lines in the pattern are scanned so that the voltage contrast method can be used, there may be a configuration in which only a part is present in the scanning swath.
[0128]
FIG. 18 provides another example of a density pitch pattern 380 for CMP defect testing. The pattern comprises a plurality of metal lines 381 with a plurality of contacts 382 to ground. The pattern shown in FIG. 18 shows three different density patterns. In the illustrated embodiment, the test pattern metal lines are 5 microns or less in length, and the widest line (density # 3) is 0.2 microns or less in width. The metal wires of the plurality of metal wires 381 are alternately electrically insulated.
[0129]
3. Test structure for testing horizontal aspect ratio
FIG. 20 shows a cross-section of a CMP aspect ratio test pattern 740 with metal lines 742 having different widths and lengths to achieve reasonable utilization of land on the test die. As can be seen from FIG. 20, the horizontal aspect ratio of the line of the pattern 740 increases from left to right. The length increases from left to right, and the width increases from right to left. Similar to the CMP test structure described above, in this configuration, every other metal wire is grounded to the substrate, and the test structure 740 is repeated in various modules with different critical dimensions. As can be seen from FIG. 20, in one embodiment, the lines are pairs of lines having the same horizontal aspect ratio (and preferably the same dimensions). In each such pair (eg, pair 743, 744), one of the two lines is electrically isolated (floating) and the other line is electrically non-isolated (grounded) Preferably).
[0130]
It should be noted that the pattern 740 can be repeated above the test die, increasing or decreasing the space between the lines. This is true for all horizontal aspect ratio test patterns. Such repetition (a test pattern repeated with increasing or decreasing spaces between lines) can be used to form a row of test patterns above the substrate.
[0131]
FIG. 19 shows another horizontal aspect ratio test pattern 720. In this pattern, the horizontal aspect ratio increases from left to right, but the line length remains the same. The length is preferably 10 microns or less, and more preferably 5 microns or less. This pattern may be repeated on the test die similar to the test pattern of FIG. Again, the lines of the test pattern 720 are pairs of lines of the same dimensions, and the two lines of the pair are alternately electrically insulated. Test patterns 720, 740 are inspected in the same manner as CMP pitch test structure 700.
[0132]
FIG. 21 shows a further horizontal aspect ratio test pattern 750. The pattern comprises metal lines that increase in waterside aspect ratio from left to right. The lines have alternating contacts 752 to ground. Below each line, a scanning structure having a uniform size over the entire pattern 750 is provided. In one embodiment of the invention, the metal lines are scanned along the scanning structure (to ensure better uniformity). However, such a scanning structure is not necessary for the implementation of the present invention. However, it should be noted that such a scanning structure can also be used in the other CMP patterns (pitch and density) described above.
[0133]
I. Contact array
FIG. 15A is an example array 600 of insulating contact test structures 602 disposed in the intermediate portion 210. Such a structure allows monitoring of defective contacts in integrated circuits.
[0134]
The rows of the array 600 preferably extend parallel to the proximal edges 206A, 208A of the first and second portions 206, 208 of the test die 204 (see FIG. 4C). FIG. 15B illustrates a multilayer structure of an insulating contact test structure 602 formed over a substrate 604 using conventional semiconductor processing techniques. An insulating layer 606 such as an oxide layer insulates the portion 608 (M1 pad) of the M1 layer from the substrate 604. A contact 610 formed through the insulating layer 606 connects the M1 layer to the substrate 604. The interlayer dielectric 612 preferably insulates the M1 layer portion from the M2 layer portion 614 (M2 pad). The portion of the M2 layer is connected to the portion of the M2 layer by a via 616 formed through the interlayer dielectric 612, thereby establishing a connection to the ground of the M2 pad 614. In the illustrated embodiment, the M1 and M2 layer portions 608, 614 are connected by four vias, which are referred to as redundant vias. In this embodiment, according to the redundant via 616, it is possible to monitor the defect contact without considering the defect of the via, so that the defect mechanism can be limited to the contact 610. The configuration shown in FIGS. 15A and 15B ensures that any defect in any via 616 does not interfere with connection to the substrate 604. If at least one via 616 is not defective, a ground connection between the M2 pad and the substrate is established.
[0135]
During electron beam inspection, when the probe is scanned along the exposed metal column of M2 pad 614, if the contact 610 is not open, the electrons from the beam will find a circuit to ground and the secondary electrons will be Emission from the pad 616 suggests that the contact is good. If the contact is open, the pad 616 remains dark.
[0136]
J. et al. Test structure for monitoring deviations
As is well known in the semiconductor industry, each IC manufacturing process requires precise alignment control to prevent unwanted contact between devices and changes in device dimensions. 22A-22C show six types of overlay test structures 800a-800f that are used to observe misalignment problems that occur during the manufacturing process, such as misalignments that occur during patterning of the metal layer. Test structures 800a, 800d are "M1-contact" type structures and have M1 metal strips (804a, 804d, respectively) extending above the contacts (806a, 806d). Test structures 800b, 800e are “via-M1” type structures with M2 vias (806b, 806e, respectively) above the M1 metal strips (804b, 804e). Test structures 800c, 800f are "M2-via" type structures and have M2 metal strips (802c, 802f, respectively) extending above vias (806c, 806f). Each type of structure includes a test structure for measuring misalignment in the x direction (eg, FIG. 22A) as well as the y direction (eg, FIG. 22B). Of course, any other misalignment direction may be used.
[0137]
As illustrated in FIGS. 23A and 23B, each test structure may form part of an array that is used to determine whether a shift has occurred and to measure such a shift. An array of “M1-contact” type structures is shown in FIGS. 23A and 23B. The structures are machined so that they are substantially identical in shape, except for the location of the contacts (eg, 811 or 813). As shown in FIG. 23A, the central test structure 810E has a contact 811E that is perfectly centered when there is no misalignment. The contact of the structure located on the right side of the central structure has a larger negative y-direction misalignment toward the right. The rightmost contact 811i is offset so that it no longer contacts the M1 layer. Conversely, the contact of the structure located on the left side of the center has a larger displacement in the positive y direction toward the left. The leftmost contact 811a is offset so that it no longer contacts the M1 layer. Similarly, in the test structure of FIG. 23B, the deviation gradually increases in the positive and negative x directions.
[0138]
Contacts 811 and 813 are coupled to the substrate and grounded. Thus, when the test structure is aligned, certain test structures will contact the contacts and no other contacts will contact. As a result, in the voltage contrast test, the contacting test structure appears bright and the non-contacting structure appears dark. In the illustrated example, test structures 810a, 810i, 812a, and 812i (which do not touch contacts 811 or 813) appear dark and the remaining structures appear bright.
[0139]
However, if there is a shift, the part of the test structure that is expected to appear bright will actually appear dark and the part of the structure that is expected to appear dark will appear bright. The relative positions of the contacts 811 and 813 are selected so that the deviation can be easily measured. For example, the contacts of the array are designed to deviate from M1 by 0.0005 μm increments. Accordingly, the amount of misalignment may be determined based on how many test structures appear dark. For example, when only the rightmost test structures 810g to 810i (and the left structure) appear dark, there is a deviation of 0.0005 μm or less in the negative y direction.
[0140]
When using the die-to-die comparison mode for defect analysis, the overlay structure must have a corresponding set of structures that are not grounded. These ungrounded structures serve as references and are compared to the grounded structures to ensure that all connected overlay structures are detected. If no reference structure is provided, the results from the overlay structure will be inconsistent.
[0141]
K. CMP dummy metal filling
Another test structure that can be formed in the intermediate portion 210 of the test die 204 is a test structure that uses a CMP dummy metal fill as a test pad for testing vias. As is well known to those skilled in the art, the CMP dummy fill is a CMP process integrity of an auxiliary metal structure located above the wafer to facilitate uniform polishing of the wafer surface. They prevent the soft material from being rapidly corroded when the relatively soft material disposed on the surface is adjacent to the relatively hard material. In one embodiment, as shown in FIGS. 24A-24B, the metal fill may be processed into a multi-layer test structure to add vias and / or contacts to monitor the integrity of the CMP process.
[0142]
In an example test structure 902, a contact 904 is formed between the substrate 906 and a first metal layer portion 908 (first metal pad) through the insulating layer 910. The first metal pad 902 may be connected to the metal fill 900 by at least one via 912 formed through the interlayer dielectric 914. This structure 902 may include more metal layers above the metal under test (MUT) and may include more redundant vias between the metal layers. During electron beam inspection, the probe is scanned along a row of metal fills 900. If a path to the substrate is established without defects, the metal fill 900 will emit secondary electrons, suggesting that the vias and contacts are not open. If any of them is open, the metal filling will remain dark.
[0143]
After the initial design of the test chip, it may be determined whether a dummy fill is required in the empty space to prevent defects caused by CMP polishing. Current technology often makes this determination using commercially available software tools. This determination is made based on the size and configuration of the free space. Once this determination is made, according to the present invention, the dummy fill can be processed as contacts that can be tested in the same manner as the contacts of the contact array described above. Thus, the empty space is used to test the test chip. Furthermore, this method can be used for free space in VLSI products.
[0144]
26A-26C show a process for using a dummy shape for the purpose of testing for defects. FIG. 26A shows a product chip 900 that includes an empty space 901. FIG. 26B shows a typical dummy shape 902 pattern used to fill the empty space of the product chip. FIG. 26C shows that a contact 904 has been added to a portion of the dummy shape 903 to allow voltage contrast testing (other dummy shapes are allowed to float). Such available dummy shapes can be provided on both dedicated test chips and product chips (for in-line voltage contrast testing).
[0145]
L. Defect location and characterization
As mentioned above, once a defect is detected by the voltage contrast technique, it will be important to determine and characterize the position of the defect. If the scan swath scan is in the x direction, it will be necessary to inspect the test structure in the y direction. For example, with respect to the exemplary test chip described above, the conductive lines are tested for defects based on an analysis of the primary scan area scan. As described above, these defects may exist outside the scan swath (ie, the primary scan area). In other words, the primary scan area is first scanned to determine whether the test structure contains one or more defects. A test in the y direction is then performed to locate and characterize the defect.
[0146]
The defect is preferably located after the x-direction scan is finished. That is, all conductive line stubs are scanned to determine if the conductive line is defective. Next, the position of each defect stub and the corresponding conductive line is recorded. Once all stubs have been scanned, each conductive line is then scanned in the y direction in an efficient pattern. For example, if the stub is scanned from left to right in the x direction, each conductive line is then scanned in the y direction starting from the leftmost line. In short, by scanning the test structure along the entire x direction (prior to locating individual defects), the number of defects in the test structure can be quickly evaluated. If necessary, individual defects may then be located and characterized as described above.
[0147]
Of course, any other suitable scan pattern may be implemented. For example, if it is found during a scan in the x direction that a conductive line is defective, the scan in the x direction is interrupted and the defect is located immediately along the conductive line in the y direction. Scanning in the x direction may resume after the defect is located. However, this scan pattern is not as efficient as a scan pattern in which scanning in the x direction is completed before the defect location is specified.
[0148]
Thus, once the defect structure on the die is re-located and identified, it will be necessary to identify the exact location and cause of the defect. In certain embodiments, this can be done using an analysis tool. FIG. 25 shows the basic configuration of an analysis tool 950 for analyzing a test die for defects that includes a test structure. The analysis system preferably comprises a dual beam analysis tool comprising both a focused ion beam (FIB) portion 951 and an electron beam (SEM) portion 952. The analysis tool 950 is connected to the system 10 of FIG. 1 and is an integral part of that system.
[0149]
Ten systems provide recorded placement data for test circuit defect structures and defect types such as open or short defects. The analysis tool 950 used in certain embodiments of the present invention can provide two different types of scanning actions by scanning a location containing a defect with either a focused ion beam (FIB) or an electron beam. . A focused ion beam may be used to eliminate the need to remove the entire layer in certain cases by locally ablating or removing material from the location containing the defect to locally expose the underlying material. it can. The electron beam can be used for chemical analysis using energy dispersive X-ray (EDX) analysis and for imaging the area under analysis.
[0150]
As shown in FIG. 25, an exemplary FIB section generally includes a liquid metal ion source 954 for generating a Ga ion beam 956 using gallium (Ga). The lens system 958 focuses the ion beam to a spot size on the wafer test die located above the stage 959. A set of scanning coils 960 is located near the lens system 958. By applying a voltage to the scanning coil 960, the ion beam 956 can scan the test die. The ion beam control unit 962 controls the output of the ion source, the focus of the lens system, and the operation of the scanning coil. During material removal, the controller 962 controls the scanning of the target surface with the focused beam with respect to scan area, scan frequency, and scan time.
[0151]
The focused ion beam is focused and scanned as described above to irradiate selected portions of the defect structure. The acceleration voltage of the ion beam 956 can range from 10 to 30 kev. The current of the focused ion beam 52 can be set between 10 pA and 1000 pA.
[0152]
The scanning electron beam unit 952 irradiates the die near the beam 52 with the electron beam 964. The electron beam control unit 966 controls the acceleration voltage, current level, and beam diameter of the electron beam 964. The electron beam 964 is used not only for EDX chemical analysis but also for imaging such as secondary and / or backscattered electron imaging. The electron beam 964 may further irradiate a region of interest on the die when the region is illuminated with a focused ion beam.
[0153]
As described above, the wafer under inspection is attached to the stage 959, and the stage is related to the stage controller 968 for moving the wafer stage 959 in the x, y, and z directions. The detection unit 970 may be disposed at a position suitable for detecting various signals generated on the surface of the wafer in response to irradiation with the focused ion beam or the electron beam. Although simplified in FIG. 25, the detector 970 is understood to represent various detectors such as secondary electrons, backscattered electrons, X-rays or mass spectrometers. The signal from the detection unit 970 is amplified and then input to the FIB / SEM computer. The ion beam control unit 962, the stage control unit 968, and the electron beam control unit 966 are connected to a FIB / SEM computer system connected to the system 10.
[0154]
When the location of the defect is re-located and characterized, a chemical analysis known as EDX (energy dispersive x-ray) is performed at that location. The EDX analysis is performed by using the electron beam unit 952 to focus the electron beam on the defect structure. The interaction between the beam electrons and the material atoms produces an X-ray spectrum that indicates the chemical properties of the focused location. Once the X-ray spectrum from the material is determined, it is possible to qualitatively identify most of the elements present at that location, and thereby determine the cause of the defect. For example, if no tungsten is present at that location, the EDX spectrum cannot show tungsten at that location. At this stage, once the cause of the defect is determined and confirmed, the process ends and a new test die can be tested. If the initial inspection did not reveal the cause of the defect, the FIB is used to remove the layer or generate a cross-section using a focused ion beam to reveal the cross-sectional structure of the region of interest. be able to.
[0155]
After FIB stripping has been performed, the position is again examined using scanning electron beam imaging and / or another EDX analysis to determine again whether the cause of the defect can be confirmed. This process is repeated until the cause of the defect is confirmed. This process allows the wafer manufacturing process to be modified to improve wafer yield as soon as the cause of the defect in the test structure is discovered, enabling rapid correction operations in real time in the manufacturing environment. You will see that it can be done.
[0156]
With respect to the position of the detected defect, additional techniques for locating the defect can be used. The technique involves pre-scanning the wafer under test with a dose designed to charge only a portion of the structure. The short line will be more fully charged to the equilibrium potential because of its lower capacitance. Therefore, the potential of the floating line changes approximately linearly with respect to the length of the line. It takes longer to charge long lines. The line can then be scanned.
[0157]
Thus, for example, line defects can be recognized using the following technique.
1. When the line is grounded, the signal level from the end of the line is an intermediate level (about 50% of the maximum value).
2. If the line is full length and floating, the signal level is about 75% of the maximum value.
3. If the line is incomplete length and is floating, the signal level approaches 100% as the length of the line gradually decreases.
[0158]
By calibrating the signal level against the position, we can guess the position of the end of the line and use that information to quickly move the wafer so that the defect enters the field of view to image the defect for classification Can be made. Alternatively, each defective line may be scanned in array mode to locate the defect. In general, a first field of view selected from a first portion of a line is compared to a second field of view selected from an adjacent second portion. In one embodiment, the first field of view is subtracted from the second field of view. The result of the subtraction is directly related to whether the defect is located in the first or second field of view. Thus, the position of the defect may be determined based on the result of such subtraction.
[0159]
M.M. Use of voltage contrast testing in the production of product chips.
Techniques and various test structures for voltage contrast testing are not only effective for test chips, but can also be used for product chips. FIG. 27 shows such a product chip 1000. Product chip 1000 has a product circuit portion 1001 (including circuitry necessary to perform the functions of the product chip) and a scanning swath 1002 located at one end of the chip. Such scanning swaths are preferably located at the end of the product chip, but such positions are not required to practice the present invention.
[0160]
The scanning swath on the product chip can comprise any combination of the above types of test structures. In fact, the exact combination of test structures may be determined by the specific circuit of the product chip. The exact combination may also be based on the specific concerns of the manufacturing plant. In any case, the scanning swath can be tested at one or more points in the manufacturing process. Further, during the manufacturing process, new test structures can be added to the scan swath at any point in the manufacturing process for testing.
[0161]
FIG. 28 is a cross-sectional view of a vertical tap 1004 (or stacked plug) for testing. The vertical tap shown in the figure is included in the scan swath of the illustrated product chip 1000. A product chip substrate 1003 is shown. As shown, a vertical tap or stack plug 1004 can be used to monitor the buried layer M1. Such vertical taps are just one type of test element that can be processed (if desired) within a scanning swath.
[0162]
FIG. 29 shows a test structure that can be included in scan swath 1002. A contact array 1006 and conductive lines are provided, and with respect to the conductive lines, grounded conductive lines 1005 and floating conductive lines 1007 are alternately arranged. All of these structures can be tested using conventional voltage contrast techniques as well as the novel techniques described herein. In a particular embodiment, a scanning device comprising a continuously moving stage of the type described above is used to scan the test structure shown in FIG. Although the preferred direction of continuous movement is indicated by arrow 1008, continuous movement may be performed in other directions. However, to test only a narrow part of a product chip, the conductive line is approximately the same as the conductive line rather than nearly perpendicular to the conductive line (as in a dedicated test chip where space is not a significant concern). It is preferably scanned by a parallel continuous movement.
[0163]
When the scan swath of the product chip is inspected at the inspection station using voltage contrast technology, the total number of defects can be calculated. For example, the number of open / shorts can be quickly quantified when the sample stage is continuously moved in the first direction through the primary scan region to detect shorts. An algorithm can then be used to infer the expected impact on product die yield. This may be used to generate defect management limits for each defect type in the layer. For example, if there is an “n1” open in an open test structure that has a critical area “A1” versus open / short per die, the predicted defect level of the product die is (n1) × (A1 / A2) Given by. Where A2 is the critical area of the product die for a given process layer open / short. The critical area of a given process layer is defined as the total area of the pattern that will be a defective element for a given type of defect in its critical dimension.
[0164]
Once this control is established, if the defect level measured in the next lot through a scan swath scan of the next product chip exceeds the control limit, the manufacturer will tend to be unable to manage the manufacturing process. To know. In addition, the manufacturer obtains direct feedback from the scan swath scan as to which defect mechanism is causing the problem. The scanning swath test structure directly provides a classification of defects by the position and signature of the defects in a given test structure so that the manufacturer can quickly investigate and resolve the problem.
[0165]
N. Using voltage contrast testing to optimize other test equipment
The voltage control test apparatus, configurations and techniques described above can also be used to optimize other inspection systems used in the manufacturing process. Examples of such a test system include AIT II (patterned wafer inspection system) and KLA-2138 (ultra-wideband wafer inspection system) of KLA-Tencor products. Such a system detects many defects in the semiconductor chip. However, some of these detected defects may not be important in that they do not affect chip performance or operation. On the other hand, the voltage contrast test detects only essential defects (so-called “fatal defects”). Thus, the voltage contrast techniques and structures described above allow other systems to maximize detection of “fatal defects” and / or minimize the detection of “nuisance defects”. It can be used to optimize such a test system to suppress.
[0166]
Such optimization includes performing the following actions:
1. In order to detect serious defects, the test chip or test part of the product chip is inspected by the SEM inspection apparatus.
2. Defective test structure to locate defects and classify defects based on type (eg, “open”, “short” or “via open”) and generate a wafer map of critical defects by type Is further scanned.
3. The same test chip or test part of the product chip is inspected by the inspection tool to be optimized.
4). Preferably, step 3 is repeated several times for inspection tools set to different configurations.
5. A defect map is generated based on the inspection using the inspection tool to be optimized.
6). Each of the various defect maps is overlaid on the wafer map generated by the voltage contrast test, which inspection tool configuration maximizes the detection of critical defects and minimizes the detection of non-critical defects Analyze to determine whether to suppress.
7). Set the detection tool to the optimal configuration.
The inspection tool may generate the defect map from a layer different from the layer from which the voltage contrast defect map was generated. The above-described procedure may be used for periodic calibration of the inspection tool and extraction inspection.
[0167]
This process is automated using standard automatic nuisance filter technology, specifying "fatal" defects as real, other defects as nuances, automatic segmented auto threshold and real-time classification algorithms Makes it possible to configure the tool to maximize the detection of “fatal” defects and to minimize the detection of nuisance defects. For example, inventor Bakker et al. U.S. Provisional Patent Application No. 60 / 167,955, filed Nov. 29, 1999, "POWER ASSISTED AUTOMATIC SUPERVISED CLASSIFIER CREATION TOOL FOR SEMICONDUCTOR DEVICES". This is incorporated herein by reference.
[0168]
An example of a system that can be used to automate this process is KLA-Tencor's product Klarity. Klarity is KLA-Tencor's automatic defect data analysis means. Thereby, semiconductor manufacturing facilities can automate the analysis of defect data generated by inspection, classification and re-inspection tools. This yield analysis module allows a user to substantially automate complex engineering procedures using simple flow charts and send expert engineering knowledge and defect analysis routines to factory operators. Such automation allows a user to quickly analyze a large amount of defect data and helps reduce the defect data set to represent only the most critical yield failures.
[0169]
The voltage contrast techniques, structures and devices described above can also be used with defect classification methods. For example, voltage contrast techniques and the like can be used with the methods and apparatus described in the US provisional application referenced above and incorporated herein. In one embodiment, electrical (ie, voltage contrast) data and optical data are sorted and grouped by defect type. The electrically acquired defect information may then be used to characterize the optical image (eg, sort into fatal and non-fatal defects) during the optical inspection setup phase. Further, the wafer map generated as a result of the inventive voltage contrast technique described above can be studied and analyzed to find systematic defects. For example, if a wafer map of several test chips indicates that the frequency of defects is high in a particular area of the tested chip, it indicates that there is a systematic problem at that particular location.
[0170]
The wafer defect map generated from the voltage contrast measurement may be used for other inspection or re-inspection tools. For example, a defect map is generated with a first inspection tool, and then the defect map is used to locate the defect with a second inspection or re-inspection tool. For example, a focused ion beam tool may be used to expose and observe defects as described above. In short, the defect map can be used to determine the position of the defect after the sample is removed from the voltage contrast tool.
[0171]
In addition, certain patterns may appear in a wafer map that identifies certain defective (or non-standard) manufacturing processes. That is, a specific physical arrangement of defects on the sample can indicate the type of defect. An example of a defect that forms an edge-type pattern is shown in FIG. Certain types of processing processes typically have a specific defect footprint. For example, defects placed in a radial pattern from the center of the chip may indicate a problem with an apparatus that spins a particular layer above the wafer. The defect shown in FIG. 34 may have arisen from an etching process in an etching tool with a gas inlet port on one side of the wafer and a gas exhaust port on the opposite side of the wafer. As such, a particular arrangement of defects can then be compared and matched to a particular device footprint and corresponding process steps. In addition, defect data maps from several wafers across several lots can be stored in a database and signature analysis can be performed across a huge data set. This makes it possible to detect low level signatures in data suggesting systematic process yield problems. A processor may be used to efficiently compare the detection data map with the signature pattern. Of course, the user may manually compare the map with the signature. As another example, voltage contrast data may be used with optical data to determine the manufacturing process and to inspect to maximize the detection of fatal defects.
[0172]
Electrical defect data from voltage contrast inspection may be associated with other types of data obtained at various steps in the manufacturing process. For example, electrical defect data and corresponding optical images may be generated from the test structure after the etching process step. Each electrical defect is then characterized and associated with one or more optical images. Process information (eg, process step identities and processing device operating parameters) may be associated with each associated pair of electrical defect and optical image. The progress of the defect may then be tracked through a corresponding optical image of the defect. For example, defects that appear after a particular process can be attributed to such a process. The process can then be adjusted (eg, adjusting operating conditions). In addition, when a particular defect type is associated with a particular optical image, any subsequent optical image characterized as being identical to the previous optical image will have the same defect as the previous optical image. Can be recognized.
[0173]
O. Other test structures
The test structure described above is exemplary only and is not intended to limit the scope of the invention. For example, any test structure suitable for realizing an efficient inspection mechanism may be used. For example, the test structure may only have lines that are straight and uniform in width. This configuration is in contrast to the alternative island and conductive line test structure shown in FIGS. 5 and 6A. FIG. 30 shows such a product chip 1100. The test structure 1100 includes floating conductive lines 1104 and ground conductive lines 1102 that are interleaved. In this embodiment, the line is substantially straight. One end (1105) of the conductive line 1102 is grounded, and the other end of both the conductive lines 1102 and 1104 protrudes into the scanning region 1101. Lines protruding into the scan area may have different lengths to distinguish between two sets of conductive lines (ie, 1104 and 1102). Of course, the two sets of lines 1102 and 1104 may have the same length.
[0174]
As described above, an open in the conductive line 1102 can be detected by performing a voltage contrast on the conductive line end in the scan region 1101. Similarly, an open between a conductive line 1104 and a conductive line 1102 adjacent to it can be detected by performing a voltage contrast with respect to the conductive line end 1104 in the scan region 1101. Furthermore, the stacked plug described above with reference to FIGS. 8 to 13 may be used with the structure of FIG. As described above, the stacked plug may be used to monitor a buried conductive layer (eg, regarding opening).
[0175]
A test structure partially disposed within the scan region 1101 may be used to measure other characteristics in addition to shorts and opens. For example, the test structure may be used to measure various process parameters such as CMP parameters. FIG. 31 shows a CMP test structure 1112 used to measure the CMP line width. As shown, a path metal layer is used to connect conductive lines 1106 formed by a CMP process to four probe pads (not shown). Specifically, the first path strip 1110a and the second path strip 1110b are used to pass current through the end of the conductive strip 1106 and out through the opposite end of the conductive strip. That is, the current source is connected between two probe pads that are connected to the conductive strip 1106 via the first and second path strips 1110. The third and fourth strips are then used to measure the voltage difference between each end of the conductive line 1106. Next, the resistance value of the conductive wire 1106 may be calculated based on the measured voltage difference and current value. The width of the conductive line 1106 can then be derived from the resistance value to determine the degree of corrosion and / or dishing that occurred on the conductive line 1106 during the CMP process.
[0176]
The probe pad may be connected to any of the test structures described above as well as the CMP test structure of FIG. These probe pads can then be used to measure parameter data relating to the test structure. The parameter data may be used with voltage contrast defect data to determine various characteristics related to the test structure. For example, if a particular conductive line of the test structure is shorted with an adjacent grounded line, that line may be inspected to determine the leakage current value. In addition, various interference tests may be performed through the probe pad.
[0177]
FIG. 32 shows a serpentine test structure 1200 that can be used to measure the resistance of a line. As shown, the test structure 1200 includes a plurality of first scanning elements 1202 and a second plurality of second scanning elements 1204. Each of the first scanning elements is formed from a stacked plug connected to the M1 layer 1210. M1 layer 1210 forms a serpentine pattern connected to ground through via 1212. Each of the second scanning elements 1204 is formed from an M3 conductive line connected to an M2 conductive line. The second scanning element 1204 is floating.
[0178]
When voltage contrast is performed on the first scanning element 1202, each of the first scanning elements 1202 has different line lengths relative to the grounded via 1212 and may therefore have different brightness. Expected. For example, the first scanning element 1202c is expected to have a brightness level of 100% because it is directly grounded. The first scanning elements 1202b, 1202d located on either side of element 1202c are expected to have 50% brightness, and the first elements 1202e, 1202a are expected to have 25% brightness. . Since the brightness level is also related to the line width, the brightness level measured for each of the first scanning elements 1202 is used to calculate the line width bias and / or the line resistance. It may be used.
[0179]
When performing voltage contrast on the second scanning element 1204, a short circuit between M2 and M1 can be monitored. That is, since the second scanning element is expected to be electrically isolated from the underlying M1 layer 1210, the second scanning element is expected to appear dark. If the second scanning element is bright under voltage contrast, a short circuit has occurred between the second scanning element 1204 and the underlying M1 layer 1210.
[0180]
The test structure described above is arranged to facilitate voltage contrast measurements during successive scans through the primary scan region (as described above). That is, voltage contrast readings are obtained from a plurality of conductive lines as the electron beam moves continuously across the ends of the conductive lines. In other embodiments, a test structure may be used that facilitates acquiring voltage contrast data with a stepped transfer technique. For example, a stepped test structure may be used with a stepped SEM such as KLA-Tencor 8100 or eV300, Schlumberger, AMAT SEMvision, or Hitachi CD tool.
[0181]
FIG. 33 shows a test structure 1201 suitable for step-type technology. Since the voltage contrast measurement is performed simultaneously on one group of test structures, the test structure is prepared to enter the voltage contrast group. In this way, a first voltage contrast measurement can be performed on the first group, then on the second group, and so on. As shown in the figure, the test structure 1201 includes a primary scanning region 1201 and two secondary scanning regions 1203 and 1205. Primary scan region 1201 comprises a plurality of test fields (eg, 1207a and 1207b) arranged in an array across primary scan region 1201. The ends of the plurality of conductive lines end in each test field 1207. The first portion of the conductive line extends into the secondary scanning region 1203 and the second portion extends into the secondary scanning region 1205.
[0182]
Each test field 1207 is sized so that it can easily raster scan almost the entire test field without moving the sample stage. For example, the test field is sized such that a relatively clear image of the end of a line ending in test field 1207 is generated from a raster scan of the field area. The size of the field region is determined by specific conditions of the step type SEM. The test fields are preferably arranged at substantially equal intervals so that the distance of the steps from one field to the next is the same. The test structure may be arranged in any suitable pattern, such as a two-dimensional array or checkboard pattern.
[0183]
The secondary scan area may include any suitable type of test structure. As shown in the figure, the secondary scanning region 1205 is arranged for the detection of interconnect defects (eg, open and short) as described above. On the other hand, the secondary scanning region 1203 is arranged for detecting a via defect as described above. In the illustrated embodiment, the secondary scan regions 1203, 1205 include alternating floating and ground conductive lines. The first end of each conductive line extends into the secondary scan region and the second end extends into the test field 1207. Further, the first end of the ground conductive line is grounded. During voltage contrast inspection in test field 1207, the second end of the ground conductor is expected to have a different brightness than the second end of the floating conductor. For example, the end of a grounded line appears bright and the end of a floating line appears dark. If one of the ground conductive lines has an open defect, the defective line appears to be as bright (eg, dark) as the adjacent floating conductive line. If there is a short between one of the floating conductors and the ground conductor, the shorted floating conductor appears to be as bright (eg, bright) as the ground conductor. In general, if a particular line is defective, the scanned second end of that line appears to have an unexpected brightness level. Then, the position of the defect may be specified by stepping down a specific defective conductive line.
[0184]
A stepped test structure (eg, FIG. 33) determines if there is a defect in the test structure by scanning only a portion of the test structure, and then scans the rest of the test structure. May be scanned in any suitable manner that facilitates determining the specific location of the defect. For example, the following inspection procedure may be used:
1. The wafer is pre-arranged to facilitate the arrangement of groups of conductive lines.
2. By moving the wafer stage, the ends of the conductive lines are first placed under the SEM column.
3. To obtain voltage contrast data, the first group is scanned with an electron beam.
4). A list of defect data and associated stubs (ends of conductive lines) are stored.
5. Repeat steps 1-4 for the second group of ends of the conductive lines.
The pre-placement is performed in any suitable way so that the SEM can automatically advance to each group of conductive wire ends (hereinafter referred to as a field). For example, the step size is entered to ensure that the correct steps are taken to reach from one field to another. The stage is then automatically advanced from field to field.
[0185]
A list of defects for each field may be recorded. Then, based on the recorded list, defects can be located within each group of conductive lines associated with each defect field. For example, the stage is moved so that the SEM column is stepped along the longitudinal axis of the defective conductive line. Alternatively, the defective field under test may be placed before moving to the next field. In this embodiment, a list of defects and their associated stubs may be recorded for each field. Further, specific defect positions may be recorded for each field.
[0186]
Defects in the defective line may be detected in any suitable way. In one embodiment, the portion of the defect line located closest to the field outside the field is placed under the SEM column. Next, voltage contrast data is acquired for this portion, for example, to determine whether there is a transition from light to dark within the defect line. The brightly transferred position is related to the position of the defect. If there is no transition in this part, the next part adjacent to the previously scanned part of the defect line is placed under the SEM column.
[0187]
Alternatively, any suitable search algorithm may be used to place the defective line portion under the SEM column. In the binary search example, the intermediate portion between the ends of the defect line is first placed under the column. If there is no transition to light, it is determined whether the defect is in the first half of the line closest to the field or the other half of the line. For example, if a line is expected to be grounded at the end furthest from the field and the middle portion of the line appears dark, the defect is probably located at half of the line farthest from the test field . The search continues for half of the currently searched portion until a defect is found (eg, a quarter of the line is searched next). The binary defect search mechanism may be implemented with any other test structure described herein (eg, the structure of FIGS. 6A-6C or 33).
[0188]
As described above, the position of the defect may be approximated based on the brightness level of the edge being scanned. The wafer to be tested is pre-scanned with a dose selected to charge only a portion of the structure. The short line will be more fully charged to the equilibrium potential because of its lower capacitance. Therefore, the potential of the floating line changes approximately linearly with respect to the length of the line. It takes longer to charge long lines. For example, the length of a floating conductive line having an open defect can be determined from the amount of charge or brightness level at the scanned end.
[0189]
Shorts between adjacent lines may be discovered earlier when scanning between lines than scanning over one conductive line. For example, a non-raster electron beam can be used, for example, to scan between two adjacent shorted conductive lines in a single line scan. The spot size of the electron beam is preferably a radius smaller than the distance between two adjacent lines. When the electron beam scans between lines, a large change in the intensity level of the scan area (eg, the scan area changes from light to dark or from dark to light) Suggest a short position.
[0190]
Each of the test structures described above may include a guard ring or one or more conductive structures to control the electric field of the conductive lines to improve defect detection capabilities. Otherwise, a conductive structure that is not adjacent to another conductive line (eg, an edge line in a test structure, or a stub longer than an adjacent stub) is more than a conductive line adjacent to another conductive line ( May appear bright (due to large edge effects). In general, one or more conductive portions that are not tested are used to control the electric field within the one or more conductive portions that are tested. In one embodiment, a conductive “guard” structure is positioned adjacent to a particular conductive portion in the test structure that is not positioned adjacent to other conductive portions of the test structure. The guard structure may be charged to a predetermined potential (for example, ground potential) or may be floating. Each guard structure preferably has a different potential from the adjacent conductive lines of the test structure. For example, the floating guard structure is disposed adjacent to the ground conductive line of the test structure.
[0191]
FIG. 35 is a schematic diagram of the test structure 1200 of FIG. 32 with the addition of a conductive guard ring 3502. Guard ring 3502 surrounds test structure 1200 such that a portion of the guard ring is adjacent to the outer portion of the test structure. In the embodiment shown, the guard ring is adjacent to the outer conductive portions 3504a, 3504b. Guard ring 3502 includes a finger portion (eg, 3506) adjacent to a portion of the test structure that does not extend to the full length of another adjacent structure (eg, stubs 3508a, 3508b). Similar guard ring structures may be used with other test structures described herein (eg, the structures of FIGS. 6A-6C or 33).
[0192]
In another embodiment, a strip may be placed below the center of the primary scan area to facilitate random mode positioning. If the shape of the scanning area is very repetitive and small, image aliasing increases and positioning becomes difficult. Accordingly, one or more large and unique shapes may be placed in the scan region in the x and y directions for use in positioning in the x and y directions.
[0193]
While the invention has been described in detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made without departing from the scope of the appended claims. It should be noted here that there are many other ways to implement the process and apparatus according to the present invention. For example, to establish voltage contrast balance across the wafer test structure, a large area of the wafer (eg, 10 mm) is precharged with a flood gun prior to performing a scan of the primary scan area (eg, 300 μm). May be. As a result, the inspection time of the primary scanning area of the test structure will be significantly reduced. In still other embodiments, the test structure of the present invention may be used in any suitable critical dimension measurement tool. That is, the test structure may be formed with a structure having a critical dimension (eg, minimum line width or space between lines).
[0194]
Any other suitable charge control mechanism may be used to inspect the test structure described above. Several mechanisms for controlling charging are described in co-pending US patent applications 09 / 579,867, 09 / 502,554, 09 / 394,133, and US Pat. No. 6,066,849. ing. The entirety of these applications and patents are incorporated herein by reference. Further, any suitable charged particle beam (eg, electron beam) inspection system and / or method may be used to inspect the test structure described above and to perform the inspection method described above (eg, electron Beam systems and / or methods are described in US patent applications 09 / 579,867, 09 / 502,554, 09 / 394,133, and US Pat. No. 6,066,849). Although the test structure embodiments have been described in a configuration that is inspected with an electron beam system, of course, other types of systems may be used. For example, a photon emission system (constant or pulsed beam) may be suitable for charging selected portions of the test structure for voltage contrast analysis. Other systems may be used with the electron beam system (eg, away from the row) or instead of the electron beam system.
[0195]
The mechanism of the present invention may be implemented for any suitable application in addition to semiconductor chip manufacturing. For example, other applications are data disks, gallium arsenide semiconductor devices, multichip modules, and the like. In general, embodiments of the present invention are applicable to any suitable technique for manufacturing electronic devices or other types having delicate patterns. Further, techniques for defect characterization and / or creation of defect x and y maps may be used across the wafer to facilitate the detection of systematic process problems. In other words, defects may be mapped across the wafer. If a particular area of the wafer is found to have significantly more defects than other areas, it may be determined that the process is not working properly for such areas. The process can then be adjusted to reduce subsequent defects in that particular area of the wafer. Further, the test structure described above may be formed on any suitable portion of the wafer, such as in a scribe line or on any portion of one or more dies.
[0196]
Therefore, the embodiment taken up above is for the purpose of illustration, and does not limit the contents of the present invention. Thus, the invention is not limited to the details specified herein, but can be varied within the scope of the appended claims and the equivalents.
[Brief description of the drawings]
FIG. 1 is a block diagram of an SEM inspection system according to one embodiment of the present invention.
FIG. 2 is a diagram showing a typical scanning pattern of the present invention.
FIG. 3 is a flowchart showing an inspection procedure according to an embodiment of the present invention.
FIG. 4A illustrates a semiconductor wafer with a die array prepared in accordance with the principles of the present invention.
FIG. 4B illustrates a semiconductor wafer with a die array prepared according to the principles of the present invention.
FIG. 4C shows a test die fabricated according to the principles of the present invention.
FIG. 4D illustrates a test die fabricated according to the principles of the present invention.
FIG. 5 is a plan view illustrating a portion of the test die of FIGS. 4c and 4d.
6A is a plan view of a portion of a test structure. FIG.
FIG. 6B is a cross-sectional view of a portion of the test structure.
FIG. 6C is a side view of a portion of the test structure.
7A shows a portion of a test structure having M2 interconnect wiring and island elements on top. FIG.
FIG. 7B illustrates a portion of a test structure having M2 interconnect wiring and island elements on top.
FIG. 8 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 9 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 10 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 11 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 12 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 13 shows a test structure designed to test the integrity of a covered metal layer.
FIG. 14A illustrates a portion of a test structure comprising an array of via chains.
FIG. 14B illustrates a portion of a test structure comprising an array of via chains.
FIG. 14C illustrates a portion of a test structure comprising an array of via chains.
FIG. 15A illustrates an array of isolated contact test structures.
FIG. 15B illustrates an array of isolated contact test structures.
FIG. 16A is a diagram showing a CMP pitch test pattern.
FIG. 16B is a diagram showing a CMP pitch test pattern.
FIG. 16C is a diagram showing a CMP pitch test pattern.
FIG. 17 is a diagram showing a CMP density test pattern.
FIG. 18 shows a further CMP density test pattern.
FIG. 19 is a diagram showing a CMP horizontal aspect ratio test pattern.
FIG. 20 is a view showing a cross section of a CMP aspect ratio test pattern.
FIG. 21 is a cross-sectional view of a CMP aspect ratio test pattern.
FIG. 22A is a plan view showing a test structure used for observing a problem of misalignment.
FIG. 22B is a plan view showing a test structure used for observing a problem of misalignment.
22C shows a cross section of the test structure of FIGS. 22a and 22b. FIG.
FIG. 23A shows an array of test structures used to observe y-direction misalignment and the amount of misalignment.
FIG. 23B shows an array of test structures used to observe x-direction misalignment and amount of misalignment.
FIG. 24A illustrates a multi-layer test structure fabricated from a metal fill to add vias and / or contacts to monitor the integrity of the CMP process.
FIG. 24B illustrates a multilayer test structure fabricated from a metal fill to add vias and / or contacts to monitor the integrity of the CMP process.
FIG. 25 is a schematic diagram of an analysis tool for analyzing a defect test die including a test structure.
FIG. 26A shows a process for using a dummy shape for the purpose of testing for defects.
FIG. 26B shows a process for using a dummy shape for the purpose of testing for defects.
FIG. 26C shows a process for using a dummy shape for the purpose of testing for defects.
FIG. 27 shows a product chip.
FIG. 28 is a cross-sectional view of a vertical tap for testing.
FIG. 29 illustrates a test structure that can be provided for scanning swaths.
FIG. 30 shows a test structure having a plurality of straight and uniform width lines.
FIG. 31 is a diagram showing a CMP test structure for measuring the line width of CMP.
FIG. 32 shows a meandering test structure that can be used to measure the resistance of a line.
FIG. 33 is a diagram showing a test structure suitable for a step type technique.
FIG. 34 is a diagram illustrating a defect forming an edge type pattern.
35 is a schematic view of the test structure of FIG. 32 with the addition of a conductive guard ring.
[Explanation of symbols]
10 ... Inspection system
20 ... electron beam train
21 ... Positioning computer
22: Optical positioning system
23 ... Data bus
24 ... xy stage
26 ... Stage servo
28 ... Interferometer
29 ... Bus
30. Analog deflection circuit
31 ... Bus
32 ... Detector
34 ... Handler
36 ... System computer
38 ... Computer display
40 ... User keyboard
42. Beam train control computer
44 ... Video frame buffer
46 ... Image display
48 ... Preprocessor for acquisition
50: Deflection controller
52 ... Memory block
54 ... Database adapter
56 ... Defect inspection processor
57 ... Sample
58 ... post processor
100 ... Test chip
101 ... Scanning swath
102: Scanning pattern
200: Semiconductor wafer
202 ... Die array
204 ... Test die
204A ... first edge
204B ... Second edge
204C ... Third edge
204D ... Fourth edge
206 ... Product die
206 ... 1st part
206A ... proximal edge
206B ... Distal edge
207A ... first edge
207B ... second edge
208 ... second part
208A ... proximal edge
208B ... Distal edge
209A ... first edge
209B ... second edge
210 ... middle part
210A ... first edge
210B ... second edge
212 ... 1st division
212A ... first module
212B ... second module
212C ... Third module
212D ... fourth module
212E ... fifth module
214 ... 2nd division
214A ... first module
214B ... second module
216 ... Third division
216A ... first module
216B ... second module
216C ... Third module
216D ... fourth module
216E ... fifth module
218 ... Fourth division
218A ... first module
218B ... second module
220 ... Fifth section
220A ... first module
220B ... second module
220C ... Third module
220D ... fourth module
220E ... fifth module
222 ... Sixth section
222A ... first module
222B ... second module
350 ... CMP density test pattern
351, 352, 353, 354 ...
380 ... density pitch pattern
381 ... Metal wire
382 ... Contact
400 ... Part of the test die
402: First test structure
404 ... second test structure
406 ... Third test structure
408 ... first conductor, first connector, interconnection line
409 ... 2nd conductor, 2nd connector, island member
410 ... proximal stub end
412 ... Distal end
420 ... Board
421 ... Insulating layer
422 ... Dielectric layer
424 ... Contact
430 ... M2 interconnection wiring
432 ... Island element
433 ... interlayer dielectric layer
434 ... via
436 ... opening
438 ... Distal portion, first scanning element
440 ... M3 interconnect
442 ... first scanning element
444 ... Interlayer dielectric
446 ... via
448 ... second scanning element
450 ... cutting part
452 ... First scanning element, stack plug
454 ... second scanning element
456 ... M4 interconnect
500 ... first via chain
501: Second via chain
502 ... Proximal end
504 ... Distal end
506 ... Substrate
508 ... M1 interconnection line
510 ... Oxide layer
512 ... Contact
514 ... via
516: Interlayer dielectric
518 ... M2 interconnect
520 ... first row
522 ... second row
524 ... Third row
600 ... Array
602 ... Insulated contact test structure
604 ... Board
606 ... Insulating layer
608 ... M1 layer part, M1 pad
610 ... Contact
612 ... Interlayer dielectric
614 ... M2 layer part, M2 pad
616 ... via
700 ... CMP pitch test pattern
702 ... Test element
704 ... Line width
704 ... Substrate
706 ... Space
708 ... Insulating layer
710 ... Contact
720, 740 ... aspect ratio test pattern
742 ... Metal wire
743, 744 ... Metal wire pair
750 ... Aspect ratio test pattern
752 ... Contact
800a, 800b, 800c, 800d, 800e, 800f ... overlay test structure
802c, 802f ... M2 metal strip
804a, 804b, 804d, 804e ... M1 metal strip
806a ... Contact
806b ... M2 via
806c ... via
806d ... Contact
806e ... M2 via
806f ... via
810e, 810g, 810i ... test structure
811, 813 ... contact
900 ... Metal filling
900 ... Product chip
901: Empty space
902 ... Test structure
902, 903 ... dummy shape
904 ... Contact
906 ... Substrate
908 ... part of first metal layer, first metal pad
910 ... Insulating layer
912 ... via
914 ... Interlayer dielectric
950 ... Analysis tool
951 ... Focused ion beam section
952 ... Electron beam section
954 ... Liquid metal ion source
956 ... Ga ion beam
958 ... Lens system
959 ... stage
960 ... Scanning coil
962 ... Ion beam control unit
964 ... Electron beam
966 ... Electron beam control unit
968 ... Stage control unit
970 ... detection unit
1000 ... Product chip
1001 ... Product circuit part
1002 ... Scanning swath
1003 ... Substrate
1004 ... Vertical tap
1005 ... Ground conductive wire
1006 ... Contact array
1007 ... Floating conductive wire
1008 ... Direction of stage movement
1100 ... Product chip
1101 Scanning area
1102 ... Ground conductive wire
1104: Floating conductive wire
1105: Conductive wire end
1106: Conductive wire
1110 ... Path strip
1112: CMP test structure
1200 ... test structure
1201 ... Test structure
1201 ... Primary scanning area
1202 ... First scanning element
1203 ... Secondary scanning area
1204 ... Second scanning element
1205 ... Secondary scanning area
1207 ... Test field
1210 ... M1 layer
1212 ... via
3502 ... Conductive guard ring
3504a, 3504b ... conductive portion
3506 ... Finger-shaped part
3508a, 3508b ... stub

Claims (14)

A method for inspecting a sample,
(A) a first test field associated with a first group of test structures, the first test field including a portion of the first group of test structures and a portion outside the first group of test structures; Irradiating a charged particle beam on one test field;
(B) scanning a first test field with the charged particle beam to determine whether a defect exists in the first group of test structures, in response to the scanning of the charged particle beam; Making the determination based on charged particles emitted from the first group of test structures;
(C) if it is determined that there is at least one defect in the first group of test structures, the plurality of parts while repeatedly moving to different parts in the first group of test structures; Scanning with the charged particle beam to determine the position of a specific defect in the first group of test structures;
An inspection method comprising: The inspection method according to claim 1,
The inspection method, wherein the at least one defect is located outside the first test field inspected in the step (b). The inspection method according to claim 1,
The inspection method, wherein the charged particle beam is an electron beam. The inspection method according to claim 1,
The step of (a) ~ (c), each of which repeatedly executed for a plurality of test fields associated with the test structure of one group, the inspection method. The inspection method according to claim 4, further comprising:
(D) storing defect information for each of the plurality of test fields;
With
The step (c) is performed after the steps (a) and (b) are performed for all of the plurality of test fields, and based on the defect information stored for each test field. Inspection method to be executed. The inspection method according to claim 1,
The step (b) includes a step of comparing the voltage contrast data acquired in the step (b) with a database. The inspection method according to claim 6,
The inspection method includes a voltage contrast data signature which is voltage contrast data when there is no defect in the database. The inspection method according to claim 1,
The step (b) includes a step of comparing the voltage contrast data acquired in the step (b) with a truth table. The inspection method according to claim 8,
The truth table includes an expected value when the test structure is dark and an expected value when the test structure is bright. The inspection method according to claim 1,
The sample is placed on a stage, and the step (a) includes a step of moving the stage. The inspection method according to claim 1,
The inspection method, wherein the step (a) includes a step of deflecting the charged particle beam. The inspection method according to claim 1,
The sample is placed on a stage, the charged particle beam moves through a row, and the step (a) includes a step of moving the row with respect to the stage. The inspection method according to claim 1,
An inspection method in which it is determined whether there are shorts or open defects in the conductive lines in the first group of test structures. The inspection method according to claim 1,
Depending on whether a voltage contrast pattern in which light and dark appear alternately in the first group of test structures scanned in the first test field is obtained, the first group of test structures An inspection method in which it is determined whether there is at least one defect therein.

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