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JP5187075B2 - Mounting method of semiconductor device - Google Patents

Mounting method of semiconductor device Download PDF

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Publication number
JP5187075B2
JP5187075B2 JP2008218097A JP2008218097A JP5187075B2 JP 5187075 B2 JP5187075 B2 JP 5187075B2 JP 2008218097 A JP2008218097 A JP 2008218097A JP 2008218097 A JP2008218097 A JP 2008218097A JP 5187075 B2 JP5187075 B2 JP 5187075B2
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Prior art keywords
semiconductor device
mounting
mounting member
semiconductor
semiconductor substrate
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JP2008218097A
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JP2010056213A (en
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要 加世田
望 赤木
康宏 北村
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for mounting a semiconductor device that can prevent a crack of the semiconductor device 1, and the chipping of the semiconductor device 1 when the semiconductor 1 is mounted to a mounting member 2. <P>SOLUTION: When the semiconductor device 1 is mounted to the mounting member 2, an adhesive material 3 is disposed on the mounting member 2, and then the semiconductor device 1 arranged on a supporting material 8 located over the mounting member 2 where the adhesive material 3 is disposed. Then, a portion with the adhesive material 3 in the mounting member 2 is pushed up by a jig 9 from the lower part of the mounting member 2 so that the adhesive material 3 may contact with the semiconductor device 1. After that, the semiconductor device 1 is separated from the supporting material 8 by lowering the jig 9, and mounted to the mounting member 2. Using such a mounting method for the semiconductor device 1, the semiconductor device 1 adhered to the supporting material 8 can be directly mounted to the mounting member 2, so that the crack of the semiconductor device 1 and the chipping of part of the semiconductor device 1 can be prevented. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体基板に複数の半導体素子を形成し、チップ単位に分割することにより半導体装置を形成すると共にそれぞれの半導体装置を実装部材に実装する半導体装置の実装方法に関するものである。   The present invention relates to a semiconductor device mounting method in which a plurality of semiconductor elements are formed on a semiconductor substrate and divided into chips to form a semiconductor device and each semiconductor device is mounted on a mounting member.

従来より、半導体基板に対して所望の半導体製造プロセスを実施することにより複数の半導体素子を形成し、半導体基板をチップ単位に分割して半導体装置を形成すると共にそれぞれの半導体装置を実装部材に実装する半導体装置の実装方法が知られている。   Conventionally, a plurality of semiconductor elements are formed by performing a desired semiconductor manufacturing process on a semiconductor substrate, and the semiconductor substrate is divided into chips to form a semiconductor device and each semiconductor device is mounted on a mounting member. A method for mounting a semiconductor device is known.

例えば、特許文献１には、以下の半導体装置の実装方法が開示されている。図３は従来の半導体装置の実装工程を示す断面図である。   For example, Patent Document 1 discloses the following semiconductor device mounting method. FIG. 3 is a cross-sectional view showing a conventional semiconductor device mounting process.

まず、図３（ａ）に示されるように、半導体素子が形成されていると共に表面に電極３０および表面保護膜３１が配置されている半導体基板３２を用意し、半導体基板３２の表面にバックグラインドテープ３３を配置する。   First, as shown in FIG. 3A, a semiconductor substrate 32 on which a semiconductor element is formed and an electrode 30 and a surface protection film 31 are arranged on the surface is prepared, and a back grind is formed on the surface of the semiconductor substrate 32. The tape 33 is disposed.

そして、図３（ｂ）に示されるように、半導体基板３２を裏面から所定の厚さになるようにバックグラインド等により研削した後、半導体基板３２の裏面に粘着シート３４を配置してバックグラインドテープを除去する。続いて、半導体基板３２をブレードダイシング等によりチップ単位に分割して半導体装置３５を形成する。その後、粘着シート３４に半導体装置３５が備えられた状態で粘着シート３４を半導体装置剥離装置３６に配置する。この半導体装置剥離装置３６は粘着シート３４を支持する支持台３７と、支持台３７の下方に配置され、粘着シート３４を擦ることで粘着シートの接着力を弱める摺動ピン３８と、粘着シート３４に接着されている半導体装置３５を粘着シート３４を介して上方に突き上げることで粘着シート３４から半導体装置３５の一部を剥離する押し上げピン３９とを有して構成されている。   Then, as shown in FIG. 3B, after the semiconductor substrate 32 is ground by a back grind or the like so as to have a predetermined thickness from the back surface, an adhesive sheet 34 is disposed on the back surface of the semiconductor substrate 32 and the back grind is performed. Remove the tape. Subsequently, the semiconductor device 32 is formed by dividing the semiconductor substrate 32 into chips by blade dicing or the like. Thereafter, the pressure-sensitive adhesive sheet 34 is placed in the semiconductor device peeling device 36 in a state where the pressure-sensitive adhesive sheet 34 is provided with the semiconductor device 35. This semiconductor device peeling device 36 is disposed below the support base 37 for supporting the adhesive sheet 34, the sliding pin 38 that weakens the adhesive force of the adhesive sheet by rubbing the adhesive sheet 34, and the adhesive sheet 34. The semiconductor device 35 is bonded to the adhesive sheet 34 and pushed up upward via the adhesive sheet 34 to have a push-up pin 39 for separating a part of the semiconductor device 35 from the adhesive sheet 34.

続いて、図３（ｃ）に示されるように、粘着シート３４を摺動ピン３８で擦った後、押し上げピン３９を上昇させて半導体装置３５を粘着シート３４を介して突き上げることで粘着シート３４から半導体装置３５の一部を剥離する。また、支持台３７の上方には粘着シート３４に備えられている半導体装置３５を吸着するコレット４０が配置されている。そして、図３（ｄ）に示されるように、半導体装置３５をコレット４０により吸着し、コレット４０を搬送して半導体装置３５を実装部材４１に接着材料４２を介して実装する。   Subsequently, as shown in FIG. 3C, after the adhesive sheet 34 is rubbed with the sliding pin 38, the push-up pin 39 is raised and the semiconductor device 35 is pushed up through the adhesive sheet 34, thereby causing the adhesive sheet 34. A part of the semiconductor device 35 is peeled off. A collet 40 that adsorbs the semiconductor device 35 provided on the adhesive sheet 34 is disposed above the support base 37. Then, as shown in FIG. 3D, the semiconductor device 35 is adsorbed by the collet 40, the collet 40 is conveyed, and the semiconductor device 35 is mounted on the mounting member 41 via the adhesive material 42.

また、例えば、特許文献２には、以下の半導体装置の実装方法が開示されている。まず、上記特許文献１と同様に、半導体基板に複数の半導体素子を形成する。そして、半導体基板の裏面を研削した後に、半導体基板の裏面に紫外線硬化性樹脂を有して構成される粘着シートを配置する。そして、半導体基板をチップ単位に分割して半導体装置を形成し、半導体装置を粘着シートに接着されている状態でチャックに固定する。その後、粘着シートに紫外線を照射して粘着シートの接着力を弱まらせ、治具を用いて半導体装置から粘着シートを引き剥がして半導体装置をチャックに保持する。最後に、チャックに保持されている半導体装置をコレットにより吸着して実装部材に実装する。
特開平６−２９５９３０号公報 特開２０００−３１５６９７号公報 Further, for example, Patent Document 2 discloses the following semiconductor device mounting method. First, similarly to Patent Document 1, a plurality of semiconductor elements are formed on a semiconductor substrate. And after grinding the back surface of a semiconductor substrate, the adhesive sheet comprised by having an ultraviolet curable resin on the back surface of a semiconductor substrate is arrange | positioned. Then, the semiconductor substrate is divided into chip units to form a semiconductor device, and the semiconductor device is fixed to the chuck while being bonded to the adhesive sheet. Thereafter, the adhesive sheet is irradiated with ultraviolet rays to weaken the adhesive force of the adhesive sheet, and the adhesive sheet is peeled off from the semiconductor device using a jig to hold the semiconductor device on the chuck. Finally, the semiconductor device held by the chuck is sucked by the collet and mounted on the mounting member.
JP-A-6-295930 JP 2000-315697 A

しかしながら、上記特許文献１の半導体装置３５の実装方法では、押し上げピン３９を上昇させて半導体装置３５を突き上げることにより粘着シート３４から半導体装置３５の一部を剥離しているため、半導体装置３５が、例えば、５０μｍ以下の薄厚である場合には、半導体装置３５を突き上げることにより、半導体装置３５が割れることや半導体装置３５の一部が欠けることがあるという問題がある。さらに、コレット４０により半導体装置３５を吸着するときにも、半導体装置３５とコレット４０とが接触することにより半導体装置３５が割れることや半導体装置３５の一部が欠けることがあるという問題がある。   However, in the mounting method of the semiconductor device 35 described in Patent Document 1, a part of the semiconductor device 35 is peeled off from the adhesive sheet 34 by raising the push-up pin 39 and pushing up the semiconductor device 35. For example, when the thickness is 50 μm or less, there is a problem that the semiconductor device 35 may be broken or a part of the semiconductor device 35 may be lost by pushing up the semiconductor device 35. Further, when the semiconductor device 35 is attracted by the collet 40, there is a problem that the semiconductor device 35 may be broken or a part of the semiconductor device 35 may be lost due to the contact between the semiconductor device 35 and the collet 40.

また、上記特許文献２の半導体装置の実装方法では、粘着シートに紫外線硬化性樹脂を有した材料を用いており、半導体装置と粘着シートとを剥離する際に、粘着シートに紫外線を照射して粘着シートの接着力を弱め、治具を用いて半導体装置と粘着シートとを剥離している。このため、粘着シートから半導体装置を剥離する際に、半導体装置を突き上げる必要がなく、半導体装置を突き上げることにより半導体装置が割れることや半導体装置の一部が欠けることを防止することができる。しかしながら、粘着シートから剥離された半導体装置はコレットにより吸着されて実装部材に実装されるため、半導体装置とコレットとが接触することにより半導体装置が割れることや半導体装置の一部が欠けることがあるという問題がある。   Moreover, in the mounting method of the semiconductor device of the said patent document 2, the material which has the ultraviolet curable resin for the adhesive sheet is used, and when peeling a semiconductor device and an adhesive sheet, an ultraviolet-ray is irradiated to an adhesive sheet. The adhesive force of the pressure-sensitive adhesive sheet is weakened, and the semiconductor device and the pressure-sensitive adhesive sheet are separated using a jig. For this reason, when peeling a semiconductor device from an adhesive sheet, it is not necessary to push up a semiconductor device, and it can prevent that a semiconductor device cracks or a part of semiconductor device is missing by pushing up a semiconductor device. However, since the semiconductor device peeled off from the adhesive sheet is attracted by the collet and mounted on the mounting member, the semiconductor device may be broken or a part of the semiconductor device may be lost due to the contact between the semiconductor device and the collet. There is a problem.

本発明は上記点に鑑みて、半導体装置を実装部材に実装する際に、半導体装置が割れることや半導体装置が欠けることを防止することができる半導体装置の実装方法を提供することを目的とする。   SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a method for mounting a semiconductor device that can prevent the semiconductor device from being cracked or chipped when the semiconductor device is mounted on a mounting member. .

上記目的を達成するため、請求項１に記載の発明では、複数の半導体素子が形成された半導体基板（４）を用意する工程と、半導体基板（４）の表面に複数の半導体素子とそれぞれ電気的に接続される第１導体（５）を形成する工程と、半導体基板（４）の表面に支持材（８）を配置し、支持材（８）に半導体基板（４）を接着する工程と、半導体基板（１）を支持材（８）で支持しながら裏面から研削する工程と、半導体基板（４）を半導体基板（４）の裏面から分割してチップ単位に分割された半導体装置（１）を形成する工程と、半導体装置（１）を支持材（８）から分離して実装部材（２）に接着材料（３）を介して実装する工程と、を有する半導体装置の実装方法であって、次のような点を特徴としている。   In order to achieve the above object, according to the first aspect of the present invention, a step of preparing a semiconductor substrate (4) on which a plurality of semiconductor elements are formed, and a plurality of semiconductor elements on the surface of the semiconductor substrate (4) are electrically connected. Forming a first conductor (5) to be electrically connected, placing a support material (8) on the surface of the semiconductor substrate (4), and bonding the semiconductor substrate (4) to the support material (8); The step of grinding from the back surface while supporting the semiconductor substrate (1) with the support material (8), and the semiconductor device (1) divided into chips by dividing the semiconductor substrate (4) from the back surface of the semiconductor substrate (4). ) And a step of separating the semiconductor device (1) from the support material (8) and mounting it on the mounting member (2) via the adhesive material (3). It has the following features.

すなわち、半導体装置（１）を実装部材（２）に実装する工程は、実装部材（２）に接着材料（３）を配置し、接着材料（３）が配置された実装部材（２）の上方に支持材（８）に備えられた半導体装置（１）を配置して実装部材（２）の下方から実装部材（２）のうち接着材料（３）が配置されている部分を治具（９）により押し上げて接着材料（３）を半導体装置（１）に接触させる工程と、治具（９）を降下させることにより、半導体装置（１）を支持材（８）から分離して実装部材（２）に実装する工程を含むことを特徴としている。   That is, in the step of mounting the semiconductor device (1) on the mounting member (2), the adhesive material (3) is disposed on the mounting member (2), and the upper side of the mounting member (2) on which the adhesive material (3) is disposed. The semiconductor device (1) provided on the support member (8) is disposed on the mounting member (2) from below the mounting member (2), and the portion where the adhesive material (3) is disposed is placed on the jig (9 ) To bring the adhesive material (3) into contact with the semiconductor device (1) and lower the jig (9) to separate the semiconductor device (1) from the support member (8) and to mount the mounting member ( 2) includes a mounting step.

このような半導体装置の実装方法によれば、半導体装置（１）を支持材（８）から実装部材（２）に直接実装することができ、コレット等を用いる必要がないので半導体装置（１）が割れることや半導体装置の一部が欠けたりすることを防止することができる。   According to such a mounting method of a semiconductor device, the semiconductor device (1) can be directly mounted on the mounting member (2) from the support member (8), and it is not necessary to use a collet or the like. Can be prevented from cracking or part of the semiconductor device being chipped.

例えば、請求項２に記載の発明のように、半導体装置（１）を実装部材（２）に実装する工程では、半導体装置（１）を形成する工程を行った後、支持材（８）の接着力を弱める工程を行い、少なくとも半導体装置（１）と接着材料（３）とが接触している状態において支持材（８）の弱められた接着力が接着材料（３）の接着力より弱くなるようにすることもできる。   For example, in the step of mounting the semiconductor device (1) on the mounting member (2) as in the invention described in claim 2, after the step of forming the semiconductor device (1) is performed, the support material (8) The step of weakening the adhesive force is performed, and at least in the state where the semiconductor device (1) and the adhesive material (3) are in contact, the weakened adhesive force of the support material (8) is weaker than the adhesive force of the adhesive material (3). It can also be made.

また、請求項３に記載の発明のように、半導体装置（１）を実装する工程では、治具（９）のうち実装部材（２）を押し上げる部分の面積が半導体装置（１）の裏面の面積より大きい治具（９）を用いて行うことができる。   Further, as in the third aspect of the invention, in the step of mounting the semiconductor device (1), the area of the jig (9) where the mounting member (2) is pushed up is the back surface of the semiconductor device (1). This can be done using a jig (9) larger than the area.

また、請求項４に記載の発明のように、支持材（８）に半導体基板（４）を接着する工程を行った後、半導体装置（１）を形成する工程の前に、半導体基板（４）の裏面に複数の半導体素子とそれぞれ電気的に接続される第２導体（７）を形成する工程を行い、半導体装置（１）を実装部材（２）に実装する工程では、接着材料（３）を導電性材料を有して構成した材料を用いることができる。 Moreover, after performing the process which adhere | attaches a semiconductor substrate (4) to a support material (8) like invention of Claim 4 , before the process of forming a semiconductor device (1), a semiconductor substrate (4 In the step of forming the second conductor (7) electrically connected to the plurality of semiconductor elements on the back surface of the semiconductor device (1) and mounting the semiconductor device (1) on the mounting member (2), the adhesive material (3 ) Can be used as a material having a conductive material.

さらに、請求項５に記載の発明のように、支持材（８）を紫外線硬化性樹脂を有する材料で構成し、支持材（８）に紫外線を照射することにより支持材（８）の接着力を弱めることもできる。 Further, as in the invention described in claim 5 , the support material (8) is made of a material having an ultraviolet curable resin, and the support material (8) is irradiated with ultraviolet rays to thereby adhere the support material (8). Can also be weakened.

なお、この欄および特許請求の範囲で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

（第１実施形態）
本発明の第１実施形態について説明する。図１は本実施形態の半導体装置の実装方法を適用して実装部材に実装された半導体装置の断面構成を示す図であり、この図に基づいて説明する。 (First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor device mounted on a mounting member by applying the semiconductor device mounting method of the present embodiment, and will be described based on this drawing.

図１に示されるように、半導体装置１がリードフレーム等の実装部材２に導電性材料３を介して実装されている。なお、本実施形態では導電性材料３が接着材料に相当する。   As shown in FIG. 1, a semiconductor device 1 is mounted on a mounting member 2 such as a lead frame via a conductive material 3. In the present embodiment, the conductive material 3 corresponds to an adhesive material.

本実施形態の半導体装置１は、所望の半導体製造プロセスを実施することにより半導体素子が形成されている半導体基板４と、半導体基板４の表面に配置されている第１電極５および表面保護膜６と、半導体基板４の裏面に配置されている第２電極７とを有して構成されている。そして、第１電極５は表面保護膜６から露出した構成とされている。なお、本実施形態では、第１電極５が本発明の第１導体に相当し、第２電極７が本発明の第２導体に相当する。また、表面保護膜６には、例えば、ポリイミド膜、シリコン窒化膜およびシリコン酸化膜等を用いることができる。   The semiconductor device 1 of this embodiment includes a semiconductor substrate 4 on which a semiconductor element is formed by performing a desired semiconductor manufacturing process, and a first electrode 5 and a surface protective film 6 disposed on the surface of the semiconductor substrate 4. And a second electrode 7 disposed on the back surface of the semiconductor substrate 4. The first electrode 5 is exposed from the surface protective film 6. In the present embodiment, the first electrode 5 corresponds to the first conductor of the present invention, and the second electrode 7 corresponds to the second conductor of the present invention. For the surface protective film 6, for example, a polyimide film, a silicon nitride film, a silicon oxide film, or the like can be used.

次に本実施形態の半導体装置の実装方法について説明する。   Next, a method for mounting the semiconductor device of this embodiment will be described.

図２は、本実施形態における半導体装置の実装工程を示す断面図である。まず、図２（ａ）に示されるように、複数の半導体素子が形成された半導体基板４を用意する。そして、半導体基板４の表面に、半導体素子と電気的に接続される第１電極５を形成すると共に、第１電極５が覆われるように表面保護膜６を配置する。その後、表面保護膜６のうち第１電極５上に配置されている部分をフォトリソグラフィにより除去して第１電極５を露出させる。   FIG. 2 is a cross-sectional view showing the mounting process of the semiconductor device in the present embodiment. First, as shown in FIG. 2A, a semiconductor substrate 4 on which a plurality of semiconductor elements are formed is prepared. Then, the first electrode 5 electrically connected to the semiconductor element is formed on the surface of the semiconductor substrate 4, and the surface protective film 6 is disposed so as to cover the first electrode 5. Then, the part arrange | positioned on the 1st electrode 5 among the surface protection films 6 is removed by photolithography, and the 1st electrode 5 is exposed.

続いて、図２（ｂ）に示されるように、半導体基板４の表面に表面保護膜６および第１電極５が覆われるように支持材８を配置し、半導体基板４を支持材８に接着する。この支持材８は、例えば、接着力が変化する材料で構成されているものを用いることができ、本実施形態では紫外線硬化性樹脂を有する材料で構成されたものを用いている。その後、半導体基板４をバックグラインド等により、半導体基板４の厚さが、例えば、１〜１００μｍの厚さになるまで研削する。   Subsequently, as shown in FIG. 2B, the support material 8 is disposed so that the surface protective film 6 and the first electrode 5 are covered on the surface of the semiconductor substrate 4, and the semiconductor substrate 4 is bonded to the support material 8. To do. As this support material 8, for example, a material composed of a material whose adhesive force changes can be used. In this embodiment, a material composed of a material having an ultraviolet curable resin is used. Thereafter, the semiconductor substrate 4 is ground by back grinding or the like until the thickness of the semiconductor substrate 4 becomes, for example, 1 to 100 μm.

次に、図２（ｃ）に示されるように、半導体基板４の裏面に、半導体素子と電気的に接続される第２電極７を形成する。続いて、第２電極７をアライメントとして、ブレードダイシング等により、半導体基板４を裏面から分割してチップ単位に分割された半導体装置１を形成する。その後、図２（ｄ）に示されるように、支持材８に紫外線を照射することにより、支持材８の接着力を弱める。   Next, as illustrated in FIG. 2C, the second electrode 7 that is electrically connected to the semiconductor element is formed on the back surface of the semiconductor substrate 4. Subsequently, using the second electrode 7 as an alignment, the semiconductor device 1 is divided into chips by dividing the semiconductor substrate 4 from the back surface by blade dicing or the like. Thereafter, as shown in FIG. 2D, the support material 8 is irradiated with ultraviolet rays to weaken the adhesive force of the support material 8.

そして、図２（ｅ）に示されるように、実装部材２に導電性材料３を配置し、導電性材料３が配置された実装部材２の上方に支持材８に備えられた半導体装置１を配置する。この導電性材料３は、図２（ｄ）の工程を行った後の支持材８の接着力が導電性材料３の接着力より弱くなるものを用いることができ、例えば、銀ペーストを用いることができる。続いて、実装部材２の下方から実装部材２のうち導電性材料３が配置されている部分を治具９により押し上げて導電性材料３を半導体装置１に接触させる。この治具９は、治具９の実装部材２を押し上げる力が実装部材２および導電性材料３を介して半導体装置１に伝達されることを抑制するために、実装部材２と接触する部分の面積が半導体装置１の裏面の面積より大きくなるようにされている。   2E, the conductive material 3 is disposed on the mounting member 2, and the semiconductor device 1 provided on the support member 8 is disposed above the mounting member 2 on which the conductive material 3 is disposed. Deploy. As the conductive material 3, a material in which the adhesive strength of the support material 8 after the process of FIG. 2D is weaker than the adhesive strength of the conductive material 3 can be used. For example, a silver paste is used. Can do. Subsequently, the portion of the mounting member 2 where the conductive material 3 is disposed is pushed up by the jig 9 from below the mounting member 2 to bring the conductive material 3 into contact with the semiconductor device 1. The jig 9 has a portion in contact with the mounting member 2 in order to suppress the force that pushes up the mounting member 2 of the jig 9 from being transmitted to the semiconductor device 1 through the mounting member 2 and the conductive material 3. The area is made larger than the area of the back surface of the semiconductor device 1.

その後、図２（ｆ）に示されるように、支持材８の接着力が導電性材料３の接着力より弱くなっている状態で治具９を降下させることにより、半導体装置１を支持材８から分離して実装部材２に実装する。   Thereafter, as shown in FIG. 2 (f), the semiconductor device 1 is supported on the support member 8 by lowering the jig 9 in a state where the adhesive force of the support member 8 is weaker than that of the conductive material 3. And mounted on the mounting member 2.

このような半導体装置の実装方法によれば、支持材８に接着されている半導体装置１を実装部材２に直接実装することができ、コレットにより半導体装置１を吸着する必要がないので、半導体装置１が割れたりすることや半導体装置１の一部が欠けたりすることを防止することができる。さらに、半導体装置１を実装する際にコレットを用いる必要がないため、コレットに付着している異物が半導体装置１や実装部材２に付着することもなく、半導体装置１を実装する際の設備を簡素化することもできる。さらに、半導体装置１の表面に配置される支持材８は、従来の半導体装置の実装工程におけるブレードダイシングをする際に用いられる粘着シートの機能も兼ねているため、半導体装置１の裏面に新たに粘着シートを配置する必要もなく、従来の半導体装置の実装方法と比較して製造工程を減少することもできる。   According to such a semiconductor device mounting method, the semiconductor device 1 bonded to the support member 8 can be directly mounted on the mounting member 2, and it is not necessary to suck the semiconductor device 1 with a collet. It is possible to prevent the 1 from cracking or a part of the semiconductor device 1 from being chipped. Furthermore, since it is not necessary to use a collet when mounting the semiconductor device 1, foreign matter adhering to the collet does not adhere to the semiconductor device 1 or the mounting member 2, and facilities for mounting the semiconductor device 1 are provided. It can also be simplified. Furthermore, since the support material 8 disposed on the front surface of the semiconductor device 1 also serves as a pressure-sensitive adhesive sheet used when performing blade dicing in the conventional semiconductor device mounting process, the support material 8 is newly provided on the back surface of the semiconductor device 1. There is no need to dispose an adhesive sheet, and the number of manufacturing steps can be reduced as compared with a conventional semiconductor device mounting method.

（他の実施形態）
上記第１実施形態では、導電性材料３として銀ペーストを例に挙げて説明したが、もちろん他の材料を用いることもできる。例えば、導電性材料３として熱硬化性材料を有する熱硬化性はんだを用いてもよい。導電性材料３として熱硬化性はんだを用いた場合には、治具９に治具９を加熱することのできる部材を備え、半導体装置１と導電性材料３とを接触させた状態で導電性材料３を加熱することができるようにし、治具９を加熱することにより導電性材料３を硬化させて、支持材８の接着力が導電性材料３の接着力より弱くなるようにしてもよい。 (Other embodiments)
In the said 1st Embodiment, although the silver paste was mentioned as an example as the electroconductive material 3, of course, another material can also be used. For example, a thermosetting solder having a thermosetting material may be used as the conductive material 3. When a thermosetting solder is used as the conductive material 3, the jig 9 is provided with a member capable of heating the jig 9, and the semiconductor device 1 and the conductive material 3 are in contact with each other. The material 3 can be heated, and the conductive material 3 is cured by heating the jig 9 so that the adhesive force of the support material 8 is weaker than the adhesive force of the conductive material 3. .

さらに、紫外線を照射しなくても支持材８の接着力が導電性材料３の接着力より弱くなる場合には上記図２（ｄ）の支持材８に紫外線を照射する工程を行わなくてもよい。また、上記図２（ｄ）の工程を行わない場合には、支持材８を接着力が変化する材料で構成しなくてもよい。   Furthermore, if the adhesive strength of the support material 8 becomes weaker than the adhesive strength of the conductive material 3 without irradiating with ultraviolet rays, the step of irradiating the support material 8 with the ultraviolet rays in FIG. Good. Further, in the case where the process of FIG. 2D is not performed, the support material 8 may not be formed of a material whose adhesive force changes.

また、半導体基板４の裏面に第２電極７が備えられていない構成としてもよい。この場合は、上記図２（ｃ）の工程において、半導体素子の表面に配置されている第１電極５をアライメントとして認識し、両面アライナー等を用いて半導体基板４の裏面からブレードダイシング等により半導体基板４を分割してチップ単位に分割された半導体装置１を形成することもできる。このような半導体装置１を形成した場合には、導電性材料３の代わりに、例えば、シリコーン系樹脂等の接着材料を介して半導体装置１を実装部材２に実装してもよい。   Further, the second electrode 7 may not be provided on the back surface of the semiconductor substrate 4. In this case, in the process of FIG. 2C, the first electrode 5 disposed on the surface of the semiconductor element is recognized as alignment, and the semiconductor is formed by blade dicing or the like from the back surface of the semiconductor substrate 4 using a double-side aligner or the like. The semiconductor device 1 can also be formed by dividing the substrate 4 into chips. When such a semiconductor device 1 is formed, the semiconductor device 1 may be mounted on the mounting member 2 via an adhesive material such as a silicone resin instead of the conductive material 3.

また、支持材８として紫外線硬化性樹脂を用いた例を説明したが、例えば、支持材８をガラス基板と紫外線樹脂硬化性樹脂とを用いて構成してもよい。支持材８をガラス基板と紫外線硬化性樹脂とを用いて構成した場合には、上記図２（ｂ）の工程において、半導体基板４の厚さを５０μｍ以下にまで研削する場合においても半導体基板４に余分な応力が印加されることを抑制することができる。また、支持材８をガラス基板と紫外線硬化性樹脂とを用いて構成した場合には、支持材８を紫外線硬化性樹脂のみで構成した場合よりも支持材８が撓むことを抑制することができるため、半導体装置１を実装部材２に実装し易くなる。さらに、支持材８として、例えば、赤外線硬化性樹脂等を用いることもできる。   Moreover, although the example which used the ultraviolet curable resin as the support material 8 was demonstrated, you may comprise the support material 8 using a glass substrate and ultraviolet resin curable resin, for example. When the support material 8 is configured using a glass substrate and an ultraviolet curable resin, the semiconductor substrate 4 can be used even when the thickness of the semiconductor substrate 4 is ground to 50 μm or less in the process of FIG. It is possible to suppress an excessive stress from being applied. Moreover, when the support material 8 is configured using a glass substrate and an ultraviolet curable resin, it is possible to suppress the bending of the support material 8 more than when the support material 8 is configured only with an ultraviolet curable resin. Therefore, the semiconductor device 1 can be easily mounted on the mounting member 2. Furthermore, as the support material 8, for example, an infrared curable resin or the like can be used.

さらに、半導体装置１を裏面に二つ以上の第２電極７を有する構成とすることもできる。この場合は、導電性材料３として、例えば、異方導電性フィルムや異方導電性ペースト等を用いることができる。   Furthermore, the semiconductor device 1 may be configured to have two or more second electrodes 7 on the back surface. In this case, for example, an anisotropic conductive film or an anisotropic conductive paste can be used as the conductive material 3.

また、図２（ｃ）の工程において、半導体基板４の裏面に第２電極７を配置する代わりに、半導体基板４に半導体基板４の表裏を貫通する貫通孔を形成し、貫通孔の壁面に絶縁膜を配置すると共に貫通孔の内部に導体を埋め込むことで第１電極５と電気的に接続される貫通電極を形成することもできる。   2C, instead of disposing the second electrode 7 on the back surface of the semiconductor substrate 4, a through hole penetrating the front and back of the semiconductor substrate 4 is formed in the semiconductor substrate 4, and the wall surface of the through hole is formed. A through electrode that is electrically connected to the first electrode 5 can also be formed by disposing an insulating film and embedding a conductor in the through hole.

本発明の第１実施形態における半導体装置の実装方法を適用して実装部材に実装された半導体装置の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the semiconductor device mounted in the mounting member by applying the mounting method of the semiconductor device in 1st Embodiment of this invention. 図１に示す半導体装置の実装工程を示す断面図である。FIG. 7 is a cross-sectional view showing a mounting process of the semiconductor device shown in FIG. 1. 従来の半導体装置の実装工程を示す断面図である。It is sectional drawing which shows the mounting process of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ 実装部材
３ 導電性材料
４ 半導体基板
５ 第１電極
６ 表面保護膜
７ 第２電極
８ 支持材
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Mounting member 3 Conductive material 4 Semiconductor substrate 5 1st electrode 6 Surface protective film 7 2nd electrode 8 Support material

Claims (5)

前記半導体基板（４）の表面に複数の前記半導体素子とそれぞれ電気的に接続される第１導体（５）を形成する工程と、
前記半導体基板（４）の表面に支持材（８）を配置し、前記支持材（８）に前記半導体基板（４）を接着する工程と、
前記半導体基板（４）を前記支持材（８）で支持しながら裏面から研削する工程と、
前記半導体基板（４）を前記半導体基板（４）の裏面から分割してチップ単位に分割された半導体装置（１）を形成する工程と、
前記半導体装置（１）を前記支持材（８）から分離して実装部材（２）に接着材料（３）を介して実装する工程と、を有する半導体装置の実装方法であって、
前記半導体装置（１）を前記実装部材（２）に実装する工程は、前記実装部材（２）に前記接着材料（３）を配置し、前記接着材料（３）が配置された前記実装部材（２）の上方に前記支持材（８）に備えられた前記半導体装置（１）を配置した後、前記実装部材（２）の下方から前記実装部材（２）のうち前記接着材料（３）が配置されている部分を治具（９）により押し上げて前記接着材料（３）を前記半導体装置（１）に接触させる工程と、前記治具（９）を降下させることにより、前記半導体装置（１）を前記支持材（８）から分離して前記実装部材（２）に実装する工程と、を含むことを特徴とする半導体装置の実装方法。 Forming a first conductor (5) electrically connected to each of the plurality of semiconductor elements on the surface of the semiconductor substrate (4);
Placing a support material (8) on the surface of the semiconductor substrate (4), and bonding the semiconductor substrate (4) to the support material (8);
Grinding from the back surface while supporting the semiconductor substrate (4) with the support material (8);
Dividing the semiconductor substrate (4) from the back surface of the semiconductor substrate (4) to form a semiconductor device (1) divided into chips;
A step of separating the semiconductor device (1) from the support material (8) and mounting it on a mounting member (2) via an adhesive material (3),
In the step of mounting the semiconductor device (1) on the mounting member (2), the mounting material (3) is disposed on the mounting member (2), and the mounting member (3) is disposed on the mounting member (2). After the semiconductor device (1) provided on the support member (8) is disposed above 2), the adhesive material (3) of the mounting member (2) is disposed below the mounting member (2). A step of pushing up the arranged portion by a jig (9) to bring the adhesive material (3) into contact with the semiconductor device (1), and a lowering of the jig (9), thereby the semiconductor device (1 And a step of separating from the support member (8) and mounting on the mounting member (2). 前記半導体装置（１）を前記実装部材（２）に実装する工程では、前記半導体装置（１）を形成する工程を行った後、前記支持材（８）の接着力を弱める工程を行い、少なくとも前記半導体装置（１）と前記接着材料（３）とが接触している状態において前記支持材（８）の弱められた接着力が前記接着材料（３）の接着力より弱くなるようにすることを特徴とする請求項１に記載の半導体装置の実装方法。   In the step of mounting the semiconductor device (1) on the mounting member (2), after performing the step of forming the semiconductor device (1), performing the step of weakening the adhesive force of the support material (8), In the state where the semiconductor device (1) and the adhesive material (3) are in contact with each other, the weakened adhesive force of the support material (8) is made weaker than the adhesive force of the adhesive material (3). The method of mounting a semiconductor device according to claim 1. 前記半導体装置（１）を実装する工程では、前記治具（９）のうち前記実装部材（２）を押し上げる部分の面積が前記半導体装置（１）の裏面の面積より大きい治具（９）を用いて行うことを特徴とする請求項１または２に記載の半導体装置の実装方法。   In the step of mounting the semiconductor device (1), a jig (9) in which the area of the jig (9) that pushes up the mounting member (2) is larger than the area of the back surface of the semiconductor device (1). The method for mounting a semiconductor device according to claim 1, wherein the mounting method is used. 前記支持材（８）に前記半導体基板（４）を接着する工程を行った後、前記半導体装置（１）を形成する工程の前に、前記半導体基板（４）の裏面に複数の前記半導体素子とそれぞれ電気的に接続される第２導体（７）を形成する工程を行い、
前記半導体装置（１）を前記実装部材（２）に実装する工程では、前記接着材料（３）として導電性材料を有して構成した材料を用いることを特徴とする請求項１ないし３のいずれか１つに記載の半導体装置の実装方法。 After the step of bonding the semiconductor substrate (4) to the support material (8) and before the step of forming the semiconductor device (1), a plurality of the semiconductor elements are formed on the back surface of the semiconductor substrate (4). And forming a second conductor (7) electrically connected to each other,
Wherein in the step of mounting a semiconductor device (1) on the mounting member (2), either the adhesive material (3) as claims 1, characterized by using a configuration material with a conductive material 3 A method for mounting the semiconductor device according to claim 1. 前記支持材（８）を紫外線硬化性樹脂を有する材料で構成し、前記支持材（８）に紫外線を照射することにより前記支持材（８）の接着力を弱めることを特徴とする請求項１ないし４のいずれか１つに記載の半導体装置の実装方法。 The said support material (8) is comprised with the material which has an ultraviolet curable resin, and the adhesive force of the said support material (8) is weakened by irradiating the said support material (8) with an ultraviolet-ray. 5. A method for mounting a semiconductor device according to any one of items 4 to 4 .
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