JP5186831B2 - Electronic device manufacturing method using graphene - Google Patents

Description

  The present invention relates to a method for manufacturing an electronic device using graphene, and in particular, is characterized by a configuration for realizing a high-frequency field-effect transistor and graphene wiring using graphene as a channel region with good reproducibility and accuracy. The present invention relates to a method for manufacturing an electronic device using a certain graphene.

  In recent years, transistors using carbon nanotubes have attracted attention as next-generation compact and high-speed devices, and there are many reports of transistors using carbon nanotubes as channels (see, for example, Patent Document 1), but most of them have been reported. The current situation is that there is almost no report of high-speed operation, but only DC operation confirmation.

  This is because the diameter of the carbon nanotube that becomes the channel is as small as several nanometers, so the ratio of the surface area to the volume is large and it is easily affected by the surroundings, and the number of tubes that become the channel is about several, and it can be driven This is because the current is as small as about 10 μA.

That is, the current carbon nanotube transistor has a serious problem that the parasitic capacitance ratio with respect to the intrinsic capacitance is very large as compared with other transistors, for example, MOS transistors, and high speed operation is impossible.
In other words, the problem is that the channel width cannot be controlled.

  In addition, the carbon nanotube channel is usually formed by growth, but at that time, it is difficult to control the chirality, and there is a problem that a metal nanotube is formed by mixing with the semiconductor nanotube.

  Therefore, controlling the channel width to create a semiconductor-only channel is an issue for carbon-based transistors as next-generation devices.

  Therefore, in order to solve such problems, a graphene transistor using a graphene, which is a single-layer graphite, as a channel, which can easily control the channel width, has been proposed as a carbon-based transistor instead of the carbon nanotube transistor.

For example, an SiC thin film heat treated to create a graphene semiconductor external dimensions 80nm of by removing the Si, the electron mobility in the Si impurity doped 1,500cm ² / V · sec greater than 25,000cm ² / It has been reported that an electron mobility of V · sec was obtained (for example, see Non-Patent Document 1).

Alternatively, a single graphene sheet having a thickness of several atomic layers is peeled off from a high-quality parent crystal, and a field effect transistor is formed from the graphene sheet, and exceeds 10,000 cm ² / V · sec at room temperature. It has also been reported that high mobility was observed (see, for example, Non-Patent Document 2).
JP 2003-338621 A http: // www. ednjapan. com / content / I_news / 2006/04 / 19_01. html http: // www. ricoh. co. jp / abs_club / Science / Science-2004-1022. html

  However, in the case of the above-mentioned report on graphene, the preparation of graphene sheet is a very special method, and there is a problem that such a preparation method of graphene sheet is not suitable for industrialization and mass production.

  In view of this, the present inventor has proposed to construct a transistor using graphene produced by a normal carbon nanotube growth method (see Japanese Patent Application No. 2007-040775 if necessary).

  In this proposal, the graphene formed at the tip of the carbon nanotube growth process is transferred and fixed to the substrate provided with an insulator having an adhesive action by the adhesive action of the insulator, and then the graphene is patterned by electron beam lithography. Thus, a channel is formed.

  However, in the patterning by electron beam lithography, it is difficult to control the width of the channel with high accuracy, and there is a problem that elements having a metallic property and not operating as a transistor are mixed.

  That is, when the number of the six-membered rings constituting the graphene along the zigzag direction is a multiple of 3, graphene exhibits metallic properties and does not exhibit semiconducting properties. Although it is necessary to define the channel width so that the number along the line is 3n ± 1, it is difficult to accurately match the channel width direction to the zigzag direction with the alignment accuracy by electron beam lithography.

  Also, with patterning accuracy by electron beam lithography, it is difficult to control the number of six-membered rings along the zigzag direction to 3n ± 1, that is, to control the width with an accuracy of about 0.4 nm.

  Therefore, an object of the present invention is to arbitrarily form graphene having semiconducting properties or graphene having metallic properties by controlling the channel width and directionality of graphene.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
See FIG. 1 In order to solve the above-described problem, the present invention relates to a method of manufacturing an electronic device using graphene 1, using a scanning probe microscope, and using the cantilever 2 of the scanning probe microscope in the crystal axis direction of graphene 1 The width of the extending direction of the graphene 1 and the crystal direction of the extending direction of the graphene 1 are simultaneously defined by running with the cantilever 2 pressed against the graphene 1 while confirming the above.

  As described above, by using the scanning probe microscope, the cantilever 2 of the scanning probe microscope is pressed against the graphene 1 and is marked in a predetermined direction, whereby the crystal axis direction and the width of the graphene 1 are set in an arbitrary direction or an arbitrary Since the width can be controlled, only the graphene 1 having semiconducting properties or the graphene 1 having metallic properties can be arbitrarily formed.

  In this case, since the band gap of the graphene 1 having semiconductor properties is defined by the width of the graphene 1, when the graphene 1 is used for the channel 3 of the transistor, the band gap is controlled by controlling the width of the graphene 1. Thus, the electrical characteristics such as the withstand voltage of the transistor can be arbitrarily controlled.

  Alternatively, the width of the graphene 1 can also be used as a wiring by controlling the number of six-membered rings along the zigzag direction to be a multiple of three.

  Further, when patterning the graphene 1, it is desirable to perform a step of defining the width in the extending direction of the graphene 1 and the crystal direction in the extending direction of the graphene 1 with a scanning probe microscope in a hydrogen atmosphere, Since the active bond at the edge portion of the graphene 1 is terminated with hydrogen and becomes inactive, the characteristics are stabilized.

  Further, the graphene 1 in this case is preferably the graphene 1 formed at the tip of the carbon nanotube growth process, and the single-layer graphene 1 can be stably formed by using a conventional ordinary carbon nanotube growth method. It can be formed with good reproducibility.

  Further, when fixing the graphene 1 to the substrate 4, the graphene 1 may be transferred and fixed to the substrate 4 provided with the insulator 5 having an adhesive action by the adhesive action of the insulator 5. The single-layer graphene 1 can be taken out stably and with good reproducibility without paying close attention to the handling of No. 1.

  In this case, the scanning probe microscope means any one of a narrowly-defined scanning probe microscope (SPM), an atomic force microscope (AFM), a magnetic force microscope (MFM), or an electric force microscope (EFM). To do.

  According to the present invention, the width of the graphene and the crystal direction to be processed can be controlled arbitrarily and with good reproducibility, so that whether the electrical characteristics of the graphene are semiconducting or electrical is arbitrarily controlled. Therefore, it is possible to mass-produce the next generation of small and high speed transistors.

In the present invention, after graphene formed at the tip of a carbon nanotube growth process using TiN / Co or the like as a catalyst is transferred and fixed to a substrate provided with an insulator having an adhesive action by the adhesive action of the insulator. By using a scanning probe microscope in a broad sense, such as an atomic force microscope (AFM), while confirming the crystal axis direction of the graphene with the cantilever, the graphene The width defines the crystal axis direction at the same time.
Note that a region corresponding to the width of the cantilever scraped by the cantilever is a separation region between the channels.

Here, with reference to FIG. 2 thru | or FIG. 6, the manufacturing process of the back gate type graphene transistor of Example 1 of this invention is demonstrated.
See Figure 2
First, a substrate is prepared in a state where an SOG (spin-on-glass) film 12 having a thickness of, for example, 100 nm is applied to the p-type silicon substrate 11.

On the other hand, a TiN film 24 having a thickness of, for example, 5 nm and a Co film having a thickness of, for example, 1 nm are formed on the surface of a p-type silicon substrate 21 having a SiO ₂ film 22 formed on the surface by, for example, thermal oxidation. 25 are sequentially deposited to form the catalytic metal 23, and the carbon nanotubes 26 are grown to a height of, for example, 10 μm at a growth temperature of 600 ° C. by a CVD method using acetylene as a raw material under a pressure of 100 Pa.

  In this growth process, the Co film 25 melted by heat locally aggregates to become a growth nucleus of the carbon nanotube 26, and the carbon nanotube 26 grows in the vertical direction, and graphene 27 is formed on the top surface of the carbon nanotube 26. It is formed.

  Next, the p-type silicon substrate 21 on which the carbon nanotubes 26 are grown and the p-type silicon substrate 11 provided with the SOG film 12 are brought into contact with each other so that the graphene 27 and the SOG film 12 face each other. Both substrates are bonded together by curing 12 at a temperature of 300 ° C., for example.

  Next, the bonded substrates are mechanically peeled off so that the bonded carbon nanotubes 26 and the catalytic metal 23 are peeled off at the joints.

See Figure 3
Next, by selectively removing the carbon nanotubes 26 by wet etching using sulfuric acid + hydrogen peroxide solution, the extraction of the graphene 27 is completed.

See FIG. 4 and FIG.
Next, using the AFM apparatus, the extracted graphene is scratched with a cantilever 14 provided in the AFM apparatus, whereby atoms are separated, and a portion that is not scratched is a channel array 28 composed of a plurality of channels.

At this time, an atomic image of the graphene 27 is taken out by using AFM, and then the crystal axis of the graphene 27 which is a semiconductor property is aligned with the scanning direction of the cantilever 14.
At this time, the horizontal pitch is set in consideration of the scratch width and the array width. Here, the axis is perpendicular to the zigzag direction shown in the drawing (that is, the direction perpendicular to the diagonal line of the six-membered ring). And 5 pieces of 6-membered rings (3n-1: n = 2), that is, about 2 nm (≈0.4325 nm × 5).

Note that the length direction is set to several cm, for example, 3 cm, although it depends on the extracted graphene area.
In addition, the scratch width in this case depends on the width of the tip of the cantilever 14, but is about 10 nm, for example.

  At this time, the inside of the AFM apparatus is a hydrogen atmosphere, for example, a 100% hydrogen atmosphere at normal pressure, and bonds exposed at the edge of each channel are terminated by hydrogen atoms 29 due to energy generated when scratching the graphene 27 by the cantilever 14. Is done.

  Next, for example, after forming the two-layer resist pattern 15 as a lift-off mask using a contact exposure apparatus, the thickness is, for example, 100 nm Pd film 16, 10 nm Ti film 17, 200 nm A Pt film 18 is sequentially deposited.

See FIG.
Next, the source electrode 19 and the drain electrode 20 are formed by lifting off the unnecessary Pt film 18, Ti film 17, and Pd film 16 for each two-layer resist pattern 15 using an organic solvent.

  In this case, as shown in the plan view of interruption, the source electrode 19 and the drain electrode 20 are formed so as to straddle the channel array 28 composed of a plurality of channels.

  Next, the back gate 30 is formed by depositing, for example, a 10 nm Ti film 31 and a 100 nm Au film 32 on the entire back surface of the p-type silicon substrate 11 by EB vapor deposition, for example.

  Finally, the basic configuration of the back-gate graphene transistor according to the first embodiment of the present invention is completed by cutting out by dicing according to the circuit configuration that requires the completed device.

See FIG.
FIG. 7 is an explanatory diagram of the dependence of the graphene band gap on the ribbon width. The graphene band gap rapidly decreases as the ribbon width, that is, the length in the short side direction increases.
This tendency shows the same tendency as the tube diameter dependence of the band gap of the carbon nanotube shown as a reference.

Therefore, the band gap can be controlled by controlling the ribbon width of graphene with the AFM, whereby the withstand voltage of the transistor can be arbitrarily controlled.
Incidentally, the band gap of graphene having a ribbon width of about 2 nm is about 0.6 eV.

  As described above, in Example 1 of the present invention, the width and the crystal axis direction of the channel made of graphene are defined by AFM, so that graphene having semiconductor properties can be formed with good reproducibility, and the graphene The band gap can be controlled arbitrarily.

  The graphene formed in the growth process of carbon nanotubes is a huge polycrystal with a collection of graphenes having different crystal axis directions. By applying the above process to each single crystal region, the graphene transistor has good reproducibility. Can be formed.

Next, with reference to FIGS. 8 to 11, a manufacturing process of the top-gate graphene transistor according to the second embodiment of the present invention will be described.
See FIG.
First, a substrate is prepared in a state where an SOG film 12 having a thickness of, for example, 100 nm is applied to the p-type silicon substrate 11.

On the other hand, a TiN film 24 having a thickness of, for example, 5 nm and a Co film having a thickness of, for example, 1 nm are formed on the surface of a p-type silicon substrate 21 having a SiO ₂ film 22 formed on the surface by, for example, thermal oxidation. 25 are sequentially deposited to form the catalytic metal 23, and the carbon nanotubes 26 are grown to a height of, for example, 10 μm at a growth temperature of 600 ° C. by a CVD method using acetylene as a raw material under a pressure of 100 Pa.

  In this growth process, the Co film 25 melted by heat locally aggregates to become a growth nucleus of the carbon nanotube 26, and the carbon nanotube 26 grows in the vertical direction, and graphene 27 is formed on the top surface of the carbon nanotube 26. It is formed.

  Next, the p-type silicon substrate 21 on which the carbon nanotubes 26 are grown and the p-type silicon substrate 11 provided with the SOG film 12 are brought into contact with each other so that the graphene 27 and the SOG film 12 face each other. Both substrates are bonded together by curing 12 at a temperature of 300 ° C., for example.

  Next, the bonded substrates are mechanically peeled off so that the bonded carbon nanotubes 26 and the catalytic metal 23 are peeled off at the joints.

See FIG.
Next, by selectively removing the carbon nanotubes 26 by wet etching using sulfuric acid + hydrogen peroxide solution, the extraction of the graphene 27 is completed.

See FIGS. 10 and 11
Next, in the same manner as in Example 1, the extracted graphene 27 was separated by using an AFM apparatus, for example, by pressing the cantilever 14 provided in the AFM apparatus in a 100% hydrogen atmosphere at normal pressure, thereby causing scratches. The part which did not exist is made into the channel array 28 which consists of a some channel.

Also in this case, the axis is perpendicular to the zigzag direction (that is, the direction perpendicular to the diagonal line of the six-membered ring), and five six-membered rings (3n−1: n = 2), that is, about 2 nm (≈0 .4325 nm × 5).
In addition, the scratch width in this case depends on the width of the tip of the cantilever 14, but is about 10 nm, for example.

Next, for example, after forming the two-layer resist pattern 15 as a lift-off mask using a contact exposure apparatus, for example, a Pd film 16 having a thickness of, for example, 100 nm and a Ti film 17 having a thickness of 10 nm, for example, by EB vapor deposition. , 200 nm Pt film 18 is sequentially deposited.

Next, the source electrode 19 and the drain electrode 20 are formed by lifting off the Pt film 18, the Ti film 17, and the Pd film 16 that are not required for the two-layer resist pattern 15 together with an organic solvent.
Up to this point, the process is exactly the same as in the first embodiment.

  Next, an SOG film 33 used as a gate oxide film is applied to a thickness of 100 nm, for example, and then cured at 300 ° C.

Next, after applying a resist, a window pattern on the source electrode 19 and the drain electrode 20 is exposed by a contact exposure device and developed to form a resist pattern 34, and then hydrofluoric acid is used. The exposed portion of the SOG film 33 is removed by wet etching to form a contact window portion 35.

  Next, after organically removing the resist pattern 34, for example, using a contact exposure apparatus, the two-layer resist pattern 36 is formed as a lift-off mask, and then, for example, a Ti film 37 having a thickness of, for example, 10 nm by EB vapor deposition. Then, an Au film 38 of 100 nm is sequentially deposited.

Next, the Au film 38 and the Ti film 37 that are not required for each two-layer resist pattern 36 are lifted off using an organic solvent to form the gate electrode 39.
Finally, the basic configuration of the top-gate graphene transistor according to the second embodiment of the present invention is completed by cutting out by dicing according to the circuit configuration that requires the completed device.

  Thus, also in Example 2 of the present invention, the width and the crystal axis direction of the channel made of graphene are defined by AFM, so that graphene having semiconductor properties can be formed with good reproducibility, and the graphene The band gap can be controlled arbitrarily.

  Next, with reference to FIG. 13, the circuit element in which the crystal axis direction of the graphene width is controlled by the AFM will be described. However, the basic patterning process is exactly the same as in the first embodiment, so Only the configuration of the circuit elements will be described.

See FIG.
FIG. 13 is a conceptual plan view of a circuit element using graphene according to Example 3 of the present invention. First, the upper diagram is a pn junction graphene diode in which SiO ₂ is formed on one surface of graphene. A p-type graphene 41 is formed. HfO _{2 is} formed on the other surface to form a pn junction as an n-type graphene 42, and a p-side electrode 43 made of Pd is provided at an end of the p-type graphene 41. An n-type electrode 44 made of Ti is provided at the end.

  The middle diagram of FIG. 13 is an SB (Schottky barrier) graphene diode, in which an ohmic electrode 52 made of Pd / Ti / Pt is provided at one end of a non-doped graphene 51 and at the other end. A Schottky electrode 53 is provided.

  The lower diagram of FIG. 13 shows graphene wiring, and the width of the non-doped graphene 61 in the zigzag direction is 3n of 6-membered rings, for example, 6 (n = 2), that is, about 2.5 nm (≈ 0.4325 nm × 6), and each graphene 61 is connected by an ohmic electrode 62 made of Pd / Ti / Pt.

  As mentioned above, although each Example of this invention was described, this invention is not restricted to the structure described in the Example, A various change is possible, for example, in said Example 1 and Example 2 in the above-mentioned The width of graphene is set to five six-membered rings, that is, 3n-1 (n = 2), but the value of n is arbitrary, and the band gap of graphene decreases as n increases.

  Further, the width of graphene exhibiting semiconducting properties is not limited to 3n−1 six-membered rings, but may be 3n + 1 six-membered rings, for example, seven (n = 2).

  Further, in each of the above embodiments, the AFM running is performed in a 100% hydrogen atmosphere at normal pressure. However, it is not always necessary to be in a 100% hydrogen atmosphere, and hydrogen is not mixed in a rare gas mixed atmosphere. It is good to go.

  Further, in the first and second embodiments described above, the description is made as an insulated gate transistor, but in the case of the top gate transistor shown in the second embodiment, an insulating film is not interposed in the graphene channel portion. A metal material that forms a Schottky barrier with respect to graphene is directly provided as a gate electrode, whereby a Schottky barrier gate type transistor may be used.

  In the third embodiment, each circuit element is shown alone. However, each circuit element including the graphene transistor and including the graphene wiring corresponding to the required circuit configuration is provided on the same substrate. After the formation, a graphene integrated circuit device can be configured by connecting each circuit element with an ohmic electrode.

  In each of the above embodiments, the width of the graphene and the crystal direction are defined by the AFM. However, the present invention is not limited to the AFM, and may be any scanning probe microscope in a broad sense to which the AFM belongs. A narrow-sense scanning probe microscope (SPM), magnetic force microscope (MFM), electric force microscope (EFM), or the like may be used.

Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Again see Figure 1
(Supplementary note 1) By using a scanning probe microscope, while the cantilever 2 of the scanning probe microscope is used to confirm the crystal axis direction of the graphene 1, the cantilever 2 is pressed against the graphene 1 while running A method of manufacturing an electronic device using graphene, wherein a width in the extending direction of the graphene 1 and a crystal axis direction in the extending direction of the graphene 1 are simultaneously defined.
(Supplementary note 2) The graphene according to supplementary note 1, wherein the graphene 1 is a channel 3 of a transistor, and a band gap is arbitrarily controlled by a width in a direction perpendicular to an extending direction of the channel 3 of the graphene 1 Manufacturing method for electronic devices.
(Additional remark 3) The manufacturing method of the electronic device using the graphene of Additional remark 1 characterized by using the said graphene 1 as wiring.
(Supplementary Note 4) A step of defining the width of the graphene 1 in the extending direction and the crystal direction of the extending direction of the graphene 1 with a scanning probe microscope is performed in a hydrogen atmosphere, and the edge portion of the graphene 1 is terminated with hydrogen. A method for manufacturing an electronic device using the graphene according to any one of appendices 1 to 3, wherein the graphene is used.
(Additional remark 5) The said graphene 1 is the graphene 1 formed in the front-end | tip in the growth process of a carbon nanotube, The manufacturing method of the electronic device using the graphene of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned .
(Appendix 6) After the graphene 1 is transferred and fixed to the substrate 4 provided with the insulator 5 having an adhesive action by the adhesive action of the insulator 5, the width in the extending direction of the graphene 1 is measured by the scanning probe microscope. And a method of manufacturing an electronic device using the graphene according to appendix 5, wherein a crystal direction of the extending direction of the graphene 1 is defined.
(Supplementary note 7) Any one of Supplementary notes 1 to 6, wherein the scanning probe microscope is any one of a scanning probe microscope in a narrow sense, an atomic force microscope, a magnetic force microscope, or an electric force microscope. The manufacturing method of the electronic device using the graphene of description.

  As a practical example of the present invention, a field effect transistor for high frequency is typical, but it is not necessarily limited to high frequency, but by connecting a low frequency transistor or a graphene transistor in parallel. The transistor may be used as a power transistor, and further, a diode array or the like that does not include a transistor may be configured.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the back gate type graphene transistor of Example 1 of the present invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the back gate type graphene transistor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the back gate graphene transistor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the back gate graphene transistor of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 5 of the back gate graphene transistor of Example 1 of this invention. It is explanatory drawing of the ribbon width dependence of the band gap of a graphene. It is explanatory drawing of the manufacturing process to the middle of the top gate type graphene transistor of Example 2 of the present invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 8 of the top gate type graphene transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 9 or later of the top gate graphene transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 10 of the top gate type graphene transistor of Example 2 of this invention. FIG. 12 is an explanatory diagram of the manufacturing process of FIG. It is a notional top view of the circuit element using the graphene of Example 3 of the present invention.

Explanation of symbols

1 graphene 2 cantilever 3 channel 4 substrate 5 insulator 11 p-type silicon substrate 12 SOG film 14 cantilever 15 two-layer resist pattern 16 Pd film 17 Ti film 18 Pt film 19 source electrode 20 drain electrode 21 p-type silicon substrate 22 SiO ₂ film 23 catalytic metal 24 TiN film 25 Co film 26 carbon nanotube 27 graphene 28 channel array 29 hydrogen atom 30 back gate 31 Ti film 32 Au film 33 SOG film 34 resist pattern 35 window for contact 36 two-layer resist pattern 37 Ti film 38 Au Film 39 Gate electrode 41 p-type graphene 42 n-type graphene 43 p-side electrode 44 n-type electrode 51 graphene 52 ohmic electrode 53 Schottky electrode 61 graphene 62 ohmic electrode

Claims (5)

Using the scanning probe microscope, while confirming the crystal axis direction of the graphene with the cantilever of the scanning probe microscope, by running the cantilever while pressing against the graphene, the extending direction of the graphene A method of manufacturing an electronic device using graphene, wherein the width and the crystal axis direction of the graphene extending direction are simultaneously defined. 2. The method of manufacturing an electronic device using graphene according to claim 1, wherein the graphene is used as a channel of a transistor, and a band gap is arbitrarily controlled by a width in a direction perpendicular to an extending direction of the graphene channel. The method for manufacturing an electronic device using graphene according to claim 1, wherein the graphene is used as a wiring. The step of defining the width in the extending direction of the graphene and the crystal direction in the extending direction of the graphene with a scanning probe microscope is performed in a hydrogen atmosphere, and an edge portion of the graphene is terminated with hydrogen. An electronic device manufacturing method using the graphene according to any one of 3. 5. The scanning probe microscope according to claim 1, wherein the scanning probe microscope is a narrow scanning probe microscope, an atomic force microscope, a magnetic force microscope, or an electric force microscope. Of electronic device using graphene.

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