JP5181831B2 - Drive circuit, data driver, integrated circuit device, and electronic device - Google Patents

Description

  The present invention relates to a drive circuit, a data driver, an integrated circuit device, an electronic device, and the like.

  Conventionally, as a liquid crystal panel (electro-optical device, display panel) used in an electronic device such as a cellular phone, a liquid crystal panel of a simple matrix type and an active matrix type liquid crystal using a switching element such as a thin film transistor (Thin Film Transistor). The panel is known.

  In recent years, the number of data lines (source lines) of the liquid crystal panel has increased due to the increase in the screen size of the liquid crystal panel and the increase in the number of pixels, while high accuracy of the voltage applied to each data line is required. Furthermore, due to the demand for lighter and smaller battery-powered electronic devices equipped with a liquid crystal panel, it is also required to reduce the power consumption and the chip size of the drive circuit that drives the data lines of the liquid crystal panel. As a driving circuit for driving such a data line of a liquid crystal panel, there are conventional techniques disclosed in Patent Documents 1 and 2, for example.

  However, the conventional drive circuits have a problem that the output voltage of the data line varies due to the offset voltage of the operational amplifier. In order to solve such problems, for example, in the second half of the driving period, DAC driving in which the data line is directly driven by the D / A conversion circuit is employed. However, if this DAC drive is performed, there is no room in the drive period, and there is a problem that it is difficult to cope with, for example, multi-drive in which a plurality of data lines are driven by one drive circuit.

In addition, in order to drive the data lines with high accuracy, it is necessary to devise a layout method for each circuit of the drive circuit. However, Patent Documents 1 and 2 do not disclose specific examples of such a layout technique.
JP 2005-175811 A JP 2005-175812 A

  According to some embodiments of the present invention, it is possible to provide a drive circuit, a data driver, an integrated circuit device, and an electronic device that can output a highly accurate voltage while minimizing adverse effects such as parasitic capacitance.

  The present invention is a drive circuit that receives an input voltage and outputs an output voltage, the first capacitor provided between a first node and a reference node, the first node and the input voltage A first switch element provided between the input node, a second switch element provided between the first node and the analog reference power source, a second node and the reference node A second capacitor provided therebetween, a third switch element provided between the second node and the output node of the output voltage, and between the second node and the analog reference power source. A first capacitor region including the fourth capacitor, and a fifth switch device provided between the output node and the reference node, wherein the first capacitor is formed; Formed by the second capacitor The second capacitor region is disposed along the first direction, and the first and second switch elements are arranged in the first direction when the direction opposite to the first direction is the third direction. The third capacitor element is disposed on the third direction side of the second capacitor region, and the third and fourth switch elements are disposed on the first direction side of the first and second capacitor regions. When the direction orthogonal to the first direction is the second direction, the reference node line that is the reference node line is the second direction of the first, second, third, and fourth switch elements. This relates to the drive circuit wired on the side.

  According to the present invention, since the first and second switch elements are arranged on the third direction side of the first capacitor region, the first and second switches are connected to the input voltage from the preceding circuit by a short path. Can be supplied to the element. In addition, since the third and fourth switch elements are disposed on the first direction side of the second capacitor region, the connection between the subsequent circuit and the third and fourth switch elements can be realized by a short path. Therefore, the layout efficiency can be improved, and the parasitic capacitance that adversely affects the performance can be minimized. According to the invention, the reference node line is wired on the second direction side of the first to fourth switch elements. Therefore, the distance between the first and second node lines and the reference node line can be increased, and adverse effects caused by parasitic capacitance between these nodes can be minimized.

  In the present invention, a first analog reference power supply line for supplying a voltage of the analog reference power supply to the second switch element is located on the third direction side of the first and second capacitor regions. A second analog reference power supply line that is wired along a second direction and supplies the voltage of the analog reference power supply to the fourth switch element is provided in the first and second capacitor regions. Wiring may be performed along the second direction on the direction side.

  If the first and second analog reference power lines are wired in this way, the analog reference power can be supplied to the second and fourth switch elements by, for example, a short path, and the inside of the first and second analog reference lines. This area can be shielded from the outer area. Accordingly, it is possible to prevent a situation in which voltage fluctuation or the like in the outer region is transmitted to the reference node through the parasitic capacitance and adversely affects the circuit characteristics.

  In the present invention, the second, fourth, and fifth switch elements are turned on during the initialization period, and the first and third switch elements are turned on during the output period of the output voltage. May be.

  If the first to fifth switching elements are controlled in this way, after the charge is accumulated in the first and second capacitors during the initialization period, the output voltage corresponding to the input voltage is output to the output node during the output period. become able to.

  Further, the present invention includes an operational amplifier in which the reference node is connected to the first input terminal, the voltage of the analog reference power supply is set to the second input terminal, and the output voltage is output to the output node. But you can.

  If such an operational amplifier is provided, the reference node is set to the voltage of the analog reference power supply by the imaginary short function during the initialization period, and the drive target is driven using the impedance conversion function of the operational amplifier during the output period. become able to.

  In the present invention, an oscillation prevention capacitor that includes one end electrically connected to the output node and prevents oscillation of the operational amplifier may be included in the initialization period.

  In this way, for example, even when the load on the drive circuit is reduced during the initialization period, the oscillation of the operational amplifier can be prevented by electrically connecting the oscillation prevention capacitor to the output node.

  In the present invention, the fifth switch element is disposed on the second direction side of the third and fourth switch elements, and the dummy switch element of the fifth switch element is the first and second switch elements. The second switch element may be disposed on the second direction side.

  In this way, a symmetrical layout arrangement is possible, and deterioration of circuit characteristics can be prevented.

  In the present invention, one end of the auxiliary capacitor may be connected to the reference node, and the auxiliary capacitor may be formed in a capacitor region between the first and second capacitor regions.

  In this way, it is possible to suppress voltage fluctuations at the reference node, and it is possible to perform a symmetrical layout arrangement with respect to the capacitor arrangement, thereby preventing deterioration of circuit characteristics.

  Further, the present invention is a drive circuit that receives an input voltage and outputs an output voltage, one end of which is connected to the reference node, and the other end is set to the voltage of the analog reference power supply during the initialization period. In the output period, the first capacitor set to the input voltage and one end thereof are connected to the reference node, and the other end is set to the voltage of the analog reference power supply in the initialization period. Includes a second capacitor set to the output voltage, and when the direction orthogonal to the first direction is the second direction and the opposite direction of the first direction is the third direction, A reference node line, which is a reference node line, is wired along the first direction, and a first analog reference voltage for supplying the voltage of the analog reference power supply to the other end of the first capacitor. A line is wired along the second direction on the third direction side of the first and second capacitor regions to supply the voltage of the analog reference power supply to the other end of the second capacitor. The second analog reference power supply line relates to a drive circuit wired along the second direction on the first direction side of the first and second capacitor regions.

  According to the present invention, the first analog reference power supply line is wired along the second direction on the third direction side of the first and second capacitor regions, and the second analog reference power supply line is connected to the first analog reference power supply line. Since wiring is provided along the second direction on the first direction side of the first and second capacitor regions, the inner region of the first and second analog reference lines can be shielded from the outer region. Accordingly, it is possible to prevent a situation in which voltage fluctuations or the like in the outer region are transmitted to the reference node via the parasitic capacitance and adversely affect the circuit characteristics.

  According to another aspect of the invention, there is provided a data driver for driving a data line of an electro-optical device, the D / A conversion circuit receiving grayscale data and outputting a grayscale voltage corresponding to the grayscale data, and the D The present invention relates to a data driver including the drive circuit according to claim 1, which receives the grayscale voltage from a / A conversion circuit as the input voltage and outputs the output voltage to a data line.

  The present invention also relates to an integrated circuit device including the data driver described above.

  The present invention also relates to an electronic device including the integrated circuit device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Drive Circuit FIG. 1 shows a configuration example of a drive circuit according to this embodiment. Note that the drive circuit of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components (for example, operational amplifiers) or adding other components are possible. .

  The drive circuit of FIG. 1 is a circuit that receives an input voltage VIN, outputs an output voltage VQ, and drives a drive target (for example, a data line), and includes first and second capacitors C1 and C2, 5th switch element SW1-SW5 is included. An operational amplifier OP can also be included.

  The capacitor C1 is provided between the reference node NEG (negative node, inverting input terminal node, charge storage node) and the first node N1. The capacitor C2 is provided between the reference node NEG and the second node N2. Each of these capacitors C1 and C2 can be constituted by a plurality of unit capacitors, for example.

  The switch element SW1 is provided between the node N1 and the input node NI of the input voltage VIN. The switch element SW2 is provided between the node N1 and AGND (analog reference power supply in a broad sense). Switch element SW3 is provided between node N2 and output node NQ. Switch element SW4 is provided between node N2 and AGND (AGND node). Switch element SW5 is provided between reference node NEG and output node NQ.

  These switch elements SW1 to SW5 can be constituted by, for example, CMOS transistors. Specifically, it can be constituted by a transfer gate composed of a P-type transistor and an N-type transistor. These transistors are turned on / off by a switch control signal from a switch control signal generation circuit (not shown). AGND is, for example, an intermediate voltage (for example, AGND = (VDD + VSS) / 2) between the high potential side power source VDD (second power source) and the low potential side power source VSS (first power source).

  The operational amplifier OP has a reference node NEG connected to its inverting input terminal (first input terminal in a broad sense) and an AGND (analog reference power supply) connected to its non-inverting input terminal (second input terminal in a broad sense). The output voltage VQ is output to the output node NQ (output terminal).

  In the drive circuit according to the present embodiment, as shown in FIG. 1, the switch elements SW2, SW4, and SW5 are turned on in the initialization period (period in which the initialization voltage is set in C1 and C2).

  When the switch element SW2 is turned on during the initialization period, the other end of the capacitor C1 whose one end is electrically connected to the reference node NEG is set to AGND (analog reference power supply voltage VA). Similarly, when the switch element SW4 is turned on, the other end of the capacitor C2 whose one end is electrically connected to the reference node NEG is set to AGND (VA). When the switch element SW5, which is a feedback switch element, is turned on, the output of the operational amplifier OP is fed back to the inverting input terminal, and the node NEG is set to AGND by the imaginary short function of the operational amplifier OP.

  In the drive circuit of the present embodiment, as shown in FIG. 2, the switch elements SW1 and SW3 are turned on in the output period (period in which the output target is output and the drive target is driven).

  When the switch element SW1 is turned on in the output period, the other end of the capacitor C1 whose one end is connected to the reference node NEG is set to the input voltage VIN. Further, when the switch element SW3 is turned on, the other end of the capacitor C2 having one end connected to the reference node NEG is set to the output voltage VQ (output of OP).

  FIG. 3 shows an example of signal waveforms for explaining the operation of the present embodiment. In FIG. 3, VA is the voltage of AGND, for example, VA = (VDD + VSS) / 2. However, VA may be a voltage between VDD and VSS, and is not limited to (VDD + VSS) / 2.

  Since the feedback switch element SW5 is turned on in the initialization period of FIG. 1, the node NEG of the inverting input terminal of OP is at the voltage of AGND of the non-inverting input terminal by the imaginary short function of the operational amplifier OP. It becomes equal to a certain VA. However, since the operational amplifier OP has an offset due to process variations or the like, a voltage difference of the offset voltage ΔV is generated between the voltage of the node NEG and VA as shown in FIG.

  In the drive circuit of this embodiment, this offset voltage ΔV is stored in the initialization period of FIG. 1, and this offset voltage ΔV is canceled and the output voltage VQ is output in the output period of FIG. Free can be realized.

  As shown in FIG. 3, during the output period, when the input voltage VIN changes to the high potential side (VDD side), the output voltage VQ changes to the low potential side (VSS side), and when VIN changes to the low potential side. VQ changes to the high potential side.

  FIG. 4A shows the basic configuration of the drive circuit of this embodiment. As shown in FIG. 4A, one end of the driving circuit 60 of this embodiment is connected to the reference node NEG, the other end is set to the analog reference voltage VA in the initialization period, and in the output period. A capacitor C1 set to the input voltage VIN may be included. Further, it is only necessary to include a capacitor C2 having one end connected to the reference node NEG and the other end set to the analog reference voltage VA in the initialization period and set to the output voltage VQ in the output period.

  The reference node NEG (the connection node between C1 and C2) is a node that is set to a given voltage (for example, VA, VA−ΔV) in the initialization period and is set to a high impedance state (floating state) in the output period. I just need it. In order to realize such a function of the node NEG, the operational amplifier OP is used in FIGS. 1 and 2, but such a function may be realized by a circuit other than the operational amplifier OP.

  Next, the relationship between the input voltage VIN and the output voltage VQ in the drive circuit of this embodiment will be described with reference to FIGS. 4B and 4C.

  As shown in FIG. 4B, in the initialization period, VA is set at one end of the capacitors C1 and C2, and VA−ΔV is set at the other end. Here, ΔV is an offset voltage of the operational amplifier OP.

  On the other hand, as shown in FIG. 4C, in the output period, VIN is set at one end of the capacitor C1, VA−ΔV is set at the other end, VQ is set at one end of the capacitor C2, and VA−ΔV is set at the other end. Is set. Therefore, the following equation is established by the law of charge conservation.

C1 × {(VA− (VA−ΔV)} + C2 × {(VA− (VA−ΔV)}
= C1 × {VIN− (VA−ΔV)} + C2 × {VQ− (VA−ΔV)} (1)
Therefore, the following formula is established.

VQ = VA− (C1 / C2) × (VIN−VA) (2)
As apparent from the above equation (2), since the offset voltage ΔV does not appear in the output voltage VQ, so-called offset free can be realized.

  For example, as a driving circuit of a comparative example of the present embodiment, charges corresponding to the input voltage are accumulated in the sampling capacitor during the sampling period, and the sampling capacitor is subjected to a flip-around operation during the hold period. A drive circuit that outputs a corresponding voltage is conceivable.

  However, in the drive circuit of this comparative example, the output of the drive circuit is in a high impedance state during the sampling period, causing a loss in drive time.

  On the other hand, in the drive circuit of this embodiment, the output voltage VQ can be continuously output by using two capacitors C1 and C2. That is, in the output period after the initialization period, there is no sampling period, and the output voltage VQ corresponding to the input voltage VIN is output according to the above equation (2), so that the drive target can be continuously driven. Become.

2. Layout Arrangement FIG. 5 shows a layout arrangement example of the drive circuit of the present embodiment. In FIG. 5, the direction opposite to the first direction D1 is the third direction D3, the direction orthogonal (crossing) to the first direction D1 is the second direction D2, and the direction opposite to the second direction D2 Is the fourth direction D4.

  In FIG. 5, the first capacitor region C1R in which the capacitor C1 of FIGS. 1 and 2 is formed and the second capacitor region C2R in which the capacitor C2 is formed are arranged along the direction D1. A modification in which the capacitor regions C1R and C2R are arranged along the direction D2 is also possible.

  The switch elements SW1 and SW2 are arranged on the D3 direction side of the capacitor regions C1R and C2R. The switch elements SW3 and SW4 are disposed on the D1 direction side of the capacitor regions C1R and C2R. The switch element SW5 is disposed on the D2 direction side of the switch elements SW3 and SW4.

  The line LNEG of the reference node NEG is wired on the D2 direction side of the switch elements SW1, SW2, SW3, and SW4. Specifically, the line LNEG (at least a part of the wirings; the connection wiring in the upper layer of the wiring layer constituting the capacitor) is wired along the D1 direction on the D2 direction side of SW1, SW2, SW3, and SW4.

  According to the layout arrangement of FIG. 5, since the switch elements SW1 and SW2 are arranged on the D3 direction side of the capacitor region C1R, the input voltage VIN from the previous circuit is transferred to the switch elements SW1 and SW2 (capacitor C1) through a short path. Can supply. Further, since the switch elements SW3 and SW4 are arranged on the D1 direction side of the capacitor region C2R, the connection between the subsequent circuit (for example, operational amplifier) and the switch elements SW3 and SW4 (capacitor C2) can be realized by a short path. Therefore, layout efficiency can be improved, and parasitic capacitance and parasitic resistance that adversely affect performance can be minimized.

  In FIG. 5, a reference node line LNEG is wired on the D2 direction side of the switch elements SW1 to SW4. Therefore, the distance between the lines of the nodes N1 and N2 and the reference node line LNEG can be increased. Therefore, when the parasitic capacitance value between the nodes N1 and NEG is CP1, and the parasitic capacitance value between the nodes N2 and NEG is CP2, the difference value CPD between the parasitic capacitance values CP1 and CP2 is minimized. Is possible.

  That is, when the difference value CPD of the parasitic capacitance increases, C1 / C2 changes in VQ = VA− (C1 / C2) × (VIN−VA) described in the above equation (2), and the output voltage VQ varies. Resulting in. Further, when a plurality of data lines are driven by a plurality of drive circuits as will be described later, the output voltage VQ varies between the drive circuits due to process variations, resulting in a problem that display quality deteriorates.

  In this case, if the wiring shape is formed symmetrically, the adverse effect of the difference value CPD can be eliminated. However, for example, if there is a wiring portion that is not symmetrical as shown by A1 in FIG. The influence of the difference value CPD cannot be ignored.

  In this regard, in FIG. 5, since the lines of the nodes N1 and N2 and the reference node line LNEG can be separated from each other, the absolute values of the parasitic capacitance values CP1 and CP2 between the nodes N1 and N2 and NEG can be reduced. . Therefore, even if there is a portion where the symmetry is broken as shown by A1, since the absolute value of the difference value CPD is small, the adverse effect of the difference value CPD can be minimized.

  Further, in the layout arrangement of FIG. 5, when a line along the direction D2 passing between the capacitor regions C1R and C2R is used as the axis of symmetry, a layout arrangement that is line symmetric with respect to this axis of symmetry becomes possible. Therefore, adverse effects such as the difference value CPD can be further reduced.

  In FIG. 5, a first analog reference power supply line LA1 for supplying a voltage of AGND (analog reference power supply) to the switch element SW2 is wired along the D2 direction on the D3 direction side of the capacitor regions C1R and C2R. . On the other hand, a second analog reference power line LA2 for supplying the voltage AGND to the switch element SW4 is wired along the D2 direction on the D1 direction side of the capacitor regions C1R and C2R.

  If the lines LA1 and LA2 of AGND are wired as shown in FIG. 5, AGND can be supplied to the switch elements SW2 and SW4 through a short path, and the area inside the lines LA1 and LA2 can be shielded from the outside area by AGND. become. Therefore, for example, it is possible to effectively prevent a situation in which fluctuations in the input voltage VIN and output voltage at the input node NI are transmitted to the node NEG via the parasitic capacitance and adversely affect circuit characteristics. In addition, since the lines LA1 and LA2 can be line-symmetrically arranged with respect to the above-described symmetry axis, a line-symmetric layout is possible, and adverse effects such as the difference value CPD can be reduced.

  For the line LNEG of the reference node NEG, it is desirable to further wire a shield line set to the potential of AGND on the left side, the right side, the upper side or the lower side.

  FIG. 6A shows a detailed example of the layout arrangement of the capacitor regions C1R and C2R. As shown in FIG. 6A, a plurality of unit capacitors C11 to C15 constituting the capacitor C1 are arranged in the capacitor region C1R. In the capacitor region C2R, a plurality of unit capacitors C21 to C25 constituting the capacitor C2 are arranged. By using such a unit capacitor, the processing accuracy of the capacitor is increased, and the accuracy of the capacitance values of the capacitors C1 and C2 can be improved. Note that these unit capacitors can be configured by, for example, an MIM (Metal Insulation Metal) structure.

  Further, in FIG. 6A, dummy unit capacitors CD1 to CD5 are arranged on the D3 direction side of the unit capacitors C11 to C15, and dummy unit capacitors CD6 to CD10 are arranged on the D1 direction side of the unit capacitors C21 to C25.

  For example, when a plurality of driving objects are driven by a plurality of driving circuits, the plurality of driving circuits can be arranged side by side along the direction D2. Therefore, in this case, the unit capacitors of the adjacent drive circuit are also arranged on the D4 direction side and D2 direction side of the unit capacitors C11 to C15 and C21 to C25 in FIG. 6A.

  Therefore, according to the layout arrangement of FIG. 6A, it is possible to arrange other unit capacitors adjacent to each other on the four sides of each of the unit capacitors C11 to C15 and C21 to C25. Therefore, since the gap between the edge of the unit capacitor and the unit capacitor adjacent in the four directions can be formed, for example, at substantially the same etching rate, the unit capacitor can be formed with high accuracy, and the accuracy of the capacitance value is increased. Can be improved.

  Note that the layout arrangement of the present embodiment is not limited to that shown in FIG. For example, the switch elements SW1 to SW5 are arranged at locations different from FIG. 5, and the AGND line LA1 is wired along the D2 direction on the D3 direction side of the capacitor regions C1R and C2R as shown in FIG. May be laid out along the D2 direction on the D1 direction side of the capacitor regions C1R and C2R. In the inner region shielded by these AGND lines LA1 and LA2, the line LNEG of the reference node NEG is wired along the direction D1, for example.

  7 also enables a line-symmetric layout with reference to the symmetry axis passing between the above-described C1R and C2R. In addition, since the inner area can be shielded from the outer area by the AGND lines LA1 and LA2, the adverse effect of the voltage fluctuation in the outer area on the node NEG can be minimized, and the circuit characteristics can be improved. .

3. Modified Examples FIGS. 8 and 9 show modified examples of the drive circuit of this embodiment. 8 and 9, a capacitor CC for preventing oscillation is further provided as compared with FIGS. 8 and 9, a switch element SW6 for preventing the output voltage during the initialization period from being transmitted to the subsequent circuit is provided. The switch element SW6 is turned off in the initialization period of FIG. 8, and is turned on in the output period of FIG.

  Further, in FIGS. 8 and 9, an auxiliary capacitor CAX having one end connected to the reference node NEG is provided. By providing such an auxiliary capacitor CAX, it is possible to suppress the voltage fluctuation of the node NEG that is the node of the inverting input terminal of the operational amplifier OP, and to further stabilize the output voltage VQ.

  Specifically, at the moment of shifting from the initialization period of FIG. 8 to the output period of FIG. 9, the voltage of the reference node NEG varies as shown in FIG. In this case, if the auxiliary capacitor CAX is not provided, the voltage of the reference node NEG varies instantaneously by the potential difference between the node N2 and the node NQ (NQ ') at the end of the initialization period. If the voltage of the reference node NEG at this time exceeds VDD or VSS, which is the substrate voltage of the switch element SW5, the charge accumulated in the capacitors C1 and C2 is lost. In order to prevent this, an auxiliary capacitor CAX is provided in FIGS. In this way, the capacitor C2 and the capacitor CAX connected in series are provided between the nodes NQ and AGND, and the voltage fluctuation of the reference node NEG is suppressed to the range of VDD to VSS, and C1, The situation where the accumulated charge of C2 is lost can be prevented.

  For example, in this embodiment, an amplifier of a type that does not include a phase compensation capacitor is used as the operational amplifier OP. That is, since the switch element SW6 is turned on as shown in FIG. 9 during the output period, the output of the operational amplifier OP is connected to a drive target such as a data line serving as a load. Therefore, this load (for example, 20 pF) functions as a phase compensation capacitor and can prevent oscillation of the operational amplifier OP.

  However, since the switch element SW6 is turned off in the initialization period of FIG. 8, a load such as a data line is not connected to the operational amplifier OP, and the loads of the operational amplifier OP are only the capacitors C1 and C2 and the auxiliary capacitor CAX. (For example, 1 pF load). Therefore, the load on the operational amplifier OP decreases, and the operational amplifier OP may oscillate.

  Therefore, in FIG. 8 and FIG. 9, during the initialization period, one end of which is electrically connected to the output node NQ ′ is provided with an oscillation preventing capacitor CC that prevents oscillation of the operational amplifier OP. Specifically, an oscillation prevention capacitor CC and a switch element SW7 are provided between the node NQ 'and the low potential side power supply. In the initialization period of FIG. 8, the switch element SW7 is turned on and one end of the oscillation prevention capacitor CC is connected to the output node NQ ′, while in the output period of FIG. 9, the switch element SW7 is turned off and the connection is cut off. To do.

  If such an oscillation prevention capacitor CC is provided, the oscillation prevention capacitor CC functions as a phase compensation capacitor during the initialization period in which the load of the operational amplifier OP is reduced, and oscillation of the operational amplifier OP can be effectively prevented. . In FIG. 8, resistances R1 and R2 for preventing oscillation are further provided.

  FIG. 10 shows a circuit configuration example of the operational amplifier OP. The operational amplifier OP is an amplifier that performs a class AB amplification operation, and is an amplifier having a Ford forward class AB output stage. In FIG. 10, the transistors TA1 to TA4 and the current source IS1 constitute an amplifier differential stage. Further, the gates of the P-type transistor TA17 and the N-type transistor TA18 constituting the output stage are controlled by an auxiliary circuit constituted by the transistors TA7 to TA14, thereby enabling a class AB amplification operation.

  FIG. 11 shows a layout arrangement example of the drive circuit of the modification example of FIGS. In FIG. 11, for example, resistors R1 and R2 for preventing oscillation, a switch element SW7, and a capacitor CC are arranged on the D1 direction side of the switch element SW5. In FIG. 11, the capacitor regions C1R and C2R can be modified, for example, arranged along the direction D2.

  In FIG. 11, the switch element SW5 is arranged on the D2 direction side of the switch elements SW3 and SW4. A dummy switch element of the switch element SW5 (for example, a switch element having the same size and shape as SW5) is disposed on the D2 direction side of the switch elements SW1 and SW2.

  In this way, in the area inside the lines LA1 and LA2, it is possible to realize a line-symmetric layout arrangement with respect to the symmetry axis along the direction D2 passing between the capacitor areas C1R and C2R. Accordingly, the above-described parasitic capacitance difference value CPD can be further reduced to improve the circuit characteristics.

  In FIG. 11, an auxiliary capacitor CAX that is connected to the reference node NEG and suppresses fluctuations in output voltage is formed in a capacitor region CAXR between the capacitor regions C1R and C2R. In this way, efficient layout arrangement of the capacitors C1, C2, and CAX becomes possible, and a line-symmetric layout arrangement can be realized.

  For example, FIG. 6B shows a detailed example of the layout arrangement of the capacitor regions C1R, C2R, and CAXR. As shown in FIG. 6B, a plurality of auxiliary unit capacitors CA1 to CA5 constituting the auxiliary capacitor CAX are arranged in the capacitor region CAXR.

  With such a layout arrangement, the auxiliary unit capacitors CA1 to CA5 are arranged on the D1 direction side of the unit capacitors C11 to C15 constituting the capacitor C1, and the D3 direction of the unit capacitors C21 to C25 constituting the capacitor C2 is arranged. Will be placed on the side. That is, the unit capacitors C11 to C15 are arranged between the dummy unit capacitors CD1 to CD5 and the auxiliary unit capacitors CA1 to CA5, and the unit capacitors C21 to C25 are arranged between the dummy unit capacitors CD6 to CD10 and the auxiliary unit capacitors CA1 to CA5. The Therefore, the line layout of the unit capacitors can be realized with respect to the symmetry axis along the direction D2 passing between the capacitor regions C1R and C2R, so that deterioration of circuit characteristics can be prevented.

4). Integrated Circuit Device Now, a case where the drive circuit of this embodiment is applied to a data driver that drives data lines of a display panel (electro-optical device) will be described.

  For example, FIG. 12 shows a circuit configuration example of the integrated circuit device 10 (display driver) including the data driver of this embodiment. The integrated circuit device 10 according to the present embodiment is not limited to the configuration shown in FIG. 12, and various modifications such as omitting some of the components or adding other components are possible.

  The display panel 400 (electro-optical device in a broad sense) includes a plurality of data lines (for example, source lines), a plurality of scanning lines (for example, gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel can be constituted by an active matrix type panel using switch elements such as TFT and TFD. The display panel may be a panel other than the active matrix system, or a panel other than the liquid crystal panel (organic EL panel or the like).

  The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22.

  The logic circuit 40 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 110, or the power supply voltage is supplied to the power supply circuit 90. Outputs power adjustment data for adjustment. Further, it controls the write / read processing to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28.

  The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 to the display panel side. The host (MPU) interface circuit 46 implements a host interface that accesses the memory 20 by generating an internal pulse for each access from the host. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to the memory 20 using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  The data driver 50 is a circuit that generates a data signal for driving the data lines of the display panel. Specifically, the data driver 50 receives image data (grayscale data, display data) from the memory 20, and receives a plurality of (for example, 256 levels) grayscale voltages (reference voltages) from the grayscale voltage generation circuit 110. Then, a voltage (data voltage) corresponding to the image data (gradation data) is selected from the plurality of gradation voltages and is output to the data line of the display panel.

  The scan driver 70 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output as a scanning signal (scanning voltage) to each scanning line of the display panel. . The scan driver 70 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 90 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the data driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like.

  The gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage and supplies it to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit that divides a resistance between a high potential side voltage and a low potential side voltage and outputs a gradation voltage to a resistance dividing node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

5. Data Driver FIG. 13 shows a configuration example of the data driver (source driver) of the present embodiment. This data driver drives a data line of a display panel 400 (electro-optical device) such as a liquid crystal panel, and includes a D / A conversion circuit 52 and a drive circuit 60. A drive circuit 60 or the like may be provided for each data line of the display panel 400, or the drive circuit 60 may drive a plurality of data lines in a time division manner (multi-drive). A part or all of the data driver (integrated circuit device) may be integrally formed on the display panel 400.

  The D / A conversion circuit 52 (voltage generation circuit) receives gradation data (image data, display data) from the memory 20 of FIG. 12, for example. Then, VIN which is a gradation voltage corresponding to the gradation data is output.

  Specifically, the D / A conversion circuit 52 receives a plurality of gradation voltages from the gradation voltage generation circuit 110 of FIG. A voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output as VIN.

  The drive circuit 60 receives an input voltage VIN that is a gradation voltage from the D / A conversion circuit 52. The output voltage VQ is output to drive the data line of the display panel 400. As the drive circuit 60, the drive circuit having the configuration described in FIG. 1, FIG. 2, FIG. 8, FIG.

  FIG. 14 is an explanatory diagram of the operation of the data driver of this embodiment. In FIG. 14, the VCOM stable period at the beginning of the horizontal scanning period (1H) is set to the initialization period described with reference to FIGS. After this initialization period, the drive circuit 60 multi-drives a plurality of data lines in a time division manner.

  Here, the VCOM stabilization period is a period until the common voltage VCOM (counter electrode voltage) supplied to the counter electrode of the pixel is stabilized. For example, in line inversion driving, the polarity of the voltage applied to the liquid crystal element is inverted every scanning period. For this purpose, the common voltage VCOM (VCOMH) for positive polarity and the common voltage VCOM (VCOML) for negative polarity are switched and output to the counter electrode every scanning period. A period necessary for stabilizing the fluctuation due to the polarity inversion of the VCOM is a VCOM stable period.

  In this VCOM stable period, proper driving cannot be realized even if a voltage is supplied to the data line. Therefore, in FIG. 14, the drive circuit is initialized by effectively using the VCOM stabilization period. After the VCOM is stabilized, the data line is multi-driven by switching from the initialization period to the output period. In this way, efficient data line driving is possible.

  In this VCOM stable period, for example, the data line may be set to the common voltage VCOM (common potential). In this way, charges accumulated in the display panel 400 are reused to charge and discharge the data lines of the display panel 400, so that power consumption can be reduced.

  FIG. 15 shows a configuration example of the D / A conversion circuit 52. The D / A conversion circuit 52 of FIG. 15 includes a plurality of selector blocks BL1 and BL2 in which the output of the selector included in the preceding selector block is input to the selector included in the succeeding selector block. The number of selector blocks is not limited to two as shown in FIG. 15, but may be three or more.

  In the D / A conversion circuit 52 of FIG. 15, one gradation voltage is selected from a plurality of gradation voltages by a so-called tournament method, and is output as a gradation voltage VG (VIN). For example, the selector block at the first stage is composed of 4-input selectors S10 to S13, and the gradation voltages V0 to V15 generated by the gradation voltage generation circuit 110 of FIG. Entered. The second-stage selector block is constituted by a 4-input selector S21, and the output voltages of the preceding 4-input selectors S10 to S13 are input to the 4-input selector S21. Then, the 4-input selector S21 outputs the selected gradation voltage VG (VIN). In this case, the selectors S10 to S13 are controlled by selector control signals EN1 [3] to EN1 [0] generated based on the gradation data. The selector S21 is controlled by selector control signals EN2 [3] to EN2 [0] generated based on the gradation data.

  Although FIG. 15 shows an example in the case of 16 gradations (V0 to V15), the number of gradations is not limited to this, and may be 64, 128, 256 gradations, for example.

6). Electronic Device FIGS. 16A and 16B show a configuration example of an electronic device (electro-optical device) including the integrated circuit device 10 of the present embodiment. Note that various modifications may be made such as omitting some of the components shown in FIGS. 16A and 16B and adding other components (such as a camera, an operation unit, or a power supply). . The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  In FIGS. 16A and 16B, the host device 410 is, for example, an MPU or a baseband engine. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, the image processing controller 420 in FIG. 16B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 16A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 16B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (display panel, inversion) described at least once together with different terms (electro-optical device, first input terminal, second input terminal, analog reference power source, etc.) having a broader meaning or the same meaning Input terminal, non-inverting input terminal, AGND, and the like) can be replaced with the different terms in any part of the specification or the drawings. Further, the configuration and operation of the drive circuit, data driver, D / A conversion circuit, integrated circuit device, electronic device, and the like are not limited to those described in this embodiment, and various modifications can be made. Further, the drive target of the drive circuit of the present embodiment is not limited to the data line.

2 is a configuration example of a drive circuit according to the present embodiment. 2 is a configuration example of a drive circuit according to the present embodiment. 7 is a signal waveform example for explaining the operation of the drive circuit. 4A and 4B are principle configuration diagrams of the drive circuit of the present embodiment. An example of layout arrangement of a drive circuit. 6A and 6B show layout arrangement examples of the capacitor region. An example of layout arrangement of a drive circuit. The modification of the drive circuit of this embodiment. The modification of the drive circuit of this embodiment. An example of the configuration of an operational amplifier. The layout arrangement example of the drive circuit of a modification. 1 is a configuration example of an integrated circuit device according to an embodiment. 2 is a configuration example of a data driver according to the present embodiment. FIG. 6 is an operation explanatory diagram of the data driver. 2 shows a configuration example of a D / A conversion circuit. FIG. 16A and FIG. 16B are configuration examples of electronic devices.

Explanation of symbols

SW1 to SW7, first to seventh switch elements, C1, C2, first and second capacitors,
OP operational amplifier, C1R, C2R first and second capacitor regions,
CC oscillation prevention capacitor, CAX auxiliary capacitor,
10 integrated circuit device, 20 memory, 22 memory cell array,
24 row address decoder, 26 column address decoder,
28 write / read circuit, 40 logic circuit, 42 control circuit,
44 display timing control circuit, 46 host interface circuit,
48 RGB interface circuit, 50 data driver,
52 D / A conversion circuit, 60 drive circuit, 70 scan driver,
90 power supply circuit, 110 gradation voltage generation circuit, 400 display panel,
410 Host device, 420 Image processing controller

Claims (9)

A drive circuit that receives an input voltage and outputs an output voltage,
A first capacitor provided between the first node and the reference node;
A first switch element provided between the first node and an input node of the input voltage;
A second switch element provided between the first node and an analog reference power supply;
A second capacitor provided between a second node and the reference node;
An operational amplifier for connecting the reference node to the first input terminal, setting the voltage of the analog reference power supply to the second input terminal, and outputting the output voltage;
A third switch element provided between the second node and an output node of the operational amplifier ;
A fourth switch element provided between the second node and the analog reference power supply;
A fifth switch element provided between the output node of the operational amplifier and the reference node ;
Including
In the initialization period, the second, fourth, and fifth switch elements are turned on, and the first and third switch elements are turned off,
In the output period of the output voltage, the first and third switch elements are turned on, the second, fourth, and fifth elements are turned off, and the reference node is set to a high impedance state,
A first capacitor region in which the first capacitor is formed and a second capacitor region in which the second capacitor is formed are disposed along a first direction;
When the direction opposite to the first direction is the third direction, the first and second switch elements are disposed on the third direction side of the first and second capacitor regions,
The third and fourth switch elements are disposed on the first direction side of the first and second capacitor regions;
When the direction orthogonal to the first direction is the second direction, the reference node line that is the reference node line is the second of the first, second, third, and fourth switch elements. A drive circuit characterized by being wired on the direction side. In claim 1,
A first analog reference power supply line for supplying a voltage of the analog reference power supply to the second switch element is in the second direction on the third direction side of the first and second capacitor regions. Routed along,
A second analog reference power supply line for supplying a voltage of the analog reference power supply to the fourth switch element is in the second direction on the first direction side of the first and second capacitor regions. A drive circuit characterized by being wired along. In claim 1 or 2 ,
A drive circuit comprising an oscillation prevention capacitor, one end of which is electrically connected to the output node during an initialization period, and prevents oscillation of the operational amplifier. In any one of Claims 1 thru | or 3 ,
The fifth switch element is disposed on the second direction side of the third and fourth switch elements;
A drive circuit, wherein the dummy switch element of the fifth switch element is disposed on the second direction side of the first and second switch elements. In any one of Claims 1 thru | or 4 ,
One end of which includes an auxiliary capacitor connected to the reference node;
The drive circuit, wherein the auxiliary capacitor is formed in a capacitor region between the first and second capacitor regions. A drive circuit that receives an input voltage and outputs an output voltage,
A first capacitor provided between the first node and the reference node ;
A first switch element provided between the first node and an input node of the input voltage;
A second switch element provided between the first node and an analog reference power supply;
A second capacitor provided between a second node and the reference node ;
An operational amplifier for connecting the reference node to the first input terminal, setting the voltage of the analog reference power supply to the second input terminal, and outputting the output voltage;
A third switch element provided between the second node and an output node of the operational amplifier;
A fourth switch element provided between the second node and the analog reference power supply;
A fifth switch element provided between the output node of the operational amplifier and the reference node;
Including
In the initialization period, the second, fourth, and fifth switch elements are turned on, and the first and third switch elements are turned off,
In the output period of the output voltage, the first and third switch elements are turned on, the second, fourth, and fifth elements are turned off, and the reference node is set to a high impedance state,
When a direction orthogonal to the first direction is a second direction and a direction opposite to the first direction is a third direction, a reference node line that is a line of the reference node is in the first direction. Routed along,
A first analog reference power supply line for supplying a voltage of the analog reference power supply to the second switch element is in the second direction on the third direction side of the first and second capacitor regions. Routed along,
A second analog reference power supply line for supplying a voltage of the analog reference power supply to the fourth switch element is in the second direction on the first direction side of the first and second capacitor regions. A drive circuit characterized by being wired along. A data driver for driving a data line of an electro-optical device,
A D / A conversion circuit which receives gradation data and outputs a gradation voltage corresponding to the gradation data;
A drive circuit according to any one of claims 1 to 6 subjected to the gradation voltage from the D / A converter circuit as the input voltage, and outputs the output voltage to the data line,
A data driver comprising: An integrated circuit device comprising the data driver according to claim 7 . An electronic apparatus comprising the integrated circuit device according to claim 8 .

Images