JP5176217B2 - Active matrix liquid crystal display device - Google Patents

Description

The present invention relates to an active matrix liquid crystal display device including an active matrix substrate in which pixel electrodes and thin film transistors (hereinafter abbreviated as TFTs) are arranged on a transparent substrate, and more particularly to an electrode structure thereof.

  An active matrix liquid crystal display device includes an active matrix substrate including pixel electrodes arranged in a matrix and TFTs provided corresponding to the pixel electrodes in order to control a voltage applied to the pixel electrodes. A liquid crystal is sandwiched between the active matrix substrate and the counter substrate, and the liquid crystal is driven with a voltage applied between the electrodes to perform display. For example, in the case of a vertical electric field type liquid crystal display device that forms an electric field in a direction perpendicular to the substrate, the active matrix substrate includes a plurality of scanning lines extending in the X direction on the surface of a transparent glass substrate in the Y direction. Arrange at the required intervals. In addition, a plurality of signal lines extending in the Y direction so as to be orthogonal to this are arranged in the X direction at a required interval. A pixel electrode composed of a transparent electrode is disposed in a region surrounded by the scanning line and the signal line, and a TFT is disposed corresponding to each pixel electrode. The TFT has a gate electrode connected to the scanning line, a drain electrode connected to the signal line, and a source electrode connected to the pixel electrode. Accordingly, when a required current flows through each of the scanning line and the signal line, the TFT at the position where the scanning line and the signal line intersect is turned on, and the required potential is supplied to the pixel electrode. Will be displayed. A scanning line terminal portion is provided at an end portion of the scanning line, a signal line terminal portion is provided at an end portion of the signal line, and a driving circuit is provided in the scanning line terminal portion and the signal line terminal portion. The tape-like wiring connected to (driver) is connected.

  In such an active matrix substrate, along with the demand for larger and higher density liquid crystal display devices, the dimensions of the pixel electrodes are reduced, and the scanning lines, signal lines, and common lines are made of a material and structure having low electrical resistance. It is required to configure. On the other hand, the end portions of the scanning lines, signal lines, and common lines need to be connected to the tape-like wiring of the driving circuit (not shown) as scanning line terminal portions, signal line terminal portions, and common line terminal portions. Therefore, these terminal portions need to be made of a material having high connection reliability so that the reliability of the connection portion does not deteriorate due to the ingress of moisture.

  From such a demand, for example, Patent Document 1 proposes a multilayer wiring structure including a lower layer aluminum (Al) and an upper layer titanium nitride film (TiN). In the wiring structure described in Patent Document 1, lower resistance is achieved by the lower aluminum layer, and the upper titanium nitride film can prevent the aluminum from being corroded by being exposed to a chemical solution or the like during the process, and has high reliability. A connection structure can be obtained. However, in such a wiring structure composed of a laminate of aluminum and a titanium nitride film, Al hillocks are likely to occur in aluminum during the thermal process in the process. As is well known, Al hillocks are protrusions generated on the surface of aluminum, and are generated when aluminum is subjected to compressive stress by heat treatment, and aluminum atoms diffuse to relax the stress. The generation of Al hillocks increases defects such as interlayer shorts, and causes a decrease in yield.

  As a technique for preventing Al hillock, there is a technique described in Patent Document 2, for example. The technique described in Patent Document 2 uses a TiN / Ti / Al / TiON / Ti structure film as a multilayer structure of wiring. The uppermost TiN film has anti-reflection and etching selectivity at the time of contact formation. The upper Ti film is used as a connection resistance reducing film, the Al film is used as a wiring material film, TiON is used as a diffusion barrier film for silicon, and the lower layer. The Ti film is formed as a connection resistance reducing film.

JP-A-7-120789 Japanese Patent Laid-Open No. 7-58110

  The technique described in Patent Document 2 prevents the generation of Al hillocks and alloy pits by sandwiching an Al film between a TiN film provided in an upper layer and a TiON film provided in a lower layer. However, Patent Document 2 only describes that the TiN / Ti / Al / TiON / Ti structure described above is effective, and it is effective to prevent Al hillocks in other multilayer structures. Is not specifically described. Therefore, when the wiring is not formed in contact with the semiconductor layer, for example, when the wiring structure is directly formed on the insulating substrate like the gate electrode of the liquid crystal display device to which the present invention is applied, Patent Document 2 It is not clear whether the multilayer structure described in 1 is effective. In particular, the lower TiON film functions as a diffusion barrier film for silicon. However, when the diffusion barrier film is not required like an insulating substrate, the TiON film unnecessarily complicates the wiring structure. It becomes a factor. Further, within the range described in Patent Document 2, it is clear that the combined structures of the upper TiN film and Ti film of the Al film and the lower TiON film and Ti film are effective, but one of these films is effective. If the part is omitted, it is not clear whether the disclosed effects can be expected.

  An object of the present invention is to provide an active matrix liquid crystal display device in which the Al hillock is suppressed and the connection resistance is reduced by improving the reliability of the connection portion without complicating the structure of each wiring. .

The present invention provides an active matrix type liquid crystal display device including an active matrix substrate in which a thin film transistor and a pixel electrode are formed on a transparent insulating substrate, wherein the gate electrode of the thin film transistor and the scanning line connected thereto are formed on an upper layer of an aluminum film. A multilayer wiring in which a titanium film is formed on at least one of the lower layer and a titanium nitride film on the uppermost layer, and a transparent conductive film in contact with the titanium nitride film is not formed on the upper side of the scanning line The titanium nitride film is exposed at the terminal portion of the scanning line, and the titanium nitride film has a nitrogen concentration of 25 atomic% or more. In addition, the source electrode and drain electrode of the thin film transistor and the signal line connected thereto are multilayers in which a titanium film is formed in the lower layer of the aluminum film, or both the upper layer and the lower layer, and a titanium nitride film is formed in the uppermost layer. A transparent conductive film in contact with the titanium nitride film is not formed on the upper layer side of the signal line, the titanium nitride film is exposed at a terminal portion of the signal line, and the titanium nitride The film is characterized by a nitrogen concentration of 25 atomic% or more. In the present invention, a thin film transistor is formed with a gate electrode, a gate insulating film formed to cover the gate electrode, an island-shaped semiconductor layer formed on the gate insulating film, and a channel gap on the semiconductor layer. It is preferably configured as an inverted staggered thin film transistor including a source electrode and a drain electrode. Further, a part of the multilayer wiring structure film of the scanning line and the signal line is, for example, a TiN / Ti / Al structure film. Alternatively, a TiN / Al / Ti structure film is used. Furthermore, a TiN / Ti / Al / Ti structure film is used. Al is Al or Al alloy.

  According to the active matrix liquid crystal display device of the present invention, the scanning line or the signal line is in contact with the Al film and the Ti film is present, so that the generation of Al hillocks in the Al film is suppressed. Regarding the drain layer, the presence of a Ti film between the Al film and the semiconductor film suppresses the generation of alloy pits. In addition, there is a TiN film in the uppermost layer, and a transparent conductive film is not formed on the upper layer of the TiN film in contact with the TiN film, the TiN film is exposed at the terminal portion, and the nitrogen concentration of the TiN film Is 25 atomic% or more, it is possible to suppress corrosion at each connection portion of the scanning line and the signal line, to reduce the connection resistance at the connection portion, and to improve its reliability.

1 is a schematic configuration diagram of an active matrix substrate according to a first embodiment of the present invention. FIG. 2 is a plan layout view of one pixel region and a connection portion of the active matrix substrate of FIG. The figure similar to FIG. 2 which shows the manufacturing process 1 of 1st Embodiment. The figure similar to FIG. 2 which shows the manufacturing process 2 of 1st Embodiment. The figure similar to FIG. 2 which shows the manufacturing process 3 of 1st Embodiment. The figure similar to FIG. 2 which shows the manufacturing process 4 of 1st Embodiment. The figure which shows the correlation of a multilayer wiring structure and the number of Al hillocks. The figure which shows the correlation with the nitrogen content% of TiN, and resistance increase amount. The figure which shows the test method of the connection resistance of a terminal part, and the state which connection resistance increased. The schematic block diagram of the active matrix substrate concerning the 2nd Embodiment of this invention. FIG. 11 is a plan layout view of one pixel region and connection portion of the active matrix substrate of FIG. 10 and enlarged sectional views of AA, BB, CC, and DD lines thereof. The figure similar to FIG. 11 which shows the manufacturing process 1 of 2nd Embodiment. The figure similar to FIG. 11 which shows the manufacturing process 2 of 2nd Embodiment. The figure similar to FIG. 11 which shows the manufacturing process 3 of 2nd Embodiment. The figure similar to FIG. 11 which shows the manufacturing process 4 of 2nd Embodiment.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view of a first embodiment in which an active matrix type liquid crystal display device of the present invention is applied to a vertical electric field type active matrix substrate. FIG. 2 shows one of the pixel regions. FIG. 2A is a plan layout view, and FIGS. 2B to 2D are cross-sectional views taken along lines AA, BB, and CC. is there. Referring to FIGS. 1 and 2, a plurality of scanning lines 11 extending in the X direction are disposed on the transparent insulating substrate 10 at a predetermined interval in the Y direction, and are orthogonal to the scanning lines 11. A plurality of signal lines 12 extended in the Y direction are arranged at a required interval in the X direction. A pixel portion 13 and a TFT 14 are formed in a region surrounded by the scanning line 11 and the signal line 12. The TFT 14 includes a gate electrode 15 formed on the surface of the transparent glass substrate 10 in the same layer as the scanning line 11, a gate insulating film 16 formed so as to cover the scanning line 11 and the gate electrode 15, An island-shaped semiconductor layer 17 formed on the gate insulating film 16 so as to face the gate electrode, and a pair of sources formed on the semiconductor layer 17 and formed in the same layer as the signal line 12 An inverted staggered TFT comprising an electrode 18 and a drain electrode 19 is configured. Further, a passivation film 20 is formed thereon.

  The pixel unit 13 includes a pixel electrode 21 made of a transparent electrode such as ITO formed on the gate insulating film 16. Most of the pixel electrode 21 is exposed in an opening 21a as a display window formed in the passivation film 20, and this exposed region is configured as a display region. The gate electrode 15 is connected to the scanning line 11, the drain electrode 19 is connected to the signal line 12, and the source electrode 18 is connected to the pixel electrode 21. Further, the scanning line terminal portion 22 provided at the end portion of the scanning line 11 is configured such that the end portion of the scanning line 11 is exposed in the opening 22a formed in the gate insulating film 16 and the passivation film 20. The Similarly, the signal line terminal portion 23 provided at the end portion of the signal line 12 is configured such that the end portion of the signal line is exposed in the opening 23 a formed in the passivation film 20.

  Here, the gate electrode 15 and the scanning line 11 are formed as an integral multilayer wiring structure. In the first embodiment, the lower Al film 101, the upper Ti film 102, and the uppermost TiN film. 103, a TiN / Ti / Al structure film. The TiN film 103 is formed to a thickness of 100 nm, the Ti film 102 is formed to a thickness of 50 nm, and the Al film 101 is formed to a thickness of 200 nm. The source electrode 18, the drain electrode 19, and the signal line 12 are configured as the same multilayer wiring structure. In this embodiment, a Cr / ITO structure film composed of a lower ITO film 111 and an upper Cr film 112 is used. Has been. Here, the transparent electrode, that is, the signal line 11 formed of the same layer as the ITO film 111 is present on the upper part of the scanning line 11, but the ITO film 111 is interposed, so that the ITO The film 111 is not in contact with the uppermost TiN film 103 of the scanning line 11. In the pixel electrode 21 and the signal line terminal portion 23, the upper layer Cr film 112 is partially removed, and only the lower layer ITO film 111 is formed. As a result, the pixel electrode 21 has transparency, and the signal electrode In the line terminal portion 23, reliability of electrical connection is ensured. The ITO film 111 is formed to a thickness of 50 nm, and the Cr film 112 is formed to a thickness of 200 nm.

  3 to 6 are views similar to FIG. 2 in the main steps. First, as shown in FIG. 3, a TiN / Ti / Al structure film in which an Al film 101, a Ti film 102, and a TiN film 103 are sequentially laminated is formed on a transparent insulating substrate 10 such as glass by a sputtering method. As described above, the film thickness is TiN / Ti / Al = 100 nm / 50 nm / 200 nm. In the first PR (photoresist) step, a first photoresist film having a required pattern is formed on the TiN / Ti / Al structure film, exposed and developed, and then the first photoresist is used as a mask. Then, the TiN / Ti / Al structure film is dry etched to form the gate electrode 15 and the scanning line 11.

Here, the TiN film 103 is formed by a reactive sputtering method, the flow rate ratio of Ar gas and N gas is adjusted, and nitrogen is contained at 25 atomic% or more. For example, a TiN film containing 25 atomic% or more of nitrogen is performed under the conditions of pressure 0.8 Pa, Ar gas flow rate 225 sccm, N ₂ gas flow rate 150 sccm, DC discharge power 16 kW, substrate temperature 150 ° C., gap 115 mm. 103 can be formed.

Next, as shown in FIG. 4, a SiN film is formed as a gate insulating film 16 on the entire surface to a thickness of 400 nm. An intrinsic a-Si film 121 having a thickness of 250 nm is formed thereon, and an n ⁺ -type a-Si film 122 containing phosphorus as an ohmic layer is formed thereon by a plasma CVD method to a thickness of 50 nm. Then, in the second PR step, a second photoresist film is formed in a required pattern, exposed and developed, and then the n ⁺ -type a-Si film 121 and the intrinsic a− are formed using the second photoresist as a mask. The Si film 122 is sequentially dry etched to form an island-shaped semiconductor layer 17 directly above the gate electrode 15 with the gate insulating film 16 interposed therebetween.

  Next, as shown in FIG. 5, an ITO film 111 as a transparent electrode shown in FIG. 2 is formed to a thickness of 50 nm on the entire surface, and a Cr film 112 is further formed thereon to a thickness of 200 nm by sputtering. Then, a third photoresist film is formed in a required pattern, exposed and developed, and then the Cr film 112 and the ITO film 111 are wet-etched to form the pixel electrode 21 and the source electrode 18 integrated with the pixel electrode 21. The drain electrode 19 and the signal line 12 integral with the drain electrode 19 are formed.

Then, the n ⁺ type a-Si film 122 is dry-etched using the source electrode 18 and the drain electrode 19 as a mask. By this etching, in the semiconductor layer 17, the n ⁺ -type a-Si film 122 between the drain electrode 19 and the source electrode 18 is etched to form a channel gap, and the drain electrode 19 and the source electrode 18 An ohmic layer of the n ⁺ type a-Si film 122 is formed immediately below. Thereby, the TFT 14 is formed.

  Next, as shown in FIG. 6, a SiN film is formed as a passivation film 20 on the entire surface by plasma CVD. Then, by the fourth PR, the respective passivation films 20 of the pixel electrode 21, the scanning line terminal portion 22, and the signal line terminal portion 23 are selectively removed to form openings 21a, 22a, and 23a. Further, the gate insulating film 16 is removed when the opening 22a is formed in the scanning line terminal portion 22. As a result, as shown in FIG. 2, in the scanning line terminal portion 22, the end portion of the scanning line 11 is exposed in the opening 22 a of the passivation film 20 and the gate insulating film 16, thereby forming the scanning line terminal portion 22. In the pixel portion 13 and the signal line terminal portion 23, the Cr film 112 exposed in the openings 21a and 23a of the passivation film 20 is removed, and the underlying ITO film 111 is exposed. Thereby, the pixel portion 13 and the signal line terminal portion 23 are formed.

  Accordingly, although not shown in the drawings, an alignment film is formed on the passivation film 20 in the pixel array region arranged in a matrix, thereby completing the active matrix substrate. Further, an active matrix liquid crystal display device is completed by disposing a counter substrate on the active matrix substrate at a predetermined interval and sealing the interval between them to fill the liquid crystal. Further, by connecting the tape-like terminal of the drive circuit to the scanning line terminal portion 22 and the signal line terminal portion 23 arranged in the peripheral portion of the active matrix substrate 10, power can be supplied to the active matrix liquid crystal display device. It becomes possible and a liquid crystal display becomes possible.

  As described above, in the first embodiment of the present invention, since the TiN / Ti / Al structure film is used as the multilayer wiring constituting the gate electrode 15 and the scanning line 11, the effect of suppressing the generation of Al hillocks. Is increased. FIG. 7 is an example in which the number of Al hillocks generated in the conventional TiN / Al structure film described in Patent Document 1 and the TiN / Ti / Al structure film of the present invention are compared. Here, the number of Al hillocks observed visually within a wiring area of 1 mm square after each multilayer wiring is formed and then heat-treated at 300 ° C. for 1 hour in a nitrogen gas atmosphere is shown. In the structure described in the first publication, 6410 Al hillocks are confirmed per 1 mm square, but in the present embodiment, only 1 to 26 Al hillocks are confirmed. The figure also shows the number of Al hillocks when the thicknesses of the TiN / Ti / Al structure films are different. As described above, in the first embodiment, by using the TiN / Ti / Al structure film as the scanning line, the generation of Al hillocks in the scanning line can be extremely effectively suppressed. This is presumed to be because, when Ti is formed between TiN and Al, the physical hillock suppression effect, which is insufficient with TiN, is improved. Here, it can be seen that the effect of suppressing Al hillocks can be enhanced by increasing the thickness of the TiN film. It can also be seen that the effect of suppressing Al hillocks can be enhanced even if the thickness of the Ti film is increased.

  In the TiN / Ti / Al structure film, the uppermost TiN layer improves the reliability of electrical connection at the scanning line terminal portion. That is, FIG. 8 is a diagram showing a difference in connection resistance at the scanning line terminal portion when the nitrogen content% of the TiN film is different in a scanning line made of a TiN / Ti / Al structure film. The connection resistance of the scanning line terminal portion 22 is shown in FIG. 9A as a schematic wiring configuration diagram, and as shown in FIG. 9B as a sectional view along the EE line, A test terminal TEG in which a plurality of, for example, 2000, dummy scanning line terminal portions 22 in the same standard are arranged is formed, and a tape-like terminal TCP is connected to each dummy scanning line terminal portion 22 of the test terminal TEG. To do. Here, the connected length TL is defined as a terminal connection length. The test terminals TEG are formed with different nitrogen content percentages of the TiN film. Here, three types having 15%, 25%, and 35% nitrogen content were formed. The tape-shaped terminal TCP is formed according to the same standard as the tape-shaped terminal used when the active matrix substrate is actually connected to the drive circuit. Then, the test terminal TEG and the tape-like terminal TCP are connected in series as shown in FIG. 9A by the metal bonding material MB, and the resistances at both ends thereof are measured.

  In this state, a change in resistance value is measured when heat treatment is performed at a temperature of 85 ° C. and a humidity of 85% for 1000 hours. By this heat treatment, as shown in FIG. 9C, the defective connection portion advances from the periphery of the opening in the scanning line terminal portion 22, so that the terminal connection length described above is shortened, and the dummy scanning line terminal portion 22 Resistance value increases. Here, the resistance increase amount (arb.unit) when the allowable terminal connection length TL at the dummy scanning line terminal portion 22 is 0.1 mm is “2”, and those that do not exceed “2” are non-defective products. To do. The resistance values after the heat treatment at the three types of test terminals TEG are as plotted in FIG. 8, and when these are connected by continuous lines, they become as indicated by the broken lines in the figure. When the nitrogen content% at which the resistance increase amount is “2” or less is determined, if the nitrogen content% is 25% or more, the resistance increase amount can be suppressed to “2” or less including variation. That is, by setting the nitrogen content% of the TiN film to 25% or more, it is possible to configure a highly reliable scanning line connection portion with little increase in connection resistance against corrosion. Further, since the ITO film 111 which is the upper transparent electrode film is not in contact with the uppermost TiN film 103 of the scanning line 11, the TiN film 103 is not damaged when the ITO film 111 is etched. Can be secured.

  Next, a second embodiment of the present invention will be described. In the second embodiment, the present invention is applied to a lateral electric field type active matrix substrate. FIG. 10 is a schematic configuration diagram of the active matrix substrate, FIG. 11 shows one pixel region, FIG. 10A is a plan layout diagram, FIGS. 10B to 10E are AA lines, BB lines, and CC lines. FIG. 4 is a sectional view taken along line DD. In addition, the same code | symbol is attached | subjected to the part equivalent to 1st Embodiment. Referring to FIGS. 10 and 11, in the active matrix substrate 1A of the second embodiment, a plurality of scanning lines 11 extended in the X direction are arranged on the transparent insulating substrate 10 at a required interval in the Y direction. In addition, a common line 30 extending in the X direction is disposed between the Y directions of the scanning lines 11. On the other hand, a plurality of signal lines 12 extended in the Y direction so as to be orthogonal to the scanning lines 11 and the common line 30 are arranged at a predetermined interval in the X direction. As shown in FIG. 10, a pixel portion 13 is formed in a region surrounded by the scanning line 11, the common line 30 and the signal line 12, and a TFT 14 is formed adjacent to the pixel portion 13. The TFT 14 is the same as that of the first embodiment. The TFT 14 is formed on the surface of the transparent glass substrate 10. The gate electrode 15 is formed in the same layer as the scanning line 11 and the common line 30. A gate insulating film 16 formed so as to cover the scanning line 11 and the common line 30, an island-shaped semiconductor layer 17 formed on the gate insulating film 16 so as to face the gate electrode 15, and the semiconductor A source electrode 18 and a drain electrode 19 are formed on the layer 17 and form a pair formed in the same layer as the signal line 12. Further, a passivation film 20 is formed thereon.

  Further, the pixel portion 13 is formed in the same layer as the comb-shaped or frame-shaped common electrode 32 formed in the same layer as the gate electrode 13 and the source electrode 18 formed in the upper layer of the gate insulating film 16. Thus, the common electrode 32 is composed of a comb-like or frame-like pixel electrode 33 formed with a pitch shifted. The gate electrode 15 is connected to the scanning line 11, the drain electrode 19 is connected to the signal line 12, the source electrode 18 is connected to the pixel electrode 33, and the common electrode 32 is connected to the common line 30. Further, the scanning line terminal portion 22 provided at the end portion of the scanning line 11 is configured such that the end portion of the scanning line 11 is exposed in the opening 22a formed in the gate insulating film 16 and the passivation film 20. The Similarly, the signal line terminal portion 23 provided at the end portion of the signal line 12 is configured such that the end portion of the signal line 12 is exposed in the opening 23 a formed in the passivation film 20. Further, the common line terminal portion 31 provided at the end portion of the common line 30 is configured such that the end portion of the common line 30 is exposed in the opening 31a formed in the gate insulating film 16 and the passivation film 20. The

  Here, the gate electrode 15 and the scanning line 11, and the common electrode 32 and the common line 30 are each configured as a multilayer wiring structure. In this embodiment, the lower Ti film 104 and the Al film 101 thereon. The TiN / Ti / Al / Ti structure film is composed of the Ti film 102 as the upper layer and the TiN film 103 as the uppermost layer. In addition, the drain electrode 19 and the signal line 12, and the source electrode 18 and the pixel electrode 33 are each configured as an integral multilayer wiring structure. In this embodiment, as with the scanning line 11 and the common line 30, A TiN / Ti / Al / Ti structure film composed of a lower Ti film 134, an Al film 131 thereon, an upper Ti film 132, and an uppermost TiN film 133 is formed. Here, since the ITO film as in the first embodiment does not exist in the upper layer, it is natural that the ITO film does not directly contact the uppermost film TiN film 133 of the scanning line 11 and the signal line 12. It is.

  12 to 15 are views similar to FIG. 11 for explaining each step. First, in FIG. 12, a Ti film 104, an Al film 101, a Ti film 102, and a TiN film 103 are sequentially formed on the transparent insulating substrate 10 by a sputtering method to form a TiN / Ti / Al / Ti structure film. Here, each thickness of the TiN / Ti / Al / Ti structure film is 50 nm / 50 nm / 200 nm / 50 nm. Then, the TiN / Ti / Al / Ti structure film is etched by the first PR to form the gate electrode 15 and the scanning line 11 connected thereto, the frame-shaped common electrode 32 and the common wiring 30 connected thereto. Here, the TiN film 103 is formed by a reactive sputtering method, the flow rate ratio of Ar gas and N gas is adjusted, and nitrogen is contained at 25 atomic% or more. For example, the film forming conditions may be the same as the conditions described in the first embodiment.

Next, as shown in FIG. 13, a SiN film is formed as a gate insulating film 16 on the entire surface to a thickness of 400 nm. Further, an intrinsic a-Si film 121 having a thickness of 250 nm is formed thereon, and an n ⁺ -type a-Si film 122 containing phosphorus as an ohmic layer is formed thereon by a plasma CVD method to a thickness of 50 nm. Then, in the second PR step, a second photoresist film is formed in a required pattern, exposed and developed, and then the n ⁺ -type a-Si film 122 and the intrinsic a− are formed using the second photoresist as a mask. The Si film 121 is sequentially dry etched to form an island-shaped semiconductor layer 17 on the gate electrode 15 with the gate insulating film 16 interposed therebetween.

Further, as shown in FIG. 14, a Ti film 134, an Al film 131, a Ti film 132, and a TiN film 133 are sequentially formed thereon by a sputtering method, and a TiN / Ti / Al / Ti structure film is formed on the scanning line 11. The same thickness as in the case of. Then, the formed TiN / Ti / Al / Ti structure film is etched by the third PR to form the drain electrode 19 and the signal line 12 connected thereto, the source electrode 18 and the frame-like pixel electrode 33 connected thereto. . Here, the TiN film 133 is formed by a reactive sputtering method, and the flow rate ratio between Ar gas and N ₂ gas is adjusted so that nitrogen is contained at 25 atomic% or more. The film forming conditions at this time may be the same as the film forming conditions at the time of forming the scanning lines.

Then, the n ⁺ type a-Si film 122 is dry-etched using the source electrode 18 and the drain electrode 19 as a mask. By this etching, in the semiconductor layer 17, a channel gap is formed between the drain electrode 19 and the source electrode 18, and an ohmic contact of the n ⁺ -type a-Si film 122 is provided immediately below the drain electrode 19 and the source electrode 18. A layer is formed. Thereby, the TFT 14 is formed.

  Next, as shown in FIG. 15, a SiN film is formed as a passivation film 20 on the entire surface by plasma CVD. Thereafter, the gate insulating film 16 and the passivation film 20 of the scanning line terminal portion 22, the common line terminal portion 31, and the passivation film 20 of the signal line terminal portion 23 are removed by the fourth PR, and openings 22a, 31a, and 23a are formed. Form. Accordingly, the configuration shown in FIG. 11 is obtained, and the scanning lines 22, the common lines 30, and the signal lines 12 are partially exposed in the openings 22a, 31a, and 23a, and the terminal portions 22, 31 and 23 are formed. . Next, although not shown, an alignment film is formed on the passivation film in the pixel region arranged in a matrix to form an active matrix substrate. Further, an active matrix liquid crystal display device is completed by disposing a counter substrate on the active matrix substrate at a predetermined interval and sealing the interval between them to fill the liquid crystal. In addition, it is possible to supply power to the active matrix liquid crystal display device by connecting the tape-like terminal of the drive circuit to the scanning line terminal portion and the signal line terminal portion arranged in the peripheral portion of the active matrix substrate. Liquid crystal display becomes possible.

  In the second embodiment, the TiN / Ti / Al / Ti structure film is used for each of the scanning line 11, the common line 30, and the signal line 12, so that Al hillocks are suppressed as in the first embodiment. It becomes possible to do. That is, as in the first embodiment, when Ti is formed between TiN and Al, the physical hillock suppression effect, which is insufficient with TiN, is improved. Further, when Ti is formed in the lower layer of Al, the crystallinity of Al is improved, migration is difficult to occur, and hillocks are suppressed. In addition, as a result of the same connection resistance test as that in the first embodiment, the scanning line terminal unit 22, the common line terminal unit 31, and the signal line terminal unit 23 are similarly tested as shown in FIG. By setting the nitrogen content% of the TiN film to 25% or more, it becomes possible to configure a scanning line connection portion with high reliability against corrosion. From this result, it can be confirmed that even if the thickness of the TiN film is varied, there is no difference in the effect of suppressing Al hillocks. Further, since the ITO film 111 as the upper film is not in contact with the uppermost TiN film 103 of the scanning line 11 and the signal line 12, there is no step of etching the ITO film 111, and the TiN film 103 is damaged. It is natural that reliability can be secured without receiving it.

  In the above embodiment, an example of the TiN / Ti / Al structure film is shown in the first embodiment, and an example of the TiN / Ti / Al / Ti structure film is shown in the second embodiment. It is also possible to use a Ti structure film. In particular, FIG. 7 shows the number of Al hillocks when this TiN / Al / Ti structure film is used. As can be seen from the figure, Al hillocks can be suppressed to almost zero. Further, it has been confirmed that both effects of reducing the connection resistance can be obtained also in this structure. Furthermore, in the present invention, it has been confirmed that similar effects can be obtained even when the Al film is composed of pure Al or an Al alloy.

1, 1A active matrix substrate 10 transparent insulating substrate 11 scanning line 12 signal line 13 pixel portion 14 TFT (thin film transistor)
15 Gate electrode 16 Gate insulating film 17 Semiconductor layer (island)
18 Source electrode 19 Drain electrode 20 Passivation film 21 Pixel electrode 22 Scan line terminal part 23 Signal line terminal part 30 Common line 31 Common line terminal part 32 Common electrode 101 Al film 102 Ti film 103 TiN film 104 Ti film 111 ITO film 112 Cr Film 121 Intrinsic a-Si film 122 n ⁺ type a-Si film 131 Al film 132 Ti film 133 TiN film 134 Ti film

Claims (8)

In an active matrix liquid crystal display device including an active matrix substrate in which a thin film transistor and a pixel electrode are formed on a transparent insulating substrate, the gate electrode of the thin film transistor and a scanning line connected thereto are at least an upper layer and a lower layer of an aluminum film. A multilayer wiring in which a titanium film is formed on one side and a titanium nitride film is formed on the uppermost layer, and a transparent conductive film in contact with the titanium nitride film is not formed on the upper side of the scanning line. The active matrix liquid crystal display device, wherein the titanium nitride film is exposed at the terminal portion of the scanning line, and the titanium nitride film has a nitrogen concentration of 25 atomic% or more. In an active matrix liquid crystal display device including an active matrix substrate in which a thin film transistor and a pixel electrode are formed on a transparent insulating substrate, the source electrode, the drain electrode of the thin film transistor, and a signal line connected thereto are a lower layer of an aluminum film, Alternatively, a multilayer wiring in which a titanium film is formed on both the upper layer and the lower layer and a titanium nitride film is formed on the uppermost layer, and a transparent conductive film in contact with the titanium nitride film is formed on the upper layer side of the signal line. An active matrix liquid crystal display device, characterized in that the titanium nitride film is exposed at a terminal portion of the signal line, and the titanium nitride film has a nitrogen concentration of 25 atomic% or more. In an active matrix liquid crystal display device including an active matrix substrate in which a thin film transistor and a pixel electrode are formed on a transparent insulating substrate, the gate electrode of the thin film transistor and a scanning line connected thereto are at least an upper layer and a lower layer of an aluminum film. A titanium film is formed on one side, and the source electrode and drain electrode of the thin film transistor and the signal line connected thereto are formed on the lower layer of the aluminum film, or both on the upper layer and the lower layer, and on the scanning line and the signal line. A multilayer wiring in which a titanium nitride film is formed on the uppermost layer of the signal line, and a transparent conductive film in contact with the titanium nitride film is not formed on an upper layer side of the scanning line or the signal line; The titanium nitride film is exposed at the terminal portions of the wires and the signal wires, and the titanium nitride film has a nitrogen concentration. Active matrix liquid crystal display device, characterized in that 5 is at% or more. The thin film transistor includes the gate electrode, a gate insulating film formed to cover the gate electrode, an island-shaped semiconductor layer formed on the gate insulating film, and a channel gap on the semiconductor layer. 4. The active matrix liquid crystal display device according to claim 1, wherein the active matrix liquid crystal display device is configured as an inverted staggered thin film transistor constituted by the formed source electrode and drain electrode. 5. The active matrix type liquid crystal according to claim 1, wherein the multilayer wiring structure film of the scanning line has a structure of an aluminum film, a titanium film, or a titanium nitride film from the lower layer to the upper layer. Display device. 5. The multilayer wiring structure film of the scanning line or the signal line has a structure of a titanium film, an aluminum film, or a titanium nitride film from a lower layer toward an upper layer. 6. Active matrix liquid crystal display device. 5. The multilayer wiring structure film of the scanning line or the signal line has a structure of a titanium film, an aluminum film, a titanium film, or a titanium nitride film from the lower layer to the upper layer. 2. An active matrix liquid crystal display device according to item 1. 8. The active matrix liquid crystal display device according to claim 1, wherein the aluminum film is made of aluminum or an alloy mainly composed of aluminum.

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