JP5147196B2 - Element substrate - Google Patents

Description

  The present invention relates to an inspection method using a plurality of oscillation circuits. The present invention also relates to an element substrate for performing the inspection and a method for manufacturing a semiconductor device using the inspection method.

  In the manufacture of a semiconductor device such as a display device composed of a plurality of processes such as etching and doping, an oscillation circuit (hereinafter referred to as an evaluation oscillation circuit) is used as an evaluation circuit in order to evaluate the electrical characteristics of the manufactured semiconductor element. ) On the same substrate as a semiconductor device such as a display device.

  Conventionally, in the measurement of a plurality of evaluation oscillation circuits, the oscillation frequency is measured by applying a needle called a probe to each evaluation oscillation circuit. Such a measurement method for applying a probe needle is called a contact method.

  In addition to display devices such as liquid crystal display devices and EL (Electro Luminescence) display devices, semiconductor devices that can perform such contact-type evaluation include CPUs (Central Processing Units), ASICs (Application Specific Integrated Circuits), and memory devices. And an RF-ID (Radio Frequency Identification) circuit device that wirelessly transmits and receives information.

  The oscillation circuit for evaluation includes a ring oscillator and a PLL (Phase Lock Loop). In addition, a VCO (Voltage Control Oscillator) which is also generally a component of a PLL, and an LC oscillation circuit including a coil and a capacitive element are also included.

  In particular, ring oscillators are commonly used as a measure of good electrical characteristics of manufactured semiconductor elements and for evaluating variations in electrical characteristics.

  In the conventional evaluation of the oscillation circuit, since the probe needle is applied to each measurement terminal of the plurality of oscillation circuits for evaluation, it takes time for measurement including movement of the needle.

  Further, in the conventional evaluation of the oscillation circuit, a plurality of oscillation circuits for evaluation cannot be measured at the same time, which may change the measurement environment. Measurement environment includes parasitic capacitance, power supply, temperature, etc.

  In the conventional evaluation of the oscillation circuit, a plurality of evaluation oscillation circuits are not measured at the same time, so that the measurement error may be different for each measurement. Measurement errors are due to instrument errors and reading errors.

  Accordingly, the present invention has been made in view of the above-described conventional problems, and is capable of measuring a plurality of evaluation oscillation circuits and a combined evaluation oscillation circuit for simultaneously measuring a plurality of evaluation oscillation circuits. It is an object of the present invention to provide a method for measuring coupled oscillation circuits for evaluation to be performed at the same time, and an element substrate that enables measurement.

  In order to solve the above problems, the present invention shares a measurement terminal in a plurality of oscillation circuits for evaluation. In order to share, the measurement terminals are electrically connected by wiring or the like.

  In the present invention, the plurality of oscillation circuits for evaluation may share terminals such as a power supply terminal, a ground terminal, and a control input terminal in addition to the measurement output terminal.

  In a method in which a plurality of evaluation oscillation circuits share a measurement terminal, the measurement terminals of the plurality of evaluation oscillation circuits may be connected via elements such as resistors and capacitors.

  Further, as a method of sharing a measurement terminal among a plurality of evaluation oscillation circuits, the measurement terminals of the plurality of evaluation oscillation circuits may be directly connected.

  The concrete structure of this invention is shown.

  One embodiment of the present invention includes a semiconductor device including a transistor, a measurement terminal, a plurality of evaluation oscillation circuits, and a plurality of evaluation oscillation circuits that share wiring for measurement. Each of the evaluation oscillation circuits includes a transistor, and the transistor included in the evaluation oscillation circuit is an element substrate manufactured in the same process as the transistor included in the semiconductor device to be evaluated.

  Another embodiment of the present invention includes a semiconductor device having a transistor, a measurement terminal, a plurality of oscillation circuits for evaluation, and a wiring for sharing the measurement terminals by the plurality of oscillation circuits for evaluation. The terminal includes a power supply terminal, a ground terminal, or a control input terminal, the plurality of evaluation oscillation circuits each include a transistor, and the transistor included in the evaluation oscillation circuit is the same process as the transistor included in the semiconductor device to be evaluated This is an element substrate manufactured by the method described above.

  Another embodiment of the present invention includes a semiconductor device having a transistor, a measurement terminal, a plurality of oscillation circuits for evaluation in the first region and the second region, and between the first region and the second region. The plurality of evaluation oscillation circuits have wiring for sharing the measurement terminal, the plurality of evaluation oscillation circuits each have a transistor, and the transistor included in the evaluation oscillation circuit is a transistor included in the semiconductor device to be evaluated It is an element substrate characterized by being manufactured in the same process.

  Another embodiment of the present invention includes a semiconductor device having a transistor, a measurement terminal, a plurality of oscillation circuits for evaluation in the first region and the second region, and between the first region and the second region. A plurality of evaluation oscillation circuits have wiring for sharing a measurement terminal, the measurement terminals have a power supply terminal, a ground terminal, or a control input terminal, and the plurality of evaluation oscillation circuits each have a transistor. The transistor included in the oscillation circuit for evaluation is an element substrate manufactured in the same process as the transistor included in the semiconductor device to be evaluated.

  Note that in the present invention, the transistor included in the semiconductor device is provided in the pixel portion or the driver circuit portion.

  Further, the present invention can efficiently inspect such an element substrate.

  In one embodiment of the inspection method of the present invention, a transistor is formed in the pixel portion on the substrate and the oscillation circuit for evaluation in the same process, and a plurality of oscillation circuits for evaluation are formed with the transistors in the oscillation circuit for evaluation. In addition, a measurement terminal that connects a plurality of oscillation circuits for evaluation is formed, and a transistor formed in the pixel portion is inspected using the measurement terminal.

  In another embodiment of the present invention, a transistor is formed in the pixel portion, the drive circuit portion, and the evaluation oscillation circuit portion on the substrate in the same process, and a plurality of evaluation oscillation circuits are formed with the transistors in the evaluation oscillation circuit portion. In addition, a measurement terminal that connects a plurality of oscillation circuits for evaluation is formed, and the transistors formed in the pixel portion and the drive circuit portion are inspected using the measurement terminal.

  In another embodiment of the present invention, a transistor is formed in the pixel portion, the drive circuit portion, and the evaluation oscillation circuit portion on the substrate in the same process, and a plurality of evaluation oscillation circuits are formed with the transistors in the evaluation oscillation circuit portion. And forming a measurement terminal for connecting a plurality of oscillation circuits for evaluation formed in the pixel portion and the drive circuit portion, and inspecting the transistors formed in the pixel portion and the drive circuit portion using the measurement terminal. is there.

  Further, according to the present invention, a semiconductor device can be manufactured using such an inspection method.

  In one embodiment of a method for manufacturing a semiconductor device of the present invention, a semiconductor film is formed over a pixel portion, a driver circuit portion, and an evaluation oscillation circuit portion over a substrate, a gate electrode is formed over the semiconductor film with an insulating film interposed therebetween, Using the gate electrode, an impurity element is added to the semiconductor film to form an impurity region, and a wiring connected to the impurity region is formed. At the same time as the wiring, the oscillation circuit for evaluation is shared by the evaluation oscillation circuit. Forming a measuring terminal.

  In another embodiment of the present invention, a semiconductor film is formed on a pixel portion, a drive circuit portion, and an evaluation oscillation circuit portion on a substrate, a gate electrode is formed on the semiconductor film via an insulating film, and the gate electrode is used. Impurity elements are added to the semiconductor film to form an impurity region, and a wiring connected to the impurity region is formed. At the same time as the wiring, a measurement terminal shared by the evaluation oscillation circuit is formed in the evaluation oscillation circuit section. And using a measuring terminal.

  In another embodiment of the present invention, a semiconductor film is formed on a pixel portion, a drive circuit portion, and an evaluation oscillation circuit portion on a substrate, a gate electrode is formed on the semiconductor film via an insulating film, and the gate electrode is used. Impurity elements are added to the semiconductor film to form an impurity region, and a wiring connected to the impurity region is formed. At the same time as the wiring, a measurement terminal shared by the evaluation oscillation circuit is formed in the evaluation oscillation circuit section. Then, an inspection is performed using the measurement terminal, and the oscillation circuit for evaluation is disconnected.

  In the present invention, when a measurement is performed by applying a needle to a measurement terminal shared by a plurality of oscillation circuits for evaluation, a waveform of a time change in potential or current obtained by superimposing the outputs of the plurality of oscillation circuits for evaluation is obtained. . The superimposed potential is the case where multiple evaluation oscillation circuits share the measurement terminal, and if the sink current and the discharge current of the element that outputs the output potential of each evaluation oscillation circuit are the same, each evaluation oscillation circuit The output potential is averaged. The sink current is also called a low-level output current or a sink current, and indicates a current that can flow into the output. The discharge current is also called a high level output current or a source current, and indicates a current that can flow from the output.

  In the present invention, when a waveform measured by applying a needle to a measurement terminal shared by a plurality of oscillation circuits for evaluation is Fourier transformed, a pattern having one or more maximum values (peaks) is obtained. The plurality of maximum values correspond to the frequencies of each evaluation oscillation circuit. That is, if the frequency of each oscillation circuit for evaluation is different, a pattern having a plurality of maximum values can be obtained by Fourier transform.

  In the present invention, the substrate may be a single crystal silicon substrate including SOI (Silicon on Insulator), an insulating substrate such as quartz, glass, plastic, or a metal substrate.

  In the present invention, since the plurality of evaluation oscillation circuits share the terminal, the oscillation frequency can be measured by placing a needle on a smaller number of measurement terminals than the number of the evaluation oscillation circuits.

  In the present invention, since a plurality of oscillation circuits for evaluation share a terminal, the oscillation frequency is measured simultaneously.

  In the present invention, in order to facilitate the simultaneous measurement of the oscillation frequencies of the plurality of oscillation circuits for evaluation, a circuit for synchronizing the plurality of oscillation circuits for evaluation is formed.

  The circuit to be synchronized can be composed of NAND, NOR, clocked inverter, analog switch, and the like.

  In the present invention, one or a plurality of oscillation circuits for evaluation are integrally formed on the same substrate as a semiconductor device such as a display device.

  According to the evaluation oscillation circuit that shares and couples the measurement terminals of the plurality of oscillation circuits for evaluation of the present invention, it is possible to perform measurement of the plurality of oscillation circuits for evaluation at the same time, including needle movement and the like. Measurement time is shortened.

  In addition, according to the evaluation oscillation circuit that shares and couples the measurement terminals of the plurality of evaluation oscillation circuits of the present invention, a plurality of evaluation oscillation circuits can be measured at the same time, so that measurement can be performed in the same measurement environment. It becomes. According to the evaluation oscillation circuit that shares the measurement terminals of the plurality of oscillation circuits for evaluation of the present invention and is coupled, it is possible to measure a plurality of oscillation circuits for evaluation at the same time. Become.

  In the present invention, when the oscillation frequencies of a plurality of evaluation oscillation circuits are designed to be the same, the characteristics of the semiconductor element, the processing of patterns such as wiring and vias, and the processing and characteristics of the insulating film vary depending on the position on the substrate. It is possible to provide a means for more easily confirming that there is no more than the conventional evaluation method.

  In the present invention, when a plurality of evaluation oscillation circuits are designed to have the same oscillation frequency, the characteristics of semiconductor elements, the processing of patterns such as wiring and vias, and the processing and characteristics of insulating films can be stabilized for a long time. Means for confirming more easily than conventional evaluation methods are provided.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, an inspection method of the present invention will be described.

  In FIG. 1, each oscillation circuit for evaluation 101 has an output signal line and is connected to a measurement terminal 100 via a wiring 102. In the present invention, the evaluation oscillation circuit 101 includes two or more. In FIG. 1, each oscillation circuit for evaluation 101 oscillates independently of each other and outputs a periodically changing potential. The evaluation oscillation circuit 101 may have a circuit for synchronization. If there is no synchronization circuit, the oscillation frequency may not be obtained in very rare cases. Considering such a case, it is desirable to have a synchronization circuit.

  In the present invention, measurement is performed by measuring a change in potential or current by applying a measurement needle called a probe to the measurement terminal 100. In the present invention, since the measurement terminal 100 is shared by the circuit, the inspection time can be shortened. In addition, since there is no need to apply a plurality of measuring needles simultaneously, there is no cost and alignment problem for making the measuring needles.

  For comparison, FIG. 9 shows a configuration of a conventional evaluation oscillation circuit. Conventionally, in order to measure a plurality of oscillation circuits for evaluation 901, the output signals of the oscillation circuits for evaluation 901 are connected to different measurement terminals 900 that are not electrically connected to each other, and each measurement terminal 900 is connected. It was measured by.

  In the configuration of FIG. 9, it takes time to measure the output signal of each evaluation oscillation circuit 901 because the measurement is performed at each measurement terminal 900. Further, in order to simultaneously apply a plurality of measuring needles, the cost for making the measuring needles and the difficulty of alignment are problems.

  In the present invention, two or more independent measurement terminals 900 are combined into one. In the present invention, two or more independent measurement terminals 900 are combined by electrically connecting the wirings 902. As a result, a plurality of oscillation circuits for evaluation can be evaluated by one measurement and can be easily evaluated from FIG.

  The entire measurement of the oscillation circuit for evaluation is performed as many times as the number of measurement terminals in the prior art and in the present invention. Actually, the same evaluation circuit may be repeatedly measured to measure the passage of time, and the measurement is performed by the number of repetitions multiplied by the number of measurement terminals. If the number of oscillation circuits for evaluation is the same in the present invention and the present invention, the present invention can measure in a short time because the number of measurement terminals is smaller than the number of measurement terminals shared. For example, in the present invention, when two evaluation oscillation circuits share one measurement terminal, the work that has been measured twice in the past to measure two evaluation oscillation circuits is one measurement in the present invention. It's okay.

  Further, if the number of measurement terminals is the same in the present invention as in the present invention, the present invention has a larger number of evaluation oscillation circuits than the number of conventional evaluation oscillation circuits. Can be evaluated. For example, in the present invention, when two evaluation oscillation circuits share one measurement terminal, conventionally, only one evaluation oscillation circuit could be evaluated in one measurement, but in the present invention, two evaluation oscillations are performed. The circuit can be evaluated.

  In FIG. 1, when the potential change of the measurement terminal 100 is measured to obtain the oscillation frequency, a waveform in which the outputs of the plurality of evaluation oscillation circuits 101 are superimposed is obtained. By observing the obtained waveform, the oscillation frequencies of the plurality of evaluation oscillation circuits 101 can be found. However, when a complex waveform is obtained, it is not easy to obtain the oscillation frequencies of the plurality of evaluation oscillation circuits 101. Therefore, according to the present invention, the oscillation frequency of the plurality of oscillation circuits for evaluation 101 can be obtained by performing Fourier transform on the waveform obtained by the measurement. The present invention is characterized by a step of Fourier transform. The oscillation frequency of the oscillation circuit for evaluation can be found by Fourier transform. It can be seen that if the oscillation frequency is different, the electrical characteristics of the semiconductor element constituting the oscillation circuit for evaluation and the electrical characteristics due to processing of wiring, vias and the like are different. If it is known that the electrical characteristics of the semiconductor elements of the evaluation oscillation circuit vary, the evaluation oscillation circuit has variations in the semiconductor elements constituting the semiconductor device such as a display device that are integrally formed on the substrate at the same time. I guess that.

  In general, when a waveform having a non-sinusoidal periodicity is output from one evaluation oscillation circuit, a pattern having a plurality of maximum values can be obtained by Fourier transforming the waveform output from one evaluation oscillation circuit. If one oscillation circuit for evaluation oscillates stably, one maximum value is obtained in the frequency portion due to the periodicity of the output waveform in the Fourier transformed pattern.

  In the conventional inspection method, since the measured waveform is the waveform of one oscillation circuit for evaluation, it is not necessary to perform Fourier transform for the purpose of analyzing the oscillation frequency. In the present invention, the oscillation frequency can be evaluated without performing Fourier transform if the oscillation frequencies and phases of the plurality of oscillation circuits for evaluation are the same, but it is desirable to perform Fourier transform in order to accurately obtain the oscillation frequency variation. .

  In the present invention, for example, when a plurality of evaluation oscillation circuits have the same electrical characteristics, and the oscillation phases of the plurality of evaluation oscillation circuits are the same, the same waveform as the output of one evaluation oscillation circuit is obtained. Alternatively, when the phases are different, a waveform different from the output of one evaluation oscillation circuit is obtained, but in the Fourier-transformed pattern, one maximum value is present in the frequency portion due to the periodicity of the output waveform of one evaluation oscillation circuit. Is obtained. And each oscillation circuit for evaluation can be inspected.

  In the conventional measurement of a plurality of evaluation oscillation circuits, for example, when the plurality of evaluation oscillation circuits have the same electrical characteristics, the same waveform is obtained as the output of each evaluation oscillation circuit. However, since measurement is not performed at the same time, there may be differences such as changes in measurement environment and measurement errors.

  In the present invention, even if a plurality of evaluation oscillation circuits are designed to have the same electrical characteristics, if there are variations in position dependence on the substrate due to the manufacturing process, the output waveform of the combined evaluation oscillation circuits is Fourier transformed. In this pattern, a plurality of maximum values are obtained in the frequency portion due to the periodicity of the output waveform. Alternatively, a pattern in which a plurality of local maximum values overlap and spread in the frequency axis direction is obtained.

  Conventionally, in order to confirm that there is no variation in the characteristics of semiconductor elements and the processing of patterns depending on the position on the substrate, it has been necessary to measure the measurement terminals 900 one by one to confirm that they have the same oscillation frequency. However, if the measurement terminal 100 is measured and Fourier transformed according to the present invention, a plurality of evaluations can be easily made by simply confirming that the maximum of the Fourier transform appears at the position of the designed oscillation frequency. It can be confirmed that the oscillation frequency of the oscillation circuit 101 is the same. Then, it can be confirmed that there is no variation in the characteristics of the semiconductor element and the pattern processing depending on the position on the substrate.

  In the present invention, the semiconductor elements and wirings constituting the evaluation oscillation circuit are formed simultaneously with the semiconductor elements and wirings of a semiconductor device such as a display device or a logic circuit device. The evaluation oscillation circuits are distributed on the substrate. Therefore, if the oscillation frequency of each evaluation oscillation circuit of the evaluation oscillation circuit connected in the present invention greatly varies, a semiconductor device such as a display device or a logic circuit device is formed on the same substrate at the same time. It is presumed that there are large variations in the electrical characteristics of the semiconductor elements and the parasitic capacitance and resistance of the wiring. If variation permissible for a semiconductor device such as a display device or a logic circuit device is obtained in advance, it is possible to classify defects by measuring the combined oscillation circuit for evaluation of the present invention.

  Conventionally, when measuring the measurement terminals 900 one by one and obtaining the oscillation frequency, there is a possibility that the accuracy may be deteriorated due to variations in the measuring instruments and reading errors. In the present invention, the oscillation frequencies of the plurality of evaluation oscillation circuits 101 are simultaneously obtained by the measurement terminal 100, so that the oscillation frequencies of the plurality of evaluation oscillation circuits 101 can be compared with higher accuracy than the conventional accuracy.

  In the past, it took time and labor to measure each evaluation oscillation circuit one by one, and there were factors that caused errors due to separate measurement, but the present invention measures multiple evaluation oscillation circuits simultaneously. There is an effect that can be done.

  In the present invention, the plurality of oscillation circuits for evaluation may have different electrical characteristics of the semiconductor elements constituting each evaluation oscillation circuit.

(Embodiment 2)
In this embodiment, a configuration diagram showing another embodiment of the present invention will be described. In FIG. 2, each oscillation circuit for evaluation 201 is characterized in that an output signal line is connected to a measurement terminal 200 via an element 202 such as a resistor or a capacitor. The evaluation oscillation circuit 201 is the same circuit as the evaluation oscillation circuit 101.

  In FIG. 2, an output buffer that directly changes the potential of the output node of the oscillation circuit for evaluation 201 may be composed of a CMOS (Complementary Metal Oxide Semiconductor) inverter element. When the output nodes of a plurality of CMOS inverter elements are directly connected, a larger current flows through the inverter element connected to the output node than when the output node is not connected. Direct connection means that the connection is made without using an element such as a resistance or a capacitor that is not a parasitic resistance.

  In the element 202 such as a resistor or a capacitor, the voltage drop of the power source caused by the current flowing through the inverter element connected to the output node is sufficiently small, so that each evaluation oscillation circuit 201 can be separated. Therefore, the element 202 such as a resistor or a capacitor is preferably designed so that the voltage drop of the power source is sufficiently small.

  In the first embodiment in which the element 202 such as a resistor or a capacitor is not used, the output buffer constituting the evaluation oscillation circuit 101 needs to be designed so that the voltage drop of the power supply becomes sufficiently small. Therefore, by connecting the evaluation oscillation circuit and the measurement terminal via elements such as a resistor and a capacitor as in the present embodiment, such design restrictions can be eliminated.

  In the present invention, the plurality of oscillation circuits for evaluation may have different electrical characteristics of the semiconductor elements constituting each evaluation oscillation circuit.

(Embodiment 3)
In this embodiment mode, an element substrate for performing the inspection described in Embodiment Modes 1 and 2 will be described.

  FIG. 15A is a top view of an element substrate on which a semiconductor device according to the present invention is formed. In FIG. 15, a display device 1501 including a pixel portion 1503 and a driver circuit portion 1504 is formed over a substrate 1500 such as glass. One or a plurality of evaluation oscillation circuits 1502 of the present invention are arranged around the display device 1501. Alternatively, if there is a vacant place inside the display device 1501, it may be arranged inside.

  The evaluation oscillation circuit 1502 includes an oscillation circuit 1511 such as a ring oscillator, a common wiring 1512 connecting them, and a measurement terminal 1510 connected to the common wiring. The inspection of the present invention can be performed by applying a probe to the measurement terminal 1510.

  It is desirable to dispose a plurality of evaluation oscillation circuits 1502 in a wide range of the substrate 1500 as much as possible. By disposing a plurality of evaluation oscillation circuits 1502 around the display device 1501, the display device is more accurate than the case where there is only one evaluation oscillation circuit 1502 or a centralized arrangement. This is because the electric characteristics of the semiconductor element 1501 can be estimated.

  When the evaluation oscillation circuit 1502 is arranged inside the display device 1501, the evaluation oscillation circuit 1502 can estimate the electrical characteristics of the semiconductor elements of the display device 1501 more accurately than in the case where the evaluation oscillation circuit 1502 is arranged only in the periphery. .

  In the present invention, the oscillation circuit for evaluation 1502 is arranged as a circuit independently of the display device 1501. The evaluation oscillation circuit 1502 may be disconnected when the display device 1501 is completed.

  In FIG. 15A, one evaluation oscillation circuit 1502 is an evaluation oscillation circuit in which a plurality of evaluation oscillation circuits are connected. However, the present invention is arranged on a substrate as shown in FIG. 15B. All the oscillation circuits for evaluation arranged in a distributed manner may be connected to one measurement terminal. By connecting the probe to one measurement terminal and applying the probe to one measurement terminal to measure the potential change, each oscillation circuit for evaluation distributed over the entire substrate can be measured simultaneously. It is possible to easily evaluate the variation of the electrical characteristics and the like in a short time.

  Since the inspection method using the oscillation circuit for evaluation of the present invention can be evaluated in a short time, the mass productivity can be improved.

  In this embodiment, a circuit diagram in which the oscillation circuit for evaluation is constituted by a ring oscillator is shown. FIG. 3 corresponds to the configuration of FIG. In FIG. 3, two ring oscillators are connected via a resistance element 302. In the present invention, the oscillation circuit for evaluation is not limited to the ring oscillator, but may be a PLL, VCO, or LC oscillation circuit. In this embodiment, the case of the ring oscillator will be described. Further, in the present invention, the number of evaluation oscillation circuits may be two or more, but in this embodiment, a case where there are two ring oscillators will be described.

  In FIG. 3, the ring oscillator 304 includes 11 inverter elements, and has an inverter element as the output buffer 301. However, the number of inverter elements constituting the ring oscillator is not limited to eleven. The ring oscillator is composed of an odd number of inverter elements. However, the ring oscillator may not oscillate if the number of inverters constituting the ring oscillator is small, depending on the electrical characteristics parasitic on the wiring such as parasitic capacitance and the electrical characteristics of the semiconductor elements constituting the inverter. Therefore, it comprises a plurality of inverters.

  When the output buffer 301 is omitted in the configuration of FIG. 3, the oscillation frequency of the ring oscillator changes due to the influence of the other ring oscillator. When the output buffer 301 is omitted in the configuration of FIG. 3, the output of one ring oscillator is input to the other ring oscillator, so that the two ring oscillators oscillate in the same phase with the same period. The purpose of the present invention is to measure the variation in the oscillation frequency of the plurality of oscillation circuits for evaluation, and it is not desirable that the plurality of oscillation circuits for evaluation influence the same oscillation. Therefore, an output buffer 301 is provided in the configuration of FIG. The output buffer 301 may be composed of a plurality of inverter elements or an operational amplifier.

  In general, the measurement needle performs measurement by capacitive coupling so as not to affect the potential of the measurement object. Therefore, it is desirable that the resistance value of the resistance element 302 is not too large so that the oscillation frequency can be sufficiently measured in consideration of the capacitance of the measuring needle, the parasitic capacitance, and the parasitic resistance.

  On the other hand, when the resistance value of the resistance element 302 is small and the outputs of the two evaluation oscillation circuits do not match, a large current flows through the output buffer 301 in the configuration of FIG. Therefore, the resistance value of the resistance element 302 is not too small and desirably has a certain resistance value.

  In order to facilitate the evaluation, it is desirable that the power supply wiring and the ground wiring which are not clearly shown in the circuit diagram have little influence on the oscillation frequency of the oscillation circuit for evaluation. In order to reduce the influence of the power supply wiring and ground wiring on the oscillation frequency of the oscillation circuit for evaluation, the power supply wiring and ground wiring are designed to supply sufficient power so that there is little fluctuation and the potential can be recovered earlier than the oscillation cycle. To be. The power supply wiring and the ground wiring are designed so that the resistance of the power supply wiring and the ground wiring is reduced by using a material having a short resistance, a wide width, or a low resistance in order to supply power sufficiently. In addition, a capacitor element is formed for releasing a high frequency component of power fluctuation generated in the power supply wiring and the ground wiring.

  If the current capability and power supply capability of the output buffer 301 are sufficiently considered in the configuration of FIG. 3, the resistance element 302 that is not a parasitic resistance can be omitted.

  FIG. 4 shows a waveform obtained by measuring a potential change of the wiring 303 (hereinafter referred to as a node) in FIG. This will be described based on calculation results that can easily change the phase and frequency. Actually, a potential change is measured by applying a probe to a measurement terminal corresponding to the node 303. FIG. 4 shows waveforms when the two ring oscillators 304 of FIG. 3 oscillate at different frequencies. This represents a case where an oscillation circuit for evaluation designed to oscillate at the same frequency oscillates at a different frequency due to variations in characteristics and processing of the semiconductor element on the substrate in the process of forming the semiconductor element and wiring. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the potential of the node 303. Outputs of different frequencies of the two ring oscillators 304 cause a beat phenomenon.

  FIG. 5 shows a Fourier transform of the waveform of FIG. The oscillation frequency can be easily read by performing Fourier transform. The horizontal axis indicates the frequency. Two maxima 500 represent different oscillation frequencies of the two ring oscillators 304, respectively. Maximums other than the two maximums 500 represent frequency components due to the fact that the output waveform of the ring oscillator 304 is not a sine wave.

  FIG. 6 shows a waveform obtained by measuring the potential change of the node 303 in FIG. FIG. 6 shows waveforms when the two ring oscillators 304 of FIG. 3 oscillate at the same phase and the same frequency. This represents a case where an oscillation circuit for evaluation designed to oscillate at the same frequency oscillates at the same frequency without variations in characteristics and processing of the semiconductor element on the substrate in the process of forming the semiconductor element and wiring. Further, since the ring oscillator of FIG. 3 is configured such that the phase of oscillation cannot be controlled, it represents a case where the same phase occurs by chance. In FIG. 6, the horizontal axis represents time, and the vertical axis represents the potential of the node 303.

  FIG. 7 shows a diagram obtained by Fourier transforming the waveform of FIG. Although the oscillation frequency can be obtained without performing Fourier transform in FIG. 6, Fourier transform is performed for comparison with FIG. The oscillation frequency can be easily read by performing Fourier transform. The horizontal axis indicates the frequency. A maximum 700 represents the oscillation frequency of the two ring oscillators 304. The maximum 701 represents a frequency three times that of the maximum 700 due to the output of the ring oscillator 304 being not a sine wave.

  In the case where the two ring oscillators in FIG. 3 have the same shape or the same oscillation frequency and are laid out at different positions on the substrate, 1 near the oscillation frequency of each ring oscillator as shown in FIG. When a Fourier transform result having two maxima is obtained, it can be seen that variation due to the substrate position of the two ring oscillators is sufficiently small.

  When the two ring oscillators 304 in FIG. 3 oscillate at the same frequency with different phases, the potential change at the node 303 has a period in which the outputs of the two ring oscillators cancel each other. When oscillating in the opposite phase, sufficient amplitude cannot be obtained to perform Fourier transform. Actually, there is a low probability that the phases of the two ring oscillators will be out of phase to the extent that sufficient amplitude cannot be obtained for performing the Fourier transform. In the case of three or more ring oscillators, the phase is sufficient to perform the Fourier transform. The probability of canceling out to such an extent that amplitude cannot be obtained is much smaller than in the case of two ring oscillators.

  In order to prevent the two ring oscillators from oscillating in the opposite phase at the same frequency, a circuit for synchronizing the oscillations of the two ring oscillators may be added. In FIG. 8, in order to synchronize the oscillations of the two ring oscillators, one of 11 inverters constituting the ring oscillator 304 is replaced with a NAND 801. In FIG. 8, since the oscillation starts when the node 800 is raised from the ground potential to the power supply potential, the oscillations of the two ring oscillators are synchronized. In FIG. 8, if the potential change at the node 802 is measured, a waveform with little cancellation is obtained as shown in FIG.

  The circuit for synchronizing the oscillations of the two ring oscillators is not limited to the NAND. The circuit for synchronizing the oscillations of the two ring oscillators may be NOR or a clocked inverter. Even if any one of the 11 inverters constituting the ring oscillator 304 is replaced with the NAND 801, the NAND 801 synchronizes the oscillation of the two ring oscillators.

  In this example, a manufacturing process of a semiconductor device using the evaluation method of the present invention will be described.

  A base film is provided on the insulating substrate. A thin film transistor is provided through a base film. The thin film transistor can be used as a pixel portion of a semiconductor device or an element of a driver circuit portion. Each thin film transistor includes a gate electrode provided through a semiconductor film formed in an island shape and a gate insulating film. Preferably, an insulator (so-called sidewall) is provided on a side surface of the gate electrode. This is because the short channel effect can be prevented by the sidewall. The semiconductor film is formed to have a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Furthermore, an insulating film covering the semiconductor film and an electrode connected to the impurity region formed in the semiconductor film are provided. Note that since the electrode is connected to the impurity region, a contact hole can be formed in an insulating film such as a gate insulating film, a conductive film can be formed in the contact hole, and the conductive film can be processed.

  As the semiconductor film, amorphous silicon or polycrystalline silicon can be used. In the case of using polycrystalline silicon, amorphous silicon can be formed first, and heat treatment or laser irradiation can be performed to obtain polycrystalline silicon. At this time, the crystallization temperature can be reduced by performing heat treatment or laser irradiation using a metal element typified by nickel. For laser irradiation, a continuous wave or pulsed laser irradiation apparatus can be used. Alternatively, a crystallization method involving heat treatment may be combined with a crystallization method in which a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher is irradiated. By irradiation with a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher, the surface of the crystallized semiconductor film can be flattened. As a result, the gate insulating film can be made thinner and can contribute to improving the breakdown voltage of the gate insulating film.

  In addition, a semiconductor film obtained by scanning and crystallizing in one direction while irradiating a semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more grows crystals in the scanning direction of the beam. There is a characteristic to do. Transistors are arranged with the scanning direction aligned with the channel length direction (the direction in which carriers flow when a channel formation region is formed), and by combining the following gate insulating films, there is little variation in characteristics and field effect transfer A high degree transistor (TFT) can be obtained.

In the semiconductor device of the present invention, an insulating film such as a gate insulating film can be manufactured using high-density plasma treatment. The high density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , and microwaves (for example, frequency 2.45 GHz) This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects. In the film formation chamber capable of such plasma treatment, a substrate on which an object to be formed and a gate insulating film are formed is provided with a substrate formed with an island-shaped semiconductor film. Then, a film forming process is performed with a distance between an electrode for plasma generation, a so-called antenna, and an object to be formed being 20 mm to 80 mm, preferably 20 mm to 60 mm. Such a high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, a film can be formed over a plastic substrate with low heat resistance.

  Such an insulating film can be formed in a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used.

  The insulating film formed in this way has little damage to other films and becomes dense. In addition, an insulating film formed by high-density plasma treatment can improve an interface state in contact with the insulating film. For example, when the gate insulating film is formed using high-density plasma treatment, the interface state with the semiconductor film can be improved. As a result, the electrical characteristics of the thin film transistor can be improved. An insulating film formed by high-density plasma treatment has stable characteristics.

  Although the case where high-density plasma treatment is used for manufacturing the insulating film has been described, the semiconductor film may be subjected to high-density plasma treatment. The semiconductor film surface can be modified by high-density plasma treatment. As a result, the interface state can be improved, and the electrical characteristics of the thin film transistor can be improved. A thin film transistor formed by high-density plasma treatment has stable electrical characteristics.

  A semiconductor device such as a display device including a thin film transistor and an oscillation circuit for evaluation of the present invention which is formed on the same substrate at the same time as a semiconductor device such as a display device, for example, a high-density plasma treatment of a semiconductor film or a gate insulating film Then, the gate electrode and the wiring connected to the semiconductor film are formed and manufactured.

  The evaluation oscillation circuit of the present invention can be measured by applying a probe after the circuit is formed by wiring, in the same way as the measurement of the conventional single evaluation oscillation circuit. The wiring layer is not limited to one layer. After the oscillation circuit is formed with the first wiring layer, the measurement terminal is exposed to the surface and measurement is performed with a probe every time the circuit is multi-layered. Can also be evaluated. Although it is possible to measure a conventional oscillation circuit, in order to evaluate a plurality of evaluation oscillation circuits in order to evaluate the influence on variation, the present invention can be more easily evaluated than the conventional method.

  In order to evaluate a thin film transistor composed of an insulating film or a semiconductor film formed by high-density plasma treatment, a more accurate evaluation method is required. According to the present invention, since a plurality of evaluation oscillation circuits on a substrate can be measured simultaneously, it is possible to perform measurement with little measurement error, and it is possible to provide a semiconductor device such as a stable display device or logic circuit device.

  In this embodiment, a layout of a semiconductor device using the evaluation method of the present invention will be described.

  In the thin film transistor of the present invention, the photomask for forming the semiconductor layer has a pattern. This photomask pattern is rounded by removing right-angled triangles with sides of 10 μm or less at the corners. The shape of this mask pattern can be transferred as the pattern shape of the semiconductor layer 1000 as shown in FIG. Further, when transferring to the semiconductor layer, the corner of the semiconductor layer may be transferred so as to be more rounded than the corner of the photomask pattern. In other words, the corners of the pattern of the semiconductor layer may be provided with roundness with a smoother pattern shape than the pattern of the photomask. In FIG. 10, gate electrodes and wirings to be formed later are indicated by dotted lines.

  Next, a gate insulating film is formed over the semiconductor layer processed so that the corners are rounded. Then, a gate electrode and a gate wiring are formed at the same time so as to partially overlap the semiconductor layer. The gate electrode or the gate wiring can be formed by a photolithography technique by forming a metal layer or a semiconductor layer.

The photomask for forming the gate electrode or the gate wiring has a pattern. In this photomask pattern, corners are deleted to a length that is 1/2 or less of the line width of the wiring and 1/5 or more of the line width. The shape of the mask pattern can be transferred as a pattern shape of a gate electrode or gate wiring 1100 as shown in FIG. In addition, when transferring to the gate electrode or the gate wiring, the corner of the corner portion of the gate electrode or the gate wiring may be further rounded. That is, the corners of the gate electrode or the gate wiring may be provided with rounding with a smoother pattern shape than the photomask pattern. A corner portion of a gate electrode or a gate wiring formed using such a photomask can be rounded at a corner portion that is 1/2 or less of the line width and 1/5 or more.
Note that in FIG. 11, wirings to be formed later are indicated by dotted lines.

  Such a gate electrode or gate wiring is bent into a rectangle due to layout restrictions. Therefore, a rounded corner portion of the gate electrode or gate wiring is provided with a convex portion (outer side) and a concave portion (inner side). In the rounded outside, generation of fine powder due to abnormal discharge can be suppressed during dry etching by plasma. In the rounded inner side, even if fine powder adheres to the substrate during cleaning, the cleaning liquid can be washed away without staying in the corners of the wiring pattern. As a result, the yield can be greatly improved.

  Next, an insulating layer is formed over the gate electrode or the gate wiring. The insulating layer is composed of a single layer or a plurality of insulating films.

  Then, an opening is formed at a predetermined position of the insulating layer, and a wiring is formed in the opening. This opening is provided for electrical connection between the semiconductor layer or gate wiring layer located in the lower layer and the wiring. The wiring is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching.

  A certain element can be connected by wiring. This wiring does not connect a specific element with a straight line, but bends into a rectangle (hereinafter referred to as a bent portion) due to layout restrictions. In addition, the wiring width of the wiring may change in the opening and other regions. For example, in the opening, when the opening is equal to or larger than the wiring width, the wiring width is changed so as to widen at that portion. Further, since the wiring also serves as one electrode of the capacitor portion in the circuit layout, the wiring width may be increased.

In this case, in a bent portion that is bent into a rectangular shape of the photomask pattern, one side of the right triangle formed is 10 μm or less, or 1/2 or less of the line width of the wiring and 1/5 or more of the line width. Remove the corners. Then, as shown in FIG. 12, the wiring pattern 1200 is similarly rounded. That is, the outer periphery of the wiring at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other across the corner portion and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring corresponding to the part of the right isosceles triangle formed by is removed. When removed, two new obtuse angle parts are formed on the wiring. By appropriately setting the mask design and etching conditions, a curve that touches both the first and second lines is formed at each obtuse angle part. It is preferable to etch the wiring as described above. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion.
Such a rounded wiring shape can suppress the generation of fine powder due to abnormal discharge at the inside of the bent portion during dry etching with plasma. On the inside, even if fine powder adheres to the substrate at the time of cleaning, the cleaning liquid can be washed away without staying in the corner portion of the wiring pattern, and as a result, the yield can be greatly improved. This is also an advantage that when there are a large number of parallel wirings on the substrate, the attached fine powder can be easily removed by washing. By rounding the corners of the wiring, it can be expected to be electrically conducted.

  In the circuit having the layout shown in FIG. 12, the corners of the bent portion and the portion where the wiring width changes are smoothed and rounded to suppress the generation of fine powder due to abnormal discharge during dry etching by plasma, Even if it is a fine powder that has been produced at the time of washing, it has the effect that a significant improvement in yield can be expected as a result of washing away that it tends to collect at the corner. That is, the problem of dust and fine powder in the manufacturing process can be solved. In addition, it can be expected that the wiring is electrically conductive by adopting a configuration in which the corners of the wiring are rounded. In particular, it is very advantageous to be able to wash away dust in wiring such as a drive circuit section provided with a large number of parallel wirings.

  Note that in this embodiment, the three-layer layout of the semiconductor layer, the gate wiring, and the wiring has been described as having a rounded corner or bend, but the present invention is not limited to this. That is, in any one layer, it is only necessary to round the corners or the bent portions to solve problems such as dust and fine powder in the manufacturing process.

  According to the embodiment in which the corner portion or the bent portion is rounded as described in this embodiment, the yield of a semiconductor device such as a display device or a logic circuit device is improved, and the electrical characteristics are improved. In order to evaluate the improvement in yield, it is effective to measure a large number of oscillation circuits for evaluation arranged in a distributed manner on the substrate. However, the conventional evaluation method takes time. According to the present invention, even a large number of oscillation circuits for evaluation can be evaluated with a small number of measurements.

  In this example, a manufacturing process of a semiconductor device using the evaluation method of the present invention will be described.

  The evaluation oscillation circuit of the present invention and the semiconductor device formed simultaneously with the evaluation oscillation circuit are configured to include transistors. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 13 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 13 shows an n-channel TFT 1301, an n-channel TFT 1302, a capacitor element 1304, a resistor element 1305, and a p-channel transistor 1303. Each transistor includes a semiconductor layer 1405, an insulating layer 1408, and a gate electrode 1409. The gate electrode 1409 is formed with a stacked structure of a first conductive layer 1403 and a second conductive layer 1402. 14A to 14E are top views corresponding to the transistor, the capacitor, and the resistor illustrated in FIG. 13 and can be referred to.

  In FIG. 13, an n-channel TFT 1301 is also referred to as a low concentration drain (LDD) on both sides of the gate electrode in the channel length direction (carrier flow direction), and forms a source and drain region that forms a contact with the wiring 1404. An impurity region 1407 doped at a lower concentration than the impurity concentration of the impurity region 1406 is formed in the semiconductor layer 1405. When the n-channel TFT 1301 is formed, phosphorus or the like is added to the impurity region 1406 and the impurity region 1407 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 14A, in the gate electrode 1409 of the n-channel TFT 1301, the first conductive layer 1403 is formed so as to spread on both sides of the second conductive layer 1402. In this case, the first conductive layer 1403 is formed thinner than the second conductive layer. The first conductive layer 1403 is formed to have a thickness that allows passage of ion species accelerated by an electric field of 10 to 100 kV. The impurity region 1407 is formed so as to overlap with the first conductive layer 1403 of the gate electrode 1409. That is, an LDD region overlapping with the gate electrode 1409 is formed. In this structure, an impurity region 1407 is formed in a self-aligned manner in the gate electrode 1409 by adding one conductivity type impurity through the first conductive layer 1403 using the second conductive layer 1402 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  Transistors having LDDs on both sides are applied to rectifying TFTs and transistors constituting transmission gates (also referred to as analog switches) used in logic circuits, and constitute semiconductor devices. In these TFTs, since both positive and negative voltages are applied to the source and drain electrodes, it is preferable to provide LDDs on both sides of the gate electrode.

  In FIG. 13, an n-channel TFT 1302 has an impurity region 1407 doped in a lower concentration than the impurity concentration of the impurity region 1406 in a semiconductor layer 1405 on one side of a gate electrode. As shown in FIG. 14B, in the gate electrode 1409 of the n-channel TFT 1302, the first conductive layer 1403 is formed so as to spread on one side of the second conductive layer 1402. In this case as well, LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 1403 using the second conductive layer 1402 as a mask.

  A transistor having an LDD on one side may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 13, the capacitor 1304 is formed by sandwiching an insulating layer 1408 between a first conductive layer 1403 and a semiconductor layer 1405. A semiconductor layer 1405 that forms the capacitor 1304 includes an impurity region 1410 and an impurity region 1411. The impurity region 1411 is formed in the semiconductor layer 1405 so as to overlap with the first conductive layer 1403. The impurity region 1410 forms a contact with the wiring 1404. Since the impurity region 1411 can be doped with one conductivity type impurity through the first conductive layer 1403, the impurity concentration in the impurity region 1410 and the impurity region 1411 can be the same or can be different. It is. In any case, since the semiconductor layer 1405 functions as an electrode in the capacitor 1304, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 14C, the first conductive layer 1403 can sufficiently function as an electrode by using the second conductive layer 1402 as an auxiliary electrode. As described above, by using a composite electrode structure in which the first conductive layer 1403 and the second conductive layer 1402 are combined, the capacitor 1304 can be formed in a self-aligning manner.

  The capacitor is used as a storage capacitor included in the power supply circuit or a resonance capacitor included in the resonance circuit. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 13, the resistance element 1305 is formed by the first conductive layer 1403. Since the first conductive layer 1403 is formed to a thickness of about 30 to 150 nm, the resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element is used as a resistance load included in the modulation circuit. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 13, a p-channel transistor 1303 includes an impurity region 1412 in a semiconductor layer 1405. The impurity region 1412 forms source and drain regions that form a contact with the wiring 1404. The gate electrode 1409 has a structure in which the first conductive layer 1403 and the second conductive layer 1402 overlap each other. The p-channel transistor 1303 is a single drain transistor without an LDD. In the case of forming the p-channel transistor 1303, boron or the like is added to the impurity region 1412 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 1412, an n-channel transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 1405 and the gate insulating layer 1408 is excited by microwaves, has an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by the treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and the interface between the semiconductor layer 1405 and the gate insulating layer 1408 is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.). The defect level of can be reduced. Further, by performing this treatment on the gate insulating layer 1408, the insulating layer can be densified. That is, the generation of charged defects can be suppressed and fluctuations in the threshold voltage of the TFT can be suppressed.

  In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 1408. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 1405 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 1408 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 1304. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 13 and 14, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 14A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  13 and 14, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used as the first conductive layer, and a tungsten film can be used as the second conductive layer.

  The first conductive layer may be formed so that both ends thereof are aligned when the gate wiring is formed using the second conductive layer. As a result, a fine gate wiring can be formed. Further, it is not necessary to form the LDD overlapping the gate electrode in a self-aligning manner.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same process using a photomask or reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be divided. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  The LDD formed by combining the conductive layers having different film thicknesses in this embodiment varies in doping concentration if there is a variation in film thickness. If the doping concentration varies, the electrical characteristics of the TFT vary. If the electrical characteristics of TFTs vary, the electrical characteristics of semiconductor devices such as display devices and logic circuit devices vary. If there is a variation in the electrical characteristics of the semiconductor device, the productivity is lowered. Therefore, it is necessary to confirm that the variation does not become a problem. When used in an oscillation circuit for evaluation of the present invention formed by combining conductive layers having different thicknesses simultaneously with a semiconductor device, it can be easily confirmed that variation is small, and elements having different forms can be obtained. It can be built and integrated without increasing the number of processes.

  In this embodiment, the plurality of evaluation oscillation circuits are different from each other in the electrical characteristics of the semiconductor elements constituting the evaluation oscillation circuits.

  In a display device, a semiconductor element constituting a pixel and a semiconductor element constituting a driver for controlling the operation of the pixel have different electrical characteristics by changing the thickness of the gate insulating film, changing the doping concentration, or changing the channel length. May have specific characteristics.

  In addition, the semiconductor elements constituting the driver do not have the same channel width (direction perpendicular to the channel length) of the semiconductor elements depending on the required current.

  In the present embodiment, two output circuits, ie, two evaluation oscillation circuits made up of semiconductor elements constituting a pixel and two evaluation oscillation circuits made up of semiconductor elements forming a driver, are combined to provide four outputs for one measurement terminal. A description will be given of the case where the oscillation circuit for evaluation of the present invention is configured by being connected to. The number of oscillation circuits for evaluation composed of semiconductor elements constituting pixels and the number of two types of oscillation circuits for evaluation composed of semiconductor elements constituting drivers is not limited to two. If the purpose is to evaluate the variation, the number of the two types of oscillation circuits for evaluation may be two or more, and if only the oscillation frequency is obtained, one may be used. The two types of evaluation oscillation circuits are not limited to the semiconductor elements constituting the pixel and the semiconductor elements constituting the driver, but are examples of different electrical characteristics.

  If there is no variation in the electrical characteristics in the configuration of this embodiment, the measurement is performed by applying a probe to the measurement terminal and Fourier transform is performed. Then, the oscillation frequency of the oscillation circuit for evaluation by the semiconductor element constituting the pixel and the semiconductor element constituting the driver Thus, two oscillation frequencies of the oscillation circuit for evaluation can be obtained.

  In the configuration of this embodiment, measurement is performed when two evaluation oscillation circuits made of semiconductor elements constituting a pixel have different oscillation frequencies and two evaluation oscillation circuits made of semiconductor elements constituting a driver have different oscillation frequencies. Four oscillation frequencies can be obtained by applying a probe to the terminal for measurement and Fourier transform. On the contrary, when four oscillation frequencies are obtained in the configuration of this embodiment, it can be seen that there are variations in the semiconductor elements including the wirings constituting the respective evaluation oscillation circuits.

  As shown in the present embodiment, the present invention can be applied to a plurality of evaluation oscillation circuits even if the electrical characteristics of the semiconductor elements constituting each evaluation oscillation circuit are different.

It is the figure which showed the structure of this invention It is a block diagram which shows another form of this invention. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 4 is a diagram showing a waveform of a potential change at a node 303 in FIG. 3 measured when a plurality of oscillation circuits oscillate at different frequencies. It is the figure which carried out the Fourier transform of the waveform shown in FIG. FIG. 4 is a diagram showing a waveform of a potential change at a node 303 in FIG. 3 measured when a plurality of oscillation circuits oscillate at the same frequency. It is the figure which carried out the Fourier transform of the waveform shown in FIG. FIG. 4 is a circuit diagram changed to a structure for synchronizing the ring oscillator shown in FIG. 3. FIG. 6 is a diagram showing a configuration of a conventional evaluation oscillation circuit 1 is a layout of a semiconductor layer of a semiconductor device of the present invention. 1 is a layout of a gate electrode or a gate wiring layer of a semiconductor device of the present invention. 1 is a layout of a wiring layer of a semiconductor device of the present invention. It is a figure which shows the cross-section of a transistor It is a figure which shows the upper surface of a transistor Diagram of a semiconductor device according to the present invention

Explanation of symbols

100 Measurement terminal 101 Evaluation oscillation circuit 102 Wiring 200 Measurement terminal 201 Evaluation oscillation circuit 202 Element 301 Output buffer 302 Resistance element 303 Node 304 Ring oscillator 500 Maximum 700 Maximum 701 Maximum 800 Node 801 NAND
802 Node 900 Measurement terminal 901 Evaluation oscillation circuit 902 Wiring 1000 Semiconductor layer 1100 Gate wiring 1200 Pattern 1301 n-channel TFT
1302 n-channel TFT
1303 p-channel transistor 1304 capacitor element 1305 resistance element 1402 conductive layer 1403 conductive layer 1404 wiring 1405 semiconductor layer 1406 impurity region 1407 impurity region 1408 insulating layer 1409 gate electrode 1410 impurity region 1411 impurity region 1412 impurity region 1500 substrate 1501 display device 1502 evaluation Oscillator circuit 1510 Measurement terminal 1511 Oscillator circuit 1512 Common wiring

Claims (5)

One measurement terminal, first and second evaluation oscillation circuits ,
A semiconductor device having a transistor ,
The measurement terminal is shared by the first and second evaluation oscillation circuits,
The first evaluation oscillation circuit is electrically connected to the measurement terminal via a resistor or a capacitor,
The second evaluation oscillation circuit is electrically connected to the measurement terminal via a resistor or a capacitor ,
The element substrate wherein the transistors included in the first and second evaluation oscillation circuits are manufactured in the same process as the transistor included in the semiconductor device . One measurement terminal, first and second evaluation oscillation circuits ,
A semiconductor device having a transistor ,
The measurement terminal is shared by the first and second evaluation oscillation circuits,
The first evaluation oscillation circuit is electrically connected to the measurement terminal via a resistor or a capacitor,
The second evaluation oscillation circuit is electrically connected to the measurement terminal via a resistor or a capacitor,
The measuring pin, Available Power supply terminal, a ground terminal, or a control input,
The element substrate wherein the transistors included in the first and second evaluation oscillation circuits are manufactured in the same process as the transistor included in the semiconductor device . In claim 1 or claim 2 ,
The element substrate, wherein the measurement terminal and the first and second evaluation oscillation circuits are arranged around the semiconductor device. In claim 1 or claim 2 ,
The element substrate, wherein the measurement terminal and the first and second evaluation oscillation circuits are arranged inside the semiconductor device. In any one of Claims 1 thru | or 4 ,
The element substrate, wherein the measurement terminal and the first and second evaluation oscillation circuits are disconnected from the semiconductor device.

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