JP5005416B2 - Multilayer wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer wiring board and a manufacturing method thereof, and more particularly to a multilayer wiring board having a stacked via structure in which a plurality of vias are stacked in a vertical direction and interconnected, and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, there is a multilayer wiring board having a stacked via structure in which a plurality of vias are stacked and interconnected in a vertical direction. As shown in FIG. 1, in an example of a wiring board having a conventional stack via structure, a first interlayer insulating layer 300 is provided on a lower wiring layer 200 provided on a board 100. The first interlayer insulating layer 300 is provided with a first via hole VH1 that reaches the lower wiring layer 200. A first via pad 400 having a flat upper surface is formed on the first interlayer insulating layer 300 in the vicinity thereof from within the first via hole VH1.

  In addition, a second interlayer insulating layer 320 having a second via hole VH2 is formed on the first via pad 400, and the upper surface is flat on the second interlayer insulating layer 320 in the vicinity from the second via hole VH2. A second via pad 420 is formed.

  Further, a third interlayer insulating layer 340 having a third via hole VH3 is formed on the second via pad 420, and the upper wiring layer 220 connected to the second via pad 420 via the third via hole VH3 It is formed on the three interlayer insulating layer 340.

  As described above, the first to third via holes VH1 to VH3 are stacked in the vertical direction, and the lower wiring layer 200 includes the first and second via pads filled in the first and second via holes VH1 and VH2. The upper wiring layer 220 is electrically connected through 400 and 420. That is, the lower wiring layer 200 penetrates the first to third interlayer insulating layers 300, 320, and 340 and is electrically connected to the upper wiring layer 220.

  By adopting such a stacked via structure, interlayer connection can be achieved with a smaller area, so that a small wiring board capable of accommodating high-density mounting can be manufactured.

In Patent Document 1, in a method for manufacturing a multilayer printed wiring board, an opening having a roughened wall surface is formed in an interlayer insulating layer, and an uneven electroless plating film is formed along the rough surface of the opening. Later, it is described that a filled via hole made of copper is formed in the opening based on electrolytic plating, thereby preventing peeling and cracking of the filled via hole.
Japanese Patent Laid-Open No. 11-243279

  By the way, with the higher integration and higher performance of semiconductor chips (LSI chips), the density of wiring boards for mounting them is being increased. In such a wiring board, when heat is applied in the manufacturing process or the actual use environment, the expansion and contraction is repeated due to the thermal stress generated by the difference in the thermal expansion coefficient between different materials, and the reliability of interlayer connection tends to be a problem. In particular, in the interlayer via portion having the stacked via structure described above, stress tends to concentrate on the connecting portion (A portion in FIG. 1) between the upper surface of the lower via pad 400 and the lower outer peripheral portion of the upper via pad 420. As a result, disconnection or cracks may occur, causing a reduction in the yield of the wiring board.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer wiring board having a stacked via structure that can provide highly reliable interlayer connection, and a method for manufacturing the same.

In order to solve the above problems, the present invention relates to a multilayer wiring board, comprising: a board provided with a wiring layer; an interlayer insulating layer formed on the wiring layer and provided with a via hole reaching the wiring layer; A stacked via structure in which a plurality of interlayer connection structures each including a via pad formed on the interlayer insulating layer in the vicinity thereof from within a via hole is stacked, and the plurality of via pads are stacked in a vertical direction to be interconnected. And the via pad is formed integrally with a portion disposed in the via hole and a portion disposed on the interlayer insulating layer, and in the plurality of via pads, a peripheral edge is formed at a central portion of the upper surface of each via pad. a concave portion recessed are provided from section, and the bottom of the upper of said via pads are arranged respectively on a bottom surface of the recess of the lower side of the via pad, the upper via The lowermost portion of the pad is disposed with an interval inward from the side surface of the concave portion of the lower via pad, the interlayer insulating layer is provided in a ring shape at the interval, and the via hole is an upper portion It is characterized by a forward tapered shape in which the diameter decreases from the bottom to the bottom .

  The multilayer wiring board of the present invention has a stacked via structure in which a plurality of via pads are stacked and interconnected in the vertical direction. A concave portion is provided in the center of the upper surface of each via pad, and the lowermost portion of the upper via pad is disposed on the bottom surface of the concave portion of the lower via pad.

  In the present invention, the depth of the via hole of the interlayer insulating layer is set deeper on the via pad recess than on the peripheral edge by providing the recess in the center of the upper surface of the via pad. Since the via hole is formed in a forward tapered shape whose diameter decreases from the top to the bottom, when forming a via hole of the same design rule, the uppermost via hole has a flat top surface of the lower via pad. The diameter is smaller than the case, depending on the depth of the recess. As a result, even in the via pad filled in the via hole, the diameter of the lowermost part is formed thinner than when the upper surface of the lower via pad is flat.

  For this reason, when a plurality of stacked via pads are viewed as one via post, each connecting portion between the via pads is thinned to form a soft column. In addition, since the bottom surface of the concave portion of the lower via pad where the lowermost portion of the upper via hole is disposed is recessed below the peripheral edge portion, even if the peripheral edge portion of the via pad is deformed by stress, the bottom surface of the concave portion The stress applied to is relaxed.

  As a result, even if heat is applied to the multilayer wiring board and stress is generated, it is avoided that stress is concentrated on the connection portion between the bottom surface of the concave portion of the lower via pad and the lower outer peripheral portion of the upper via hole. Is distributed, a highly reliable interlayer connection can be obtained.

  In addition, when the lowermost portion of the upper via pad is disposed on the bottom surface of the concave portion of the lower via pad and spaced from the side surface to the inner side, the lower side surface of the upper via pad and the side surface of the concave portion of the lower via pad The gap is filled with an interlayer insulating layer. Thereby, the adhesion between the via pad and the interlayer insulating layer can be improved by the anchor effect, and the reliability of the interlayer connection can be improved.

  In the above-described invention, the upper wiring layer electrically connected to the upper via pad of the stacked via structure is formed, and the lower wiring layer is electrically connected to the upper wiring layer through the plurality of via pads. The

  Further, a via pad having a recess at the center of the upper surface is formed in the via hole based on a plating method, and a via pad having a recess disposed on the via hole can be obtained by adjusting the plating conditions (time). . Alternatively, after forming a via pad having a flat upper surface on the via hole, the central portion of the upper surface may be processed to form a recess.

  As described above, according to the present invention, in the stack via structure of the multilayer wiring board, the concave portion is provided in the central portion of the upper surface of the via pad, so that stress concentrated on the connection portion of the plurality of via pads can be relieved, and the interlayer connection Reliability can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  2 is a cross-sectional view showing a multilayer wiring board having a stacked via structure according to an embodiment of the present invention, and FIG. 3 is a perspective view schematically showing a state in which a plurality of via pads according to the embodiment of the present invention are stacked.

  As shown in FIG. 2, in the multilayer wiring board having the stack via structure of the present embodiment, a first wiring layer 20 is formed on an insulating substrate 10 made of resin or the like. A first interlayer insulating layer 30 is formed on the first wiring layer 20, and a first via hole VH 1 reaching the connection portion of the first wiring layer 20 is provided in the first interlayer insulating layer 30.

  A first via pad 40 is formed on the first interlayer insulating layer 30 in the vicinity of the first via hole VH1. The first via pad 40 is formed by burying the main part of the first via hole VH1, and the diameter D1 of the pad part is set larger than the diameter D2 of the upper part of the first via hole VH1. A recess C is provided at the center of the upper surface of the first via pad 40, and the center of the upper surface is recessed below the peripheral edge. As will be described later, the concave portion C of the first via pad 40 is provided in order to relieve stress applied to the via pad when configuring the stacked via structure and improve the reliability of interlayer connection. The depth of the recess C of the first via pad 40 is set to 5 to 20 μm (preferably 5 to 10 μm).

  The first via hole VH1 is formed in a forward tapered shape whose diameter decreases from the upper part to the lower part because the first interlayer insulating layer 30 is processed by laser or dry etching (RIE or the like). The taper angle (inclination angle) θ of the first via hole VH1 (first via pad 40) is set between 45 and 90 ° (for example, 60 to 80 °). As an example of the dimensions of the first via hole VH1, the upper diameter D2 is set to 40 to 120 μm, the lower diameter D3 is set to 30 to 100 μm, and the height H is set to 10 to 200 μm.

  A second wiring layer 22 that is separated from the first via pad 40 and is independent is formed on the first interlayer insulating layer 30.

  Further, a second interlayer insulating layer 32 is formed on the first via pad 40, and a second via hole VH 2 reaching the first via pad 40 is provided in the second interlayer insulating layer 32. The second via hole VH2 is formed in the same shape as the first via hole VH1, and the lowermost portion thereof is disposed on the bottom surface in the recess C of the first via pad 40 with a space S from the side surface to the inside. In addition, a second via pad 42 having a recess C provided at the center of the upper surface of the same structure as the first via pad 40 is formed on the second interlayer insulating layer 32 in the vicinity thereof from within the second via hole VH2.

  As a result, the lowermost portion of the second via pad 42 is disposed on the bottom surface of the recess C of the first via pad 40. In addition, the second interlayer insulating layer 32 is filled in a ring shape in the interval S between the lower side surface of the second via pad 42 and the side surface of the recess C of the first via pad 40. The interval S is set to 5 to 10 μm, for example. An independent third wiring layer 24 is formed on the second interlayer insulating layer 32 separately from the second via pad 42.

  Further, similarly, a third interlayer insulating layer 34 is formed on the second via pad 42, and a third via hole VH 3 reaching the second via pad 42 is provided in the third interlayer insulating layer 34. The third via hole VH3 is also formed in the same shape as the first via hole VH1, and its lowermost portion is disposed on the bottom surface in the recess C of the second via pad 42. Similarly, on the third interlayer insulating layer 34 in the vicinity thereof from within the third via hole VH3, a third via pad 44 having a recess C provided at the center of the upper surface of the same structure as the first via pad 40 is formed. . An independent fourth wiring layer 26 is formed on the third interlayer insulating layer 34 separately from the third via pad 44.

  Furthermore, similarly, a fourth interlayer insulating layer 36 is formed on the third via pad 44, and a fourth via hole VH 4 reaching the third via pad 44 is provided in the fourth interlayer insulating layer 36. The fourth via hole VH 4 is also formed in the same shape as the first via hole VH 1, and the lowermost part is disposed on the bottom surface in the recess C of the third via pad 44. A fifth wiring layer 28 (upper wiring layer) connected to the third via pad 44 through the fourth via hole VH4 is formed on the fourth interlayer insulating layer 36.

  Thus, one interlayer connection structure is constituted by the first interlayer insulating layer 30 provided with the first via hole VH1 on the first wiring layer 20 and the first via pad 40 provided in the first via hole VH1. Has been. A plurality of the interlayer connection structures are stacked, and the first to third via pads 40, 42, and 44 are stacked in the vertical direction and connected to each other, thereby forming the stacked via structure 5.

  In the first to third via pads 40, 42, and 44, the lowermost portion of the upper via pad is disposed on the bottom surface of the lower via pad recess C, and the lower side surface of the upper via pad and the lower via pad recess C Each interlayer insulating layer 30, 32, 34 is provided in a ring shape at a distance S from the side surface.

  The first wiring layer 20 is electrically connected to the fifth wiring layer 28 through the laminated first to third via pads 40, 42, and 44. That is, the first wiring layer 20 is electrically connected to the fifth wiring layer 28 through the four stacked first to fourth interlayer insulating layers 30 to 36.

  FIG. 3 schematically illustrates an example in which five via pads are stacked. As shown in FIG. 3, a plurality of via pads 40 each having a recess C at the center of the upper surface are stacked in a state where the recesses C are on the upper side, and the lower part of each upper via pad 40 is on the lower side. It arrange | positions so that it may sink in the recessed part C of each via pad 40. FIG. Thus, one columnar via post penetrating through a plurality of layers is formed. FIG. 3 shows an example in which the uppermost via pad 40 serves as a connection electrode, and the upper surface of the uppermost via pad 40 is flat.

  By adopting such a stacked via structure, interlayer connection can be achieved in a smaller area, so that the density of the multilayer wiring board can be increased and it can be used as a mounting board for high-performance semiconductor chips. it can.

  In FIG. 2, five-layer wiring (first to fifth wiring layers 20, 22, 24, 26, and 28) is formed on the substrate 10, and the first wiring layer 20 and the fifth wiring layer 28 are stacked. Although the form connected via via structure 5 was illustrated, the number of lamination of via pads can be set arbitrarily. The first wiring layer 20 may be formed on an arbitrary interlayer insulating layer on the substrate 10.

  Also, a laminated wiring layer having the stack via structure 5 having the same configuration may be formed on the lower surface side of the core substrate 10 so as to be symmetric with respect to the substrate 10 as an axis. In the case of this form, a through electrode is provided on the substrate 10 and the wiring layers on both sides are interconnected via the through electrode. In this case, the stacked via structure formed on the lower surface side of the core substrate 10 has the same shape of the via holes and via pads as the above-described structure when the substrate 10 is turned upside down. Absent.

  By the way, various heat is applied to the multilayer wiring board in the manufacturing process, when a semiconductor chip is mounted thereon, or in an actual use environment. At this time, in the multilayer wiring board, since materials having different thermal expansion coefficients (wiring layers, interlayer insulating layers, semiconductor chips mounted thereon, etc.) are mixed, the expansion and contraction is repeated due to the generation of thermal stress. In particular, in the stacked via structure, stress tends to concentrate on the connection portion of the via pad, and cracks may occur in the via pad and the interlayer insulating layer, so that sufficient reliability of the interlayer connection may not be obtained.

  In the stacked via structure 5 of the multilayer wiring board of the present embodiment, as described above, the concave portion C is provided in the center of the upper surface of each of the stacked via pads 40, 42, 44, and the lowermost portion of the upper via pad is the lowermost portion. They are respectively arranged on the bottom surfaces of the recesses C of the lower via pads. Thereby, on the via pad, the thickness of the interlayer insulating layer is set to be thicker on the recess C than on the peripheral edge by the depth of the recess C.

  Since the via hole is formed in a forward tapered shape whose diameter decreases from the upper part to the lower part, when forming a via hole having the same design rule, the lowermost part of the via hole of this embodiment is the upper surface of the lower via pad. Is formed with a smaller diameter than in the case of flat. As a result, also in the via pad filled in the via hole, the diameter of the lowermost part is set to be thinner than when the upper surface of the lower via pad is flat.

  Therefore, when the first to third via pads 40, 42, 44 and the fifth wiring layer 28 in the fourth via hole VH4 in FIG. 2 are viewed as one via post, the space between each via pad 40, 42, 42 is as follows. The connecting portion is thinner than the case where the upper surface of the via pad is flat, and a soft column is formed. In addition, since the bottom surface of the recess C of the lower via pad in which the lowermost portion of the upper via hole is disposed is recessed below the periphery, the recess C is formed even if the periphery of the via pad is deformed by stress. The stress applied to the bottom surface (the connecting portion A between the via pads (FIG. 2)) is relaxed.

  For this reason, even if thermal stress occurs in the multilayer wiring board, stress is dispersed by avoiding stress concentration at the connection portion between the bottom surface of the recess of the via pad and the lower outer periphery of the via hole. It will be.

  As described above, in the stacked via structure 5 of the multilayer wiring board according to the present embodiment, the concave portion is provided in the central portion of the upper surface of the via pad, and the lowermost portion of the upper via hole is disposed on the bottom surface of the concave portion. Since stress applied to the via pad is dispersed and relaxed, a highly reliable interlayer connection can be obtained.

  Further, since the interlayer insulating layer is filled in a ring shape in the space S between the lower side surface of the upper via pad and the side surface of the recess C of the lower via pad, the adhesion between the via pad and the interlayer insulating layer is achieved by the anchor effect. And high reliability of interlayer connection is ensured.

  The inventor of the present application performed a simulation to confirm the effect of the stacked via structure according to the present embodiment. Assuming that the stack via structure according to this embodiment is subjected to a thermal cycle in the range of 180 ° C. (20 to 200 ° C.), a connection portion between the upper surface of the lower via pad and the lower outer peripheral portion of the upper via pad The stress applied in the vicinity was analyzed with an axisymmetric model.

  A comparison was made between the case where the surface of the via pad is flat (prior art) and the case where a recess is provided in the center of the upper surface of the via pad (this embodiment). By normalizing so that the maximum value becomes 1 in the stress applied to the inside of the stacked via structure, 0 to 0.2, 0.2 to 0.4, 0.4 to 0.6, 0 The stress distribution inside the stacked via structure was calculated by dividing into five stress intensities of .6 to 0.8 and 0.8 to 1.

  As shown in FIG. 4, when the surface of the via pad is flat (conventional technology), the surface layer portion A in the vicinity of the connection portion between the upper surface of the lower via pad and the lower outer periphery of the upper via pad is set to 0.8 It was confirmed that a considerably large stress of ˜1 was applied. A stress of 0.6 to 0.8, which is weaker than that of the surface layer portion A, is applied to the surface layer portion B inside the surface layer portion A, and further, a stress of 0.4 to 0.6 which is weaker than that of the surface layer portion B is applied to the inner surface layer portion C. Has been confirmed. Further, it was confirmed that a stress of 0.2 to 0.4 was applied to the inner surface layer portion D from the surface layer portion C, and a stress of 0 to 0.2 was applied to the inner surface layer portion E.

  Thus, when the surface of the via pad is flat (prior art), the stress is reduced as it enters the stacked via structure, but the connection between the upper surface of the lower via pad and the lower outer periphery of the upper via hole. It was found that a considerably large stress is applied to the surface layer portion A in the vicinity of the portion. For this reason, in the conventional stack via structure, disconnection and cracks may occur due to stress, and reliability of interlayer connection may become a problem.

  On the other hand, as shown in FIG. 5, in the case where a recess is provided in the central portion of the upper surface of the via pad (this embodiment), the connection portion between the bottom surface of the recess of the lower via pad and the lower outer peripheral portion of the upper via pad. It was found that the surface layer portion A in the vicinity of is applied with a stress of 0.4 to 0.6, and the stress is reduced to about half that of the prior art. A stress of 0.2 to 0.4 is applied to the surface layer portion B inside the surface layer portion A, and a stress of 0 to 0.2 is applied to the inner surface layer portion C, and the stress is also reduced in the thickness direction. I found out that it would be.

  Next, a method for forming the stacked via structure of the multilayer wiring board according to the present embodiment will be described. As shown in FIG. 6A, first, a substrate 10 made of an insulating material such as a resin provided with a first wiring layer 20 is prepared. Thereafter, a first interlayer insulating layer 30 that covers the first wiring layer 20 is formed on the substrate 10 by sticking a resin film such as an epoxy resin. Further, as shown in FIG. 6B, the first via hole reaching the connecting portion of the first wiring layer 20 by processing the first interlayer insulating layer 30 by laser, photolithography and etching (RIE, etc.). VH1 is formed. At this time, the first via hole VH1 is formed in a forward tapered shape whose diameter decreases from the top to the bottom.

  Subsequently, as shown in FIG. 6C, a seed layer 40 a made of copper or the like is formed in the first via hole VH <b> 1 and on the first interlayer insulating layer 30. Next, as shown in FIG. 7A, a resist 12 having an opening 12x is formed in a portion where the first via pad is disposed. Subsequently, as shown in FIG. 7B, a metal plating layer 40b made of copper or the like is formed by electrolytic plating using the seed layer 40a as a plating power feeding path.

  At this time, by adjusting the plating condition (time), the metal plating layer 40b in the opening 12x of the resist 12 is embedded in the main part of the first via hole VH1, and the concave part C recessed from the peripheral part is formed in the central part. To be provided. That is, when the metal plating layer 40b grown from the inner surface of the first via hole VH1 is sufficiently formed, the upper surface becomes flat. However, before the upper surface becomes flat by adjusting the plating conditions (time). Finish plating.

  Next, as shown in FIG. 7C, after removing the resist 12, the seed layer 40a is removed by etching using the metal plating layer 40b as a mask. As a result, the first via pad 40 having the concave portion C provided in the central portion of the upper surface as described above is formed on the first interlayer insulating layer 30 in the vicinity thereof from within the first via hole VH1. The first via pad 40 includes a seed layer 40a and a metal plating layer 40b.

  Thereafter, by repeating the steps of FIG. 6A to FIG. 7C, the same shape of the via pad is stacked on the concave portion C of the first via pad 40, and the above-described view is obtained. A multilayer wiring board having the stack via structure 5 shown in FIG. 2 can be manufactured.

  As another method of forming the first via pad 40, as shown in FIG. 8A, first, in the step of FIG. 7B, electrolytic plating is performed until the upper surface of the metal plating layer 40b becomes flat. Further, as shown in FIG. 8B, after the resist 12 is removed, the seed layer 40a is etched and removed using the metal plating layer 40b as a mask, thereby obtaining a first via pad 40x having a flat upper surface.

  Further, as shown in FIG. 8C, a resist 14 having an opening 14x is formed on the center of the upper surface of the first via pad 40x. Subsequently, as shown in FIG. 9A, the first via pad 40x in the opening 14x is removed by dry etching or laser processing using the resist 14 as a mask, and then the resist 14 is removed. As a result, as shown in FIG. 9B, the first via pad 40 in which the concave portion C is provided at the center of the upper surface similar to FIG. 7C is obtained.

  7A, the metal plating layer 40b is formed on the entire seed layer 40a without forming the resist 12, and then the resist is patterned, and then the resist is used as a mask for metal plating. The first via pad 40 having the similar recess C may be formed by etching the layer 40b and the seed layer 40a.

FIG. 1 is a cross-sectional view showing an example of a multilayer wiring board having a stack via structure of the prior art. FIG. 2 is a cross-sectional view showing a multilayer wiring board having a stacked via structure according to an embodiment of the present invention. FIG. 3 is a perspective view schematically showing a state in which a plurality of via pads according to the embodiment of the present invention are stacked. FIG. 4 is a diagram showing the stress distribution of the stacked via structure when the upper surface of the via pad is flat (prior art). FIG. 5 is a diagram showing the stress distribution of the stacked via structure in the case where a recess is provided in the central portion of the upper surface of the via pad (this embodiment). 6A to 6C are cross-sectional views (No. 1) showing the method for forming the via pad according to the embodiment of the present invention. 7A to 7C are cross-sectional views (part 2) showing the method for forming the via pad according to the embodiment of the present invention. 8A to 8C are cross-sectional views (part 1) showing another method of forming the via pad according to the embodiment of the present invention. 9A and 9B are cross-sectional views (part 2) showing another method of forming the via pad according to the embodiment of the present invention.

Explanation of symbols

5 ... Stack via structure, 10 ... Substrate, 12, 14 ... Resist, 12x, 14x ... Opening, 20 ... First wiring layer, 22 ... Second wiring layer, 24 ... Third wiring layer, 26 ... Fourth wiring layer , 28 ... fifth wiring layer, 30 ... first interlayer insulating layer, 32 ... second interlayer insulating layer, 34 ... third interlayer insulating layer, 36 ... fourth interlayer insulating layer, 40 ... first via pad, 40a ... seed layer 40b ... metal plating layer, 42 ... second via pad, 44 ... third via pad, VH1 ... first via hole, VH2 ... second via hole, VH3 ... third via hole, VH4 ... fourth via hole, C ... concave, S ... interval .

Claims (6)

A substrate with a wiring layer;
An interlayer connection comprising an interlayer insulating layer formed on the wiring layer and provided with a via hole reaching the wiring layer, and a via pad formed on the interlayer insulating layer in the vicinity from within the via hole A stacked via structure in which a plurality of structures are stacked and a plurality of the via pads are stacked and interconnected in a vertical direction;
In the via pad, a portion disposed in the via hole and a portion disposed on the interlayer insulating layer are integrally formed, and in the plurality of via pads, the via pad is depressed from the peripheral portion at the center of the upper surface of each via pad. A concave portion is provided, and a lowermost portion of the upper via pad is disposed on a bottom surface of the concave portion of the lower via pad,
The lowermost portion of the upper via pad is disposed with an interval inward from the side surface of the recess of the lower via pad, and the interlayer insulating layer is provided in a ring shape in the interval, and
The multilayer wiring board according to claim 1, wherein the via hole has a forward tapered shape with a diameter decreasing from the top to the bottom . An upper wiring layer electrically connected to the uppermost via pad of the stacked via structure;
The multilayer wiring board according to claim 1 , wherein the wiring layer is electrically connected to the upper wiring layer through the plurality of via pads. Preparing a substrate with a wiring layer;
Forming an interlayer insulating layer on the wiring layer; forming a via hole reaching the wiring layer by processing the interlayer insulating layer; and on the interlayer insulating layer in the vicinity thereof from within the via hole. Forming an interlayer connection structure by forming a via pad, and stacking the interlayer connection structure to obtain a stacked via structure in which a plurality of the via pads are stacked in a vertical direction to be interconnected. And
In the step of obtaining the stacked via structure, a concave portion recessed from the peripheral edge portion is provided at the center of the upper surface of each via pad, the lowermost portion of the upper via pad is disposed on the bottom surface of the concave portion of the lower via pad, and
The via pad is integrally formed with a portion arranged in the via hole and a portion arranged on the interlayer insulating layer,
In the step of forming the via hole, a lowermost portion of the via hole is disposed inwardly from a side surface of the concave portion of the lower via pad, and in the step of forming the via pad, the lower side surface of the via pad and the lower side of the via pad are formed. The interlayer insulating layer is arranged in a ring shape between the side surface and the space of the concave portion of the via pad on the side, and
In the step of forming the via hole, laser or etching is employed, and the via hole is formed in a forward tapered shape whose diameter decreases from the upper part to the lower part . After the step of obtaining the stacked via structure, the method further includes a step of forming an upper wiring layer electrically connected to the uppermost via pad.
The method of manufacturing a multilayer wiring board according to claim 3 , wherein the wiring layer is electrically connected to the upper wiring layer through the plurality of via pads. In the step of forming the via pad,
5. The multilayer wiring board according to claim 3 , wherein the via pad is formed based on a plating method, and the via pad in which the concave portion is disposed on the via hole is obtained by adjusting a plating condition. Manufacturing method. The step of forming the via pad includes
Forming a via pad having a flat upper surface on the interlayer insulating layer in the vicinity thereof from within the via hole;
5. The method of manufacturing a multilayer wiring board according to claim 3 , further comprising: forming the via pad provided with the concave portion by processing and removing a central portion of the upper surface of the via pad.

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