JP5086817B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device mounting configuration in which a modulation / demodulation circuit mounted on a mobile phone is formed.

  Japanese Laid-Open Patent Publication No. 2003-46207 (Patent Document 1) relates to a wiring board and an electronic device, and describes a technique applicable to, for example, mounting a CSP (Chip Size Package) semiconductor integrated circuit. Specifically, Patent Document 1 has an object of enabling connection with a land by a wiring pattern that is much wider than in the past. In order to achieve this object, the wiring patterns are connected to only a part of the lands, and the wiring patterns are formed to extend symmetrically about the lands.

Japanese Patent Laying-Open No. 2003-338666 (Patent Document 2) describes a technique for obtaining a printed circuit board having improved bending rigidity. Specifically, a solid pattern is formed on a central insulating substrate where the printed wiring board side land is not disposed, and a solder resist having an opening at the top of the solid pattern is formed while covering the solid pattern. The Ni / Au plating film is formed on the solid pattern exposed from the opening of the solder resist. With such a configuration, Ni (nickel) having a higher hardness than the solder resist is formed on the solid pattern, so that the bending rigidity of the printed wiring board can be improved.
JP 2003-46207 A JP 2003-338666 A

  In recent years, mobile communication devices such as GSM (Global System for Mobile Communications), PCS (Personal Communication Systems), PDC (Personal Digital Cellular), and CDMA (Code Division Multiple Access) are widely used. Is popular. In general, this type of mobile communication device includes a baseband circuit device having a function of controlling transmission and reception, a high-frequency integrated circuit device (RF (Radio Frequency) IC) having a function of modulating and demodulating a transmission / reception signal, The power amplifier is configured to amplify the input power so that it becomes the output power necessary for a call.

  As described above, the RFIC has a modulation / demodulation circuit that modulates and demodulates transmission / reception signals. The modulation / demodulation circuit and the like are formed on a semiconductor chip. Then, by packaging this semiconductor chip, the RFIC is completed as a product. The packaging of the RFIC is, for example, BGA (ball grid array). BGA is a type of IC package, and the external connection electrode from the package is made of a metal such as solder in a spherical shape and arranged in a grid pattern on the back surface of the wiring board (the surface opposite to the chip mounting surface). It is a kind of surface mount type package.

  Specifically, this BGA will be described with reference to the drawings. FIG. 24 is a cross-sectional view showing a part of the BGA 100 studied by the present inventors. As shown in FIG. 24, a conductor pattern 102 is formed on a chip mounting surface (front surface) of a base material 101 made of an insulator, and a wiring board is formed by the base material 101 and the conductor pattern. A via hole 103a is formed in the wiring board. That is, the via hole 103a is formed so as to penetrate the conductor pattern 102 and the base material 101, and a conductor film is formed on the side surface of the via hole 103a. A solder resist 104 is formed so as to cover both surfaces of the wiring board. The conductor pattern 102 is covered with the solder resist 104, and the solder resist 104 is buried in the via hole 103a. A via 103 is formed by a via hole 103a, a conductor film formed on the side surface of the via hole 103a, and a solder resist 104 that is formed on the conductor film and fills the inside of the via hole 103a. An insulating paste 105 is formed on the wiring substrate through the solder resist 104, and a semiconductor chip 106 is formed on the insulating paste 105. On the chip mounting surface side of the wiring substrate, a part of the solder resist 104 is removed, and the conductor pattern 102 formed below is exposed. A terminal 107 is formed on the conductor pattern 102 exposed by removing a part of the solder resist 104. The terminal 107 is made of, for example, a Ni / Au plating film.

  The pads (not shown) of the semiconductor chip 106 and the terminals 107 are connected by wires 108. Therefore, the semiconductor chip 106 and the conductor pattern 102 are electrically connected. The semiconductor chip 106 is sealed with a resin 109 formed on the chip mounting surface of the wiring board.

  On the other hand, external connection terminals 110 are formed on the back surface of the wiring board opposite to the chip mounting surface. That is, although the back surface of the wiring board is also covered with the solder resist 104, the solder resist 104 is removed and the external connection terminals 110 are exposed in some areas. The external connection terminal 110 is formed of a Ni / Au plating film, similarly to the terminal 107 described above. The external connection terminal 110 is electrically connected to the conductor pattern 102 formed on the chip mounting surface of the wiring board via the conductor film forming the via 103. On the external connection terminal 110, a solder ball 111 made of a metal such as solder in a spherical shape is formed. With the above configuration, the semiconductor chip 106 is electrically connected to the conductor pattern 102 formed on the chip mounting surface of the wiring board via the wire 108, and the conductor pattern 102 is wired via the via 103. It is electrically connected to the solder ball 111 formed on the back surface of the substrate. As a result, the semiconductor chip 106 is eventually electrically connected to the solder ball 111, and the semiconductor chip 106 is electrically connected to the outside by being connected to the mounting substrate via the solder ball 111. Can be connected to.

  Here, there are a plurality of conductor patterns 102 formed on the wiring board, and each of the plurality of conductor patterns 102 is electrically separated from the other conductor patterns 102 and connected to pads of different semiconductor chips 106. . Therefore, some of the plurality of conductor patterns 102 function as a power supply wiring for supplying a power supply potential to the semiconductor chip 106 and some function as a reference wiring for supplying a reference potential (GND) to the semiconductor chip 106. Furthermore, some conductor patterns 102 function as signal wirings for transmitting signals.

  Of these conductor patterns 102, attention is paid to the conductor pattern 102 that functions as a reference wiring for supplying a reference potential. Since RFIC is a circuit that handles high frequencies, it is necessary to reduce noise as much as possible. For this reason, when the impedance of the conductor pattern 102 functioning as the reference wiring is increased and has a large resistance, the reference potential fluctuates, and a stable reference potential cannot be supplied. Therefore, in the RFIC, an increase in impedance is suppressed and noise is reduced by increasing the area of the conductor pattern 102 that functions as a reference wiring. That is, the conductor pattern 102 functioning as the reference wiring has a larger area than the other conductor patterns, and is formed as a so-called solid pattern. Thereby, the reference potential can be stabilized and noise can be reduced.

  As described above, from the viewpoint of reducing noise, it is desirable to form a solid pattern that functions as a reference wiring, but the present inventor has found that a new problem arises. As shown in FIG. 24, a solder resist 104 is formed on the wiring board. When the conductor pattern 102 is formed on the wiring board, the solder resist 104 is in direct contact with the conductor pattern 102. Become. On the other hand, on the wiring board on which the conductor pattern 102 is not formed, the base material 101 and the solder resist 104 are in direct contact. At this time, for example, the conductor pattern 102 is formed of a copper film, and the adhesive force between the conductor pattern 102 and the solder resist 104 tends to be weaker than the adhesive force between the solder resist 104 and the base material 101. Therefore, when the conductor pattern 102 is formed from a large-area solid pattern, the contact area between the solid pattern and the solder resist 104 increases, and the contact area between the base material 101 and the solder resist 104 decreases. For this reason, when the solid pattern is formed, there arises a problem that the solder resist 104 is easily peeled off from the wiring board.

  An object of the present invention is to provide a technique capable of preventing peeling between a wiring board and a solder resist even when a solid pattern having a large area is formed as a conductor pattern.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment includes (a) a semiconductor chip and (b) a wiring substrate on which the semiconductor chip is mounted. At this time, the wiring board includes (b1) a flat base material, (b2) a first conductor pattern formed on the chip mounting surface of the base material, and (b3) opening the first conductor pattern. An opening reaching the surface of the substrate on the chip mounting surface side; and (b4) a protective film embedded in the opening and formed on the first conductor pattern. And the said protective film and the said base material are directly contacting in the bottom face of the said opening part, It is characterized by the above-mentioned.

  As described above, according to the representative embodiment, the first conductor pattern is configured such that the opening is provided in the first conductor pattern, and the base material and the protective film are in direct contact with each other at the bottom of the opening. Compared with the case where the first conductor pattern and the protective film are brought into contact with each other without providing an opening, the adhesive strength between the protective film and the wiring board can be improved.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a wiring board having a base material and a conductor pattern formed on the base material, an opening is provided in the conductor pattern, and the base material and the protective film are in direct contact with each other at the bottom of the opening. Even when the area becomes large, it is possible to prevent a decrease in the adhesive strength between the wiring board and the protective film.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

<Configuration and operation of mobile phone>
FIG. 1 is a block diagram illustrating a configuration of a transmission / reception unit of a mobile phone. As shown in FIG. 1, the mobile phone 1 includes an application processor 2, a memory 3, a baseband unit 4, an RFIC 5, a power amplifier 6, a SAW (Surface Acoustic Wave) filter 7, an antenna switch 8, and an antenna 9. .

  The application processor 2 is composed of, for example, a CPU (Central Processing Unit) and has a function of realizing an application function of the mobile phone 1. Specifically, the application function is realized by reading and decoding an instruction from the memory 3 and performing various operations and controls based on the decoded result. The memory 3 has a function of storing data. For example, the memory 3 is configured to store a program for operating the application processor 2 and processing data in the application processor 2. Further, the memory 3 can be accessed not only by the application processor 2 but also by the baseband unit 2 and can be used for storing data processed by the baseband unit.

  The baseband unit 4 has a CPU as a central control unit, and at the time of transmission, a baseband signal can be generated by digitally processing an audio signal (analog signal) from a user (caller) via the operation unit. It is configured. On the other hand, at the time of reception, an audio signal can be generated from a baseband signal that is a digital signal.

  The RFIC 5 is configured to generate a radio frequency signal by modulating a baseband signal at the time of transmission, and to generate a baseband signal by demodulating the reception signal at the time of reception. The power amplifier 6 is a circuit that newly generates and outputs a high-power signal similar to a weak input signal with power supplied from a power supply. The SAW filter 7 is configured to pass only signals in a predetermined frequency band from the received signal.

  The antenna switch 8 is for separating the reception signal input to the mobile phone 1 and the transmission signal output from the mobile phone 1, and the antenna 9 is for transmitting and receiving radio waves.

  The mobile phone 1 is configured as described above, and the operation thereof will be briefly described below. First, a case where a signal is transmitted will be described. A baseband signal generated by digitally processing an analog signal such as an audio signal in the baseband unit 4 is input to the RFIC 5. In the RFIC 5, the input baseband signal is converted into a radio frequency (RF (Radio Frequency) frequency) signal by a modulation signal source and a mixer. The signal converted into the radio frequency is output from the RFIC 5 to the power amplifier (RF module) 6. A radio frequency signal input to the power amplifier 6 is amplified by the power amplifier 6 and then transmitted from the antenna 9 via the antenna switch 8.

  Next, a case where a signal is received will be described. A radio frequency signal (reception signal) received by the antenna 9 passes through the SAW filter 7 and then enters the RFIC 5. The RFIC 5 amplifies the input received signal and then performs frequency conversion using a modulation signal source and a mixer. Then, the frequency-converted signal is detected and a baseband signal is extracted. Thereafter, the baseband signal is output from the RFIC 5 to the baseband unit 4. The baseband signal is processed by the baseband unit 4 and an audio signal is output.

<Configuration of RFIC>
As described above, when transmitting a transmission signal from the mobile phone 1, the RFIC 5 modulates a baseband signal to generate a radio frequency signal, and when receiving a reception signal from the mobile phone 1, the RFIC 5 It has a function of demodulating a radio frequency signal to generate a baseband signal. Next, the configuration of the RFIC 5 having such a function will be described.

  FIG. 2 is a block diagram mainly showing the internal configuration of the RFIC 5. As illustrated in FIG. 2, the RFIC 5 includes a control unit 10, an interface circuit 11, a reception unit, and a transmission unit. The control unit 10 is configured to control the reception unit and the transmission unit, and the interface circuit is a circuit for taking an interface between the RFIC 5 and the baseband unit 4.

  Next, the configuration of the receiving unit will be described. The receiving unit includes an LNA (Low Noise Amplifier) 12, a direct conversion mixer 13, a PGA (Programmable Gain Amplifier) 14, an A / D conversion circuit 15, and a digital filter 16. The LNA 12 is configured to amplify the received signal, and noise is removed as much as possible during this amplification. In other words, the LNA 12 has a function of amplifying the received signal, but noise included in the received signal is not amplified as much as possible.

  The direct conversion mixer 13 is configured to demodulate a received signal (radio frequency signal). Specifically, the direct conversion mixer 13 generates I and Q signals by orthogonally demodulating the received signal.

  The PGA 14 is configured to amplify the demodulated I and Q signals. Specifically, the PGA 14 has a function of adjusting the gain of the I and Q signals and canceling a DC component (DC offset cancellation).

  The A / D conversion circuit 15 is configured to convert an analog signal into a digital signal, and the digital filter 16 has a function of passing only a signal in a specific frequency band in the digital signal. Yes.

  Next, the configuration of the transmission unit will be described. The transmission unit includes an offset PLL (Phase Locked Loop) circuit 17, a modulator 18, and a D / A conversion circuit 19. The offset PLL circuit 17 has a function of converting a signal frequency, and the modulator 18 has a function of generating I and Q signals. The D / A conversion circuit 19 is configured to convert a digital signal into an analog signal.

  As described above, the RFIC 5 includes an analog part and a digital part. Specifically, the analog unit includes an LNA 12, a direct conversion mixer 13, and a PGA 14 that form a receiving unit, and an offset PLL circuit 17 and a modulator 18 that form a transmitting unit. On the other hand, the digital unit includes a control unit 10, an interface circuit 11, and a digital filter 16.

<Operation of RFIC>
Subsequently, the operation of the RFIC 5 will be described. First, a case where a reception signal is received will be described. As shown in FIG. 2, the reception signal received by the antenna 9 is input to the SAW filter 7 via the antenna switch 8. The SAW filter 7 passes only a received signal in a predetermined frequency band from the input received signal. Then, the signal output from the SAW filter 7 is input to the RFIC 5. The received signal input to the RFIC 5 is first amplified by the LNA 12 and then orthogonally demodulated by the direct conversion mixer 13. As a result, I and Q signals are generated from the received signal in the radio frequency band. The I and Q signals generated by the direct conversion mixer 13 are subjected to gain adjustment and DC component removal by the PGA 14. Thereafter, the I and Q signals are converted from analog signals to digital signals by the A / D conversion circuit 15. The converted digital signal is extracted by the digital filter 16 in a predetermined frequency band and input to the interface circuit 11. The digital signal input to the interface circuit 11 is subjected to signal processing and output to the baseband unit 4 as a baseband signal.

  Next, a case where a transmission signal is transmitted will be described. As shown in FIG. 2, a baseband signal (digital signal) is input from the baseband unit 4 to the RFIC 5. The baseband signal input to the RFIC 5 is subjected to signal processing by the interface circuit, and then converted from a digital signal to an analog signal by the D / A conversion circuit 19. The analog signal generated by the D / A conversion circuit 19 is modulated into I and Q signals by the modulator 18. The I and Q signals modulated by the modulator 18 are frequency-converted by the offset PLL circuit 17 to become transmission signals that are radio frequency signals. When this transmission signal is output from the RFIC 5, the power of the transmission signal is amplified by the power amplifier 6. The transmission signal whose power is amplified by the power amplifier 6 is transmitted from the antenna 9 through the antenna switch 8. In this way, the RFIC 5 operates.

<RFIC mounting configuration>
As described above, the RFIC has a function of modulating and demodulating a transmission / reception signal, and a modulation / demodulation circuit or the like that realizes this function is formed on a semiconductor chip. Then, by packaging this semiconductor chip, the RFIC is completed as a product. The packaging of the RFIC is, for example, BGA (ball grid array). BGA is a type of IC package, and the external connection electrode from the package is made of a metal such as solder in a spherical shape and arranged in a grid pattern on the back surface of the wiring board (the surface opposite to the chip mounting surface). It is a kind of surface mount type package. Hereinafter, the mounting configuration of the RFIC 5 will be described.

  FIG. 3 is a cross-sectional view showing a schematic mounting configuration (BGA) of the RFIC 5. As shown in FIG. 3, a semiconductor chip 27 is mounted on the main surface of a base material 20 to be a wiring board, and pads (not shown) of the semiconductor chip 27 and wirings on the base material 20 (not shown). Are electrically connected by a wire 29. And vias (not shown) reaching from the chip mounting surface to the back surface are formed on the base material 20, and via these vias, wiring formed on the chip mounting surface of the base material 20, Solder balls 32 formed on the back surface (surface opposite to the chip mounting surface) of the substrate 20 are connected. Therefore, since the semiconductor chip 27 is electrically connected to the solder ball 32 formed on the back surface of the base material 20, the external circuit and the semiconductor are connected by connecting to the external circuit via the solder ball 32. The chip 27 can be connected.

  4 is a plan view seen from the solder ball mounting surface of the BGA shown in FIG. That is, it is a plan view seen from the surface opposite to the BGA chip mounting surface. As shown in FIG. 4, a plurality of solder balls 32 are formed on the surface of the square base 20. The solder balls 32 are arranged in a lattice pattern inside the base material 20. A solder resist (protective film) 25 is formed between the plurality of solder balls 32 where the solder balls 32 are not formed. As described above, in the BGA, the solder balls 32 can be formed over the entire inner surface of the base material 20, so that the number of terminals made of the solder balls 32 can be increased without increasing the size of the base material 20. That is, even if the number of terminals of the semiconductor chip 27 on which the RFIC 5 is formed increases, according to the BGA, there is an advantage that the size of the base material 20 can be reduced.

  FIG. 5 is a plan view seen from the BGA solder ball mounting surface, as in FIG. 4, with the solder balls 32 and the solder resist 25 removed. As shown in FIG. 5, a plurality of external connection terminals 31 are formed on the base material 20, and the external connection terminals 31 are arranged in a lattice pattern. Solder balls are mounted on the external connection terminals 31. A via 23 is connected to each of the plurality of external connection terminals 31. A conductor pattern 31 a is formed in the plurality of vias 23 formed in the central portion of the base material 20. In this case, for example, the vias 23 connected to the same reference potential are collected in the central portion of the base material 20 and connected to each other.

  Next, FIG. 6 is a plan view seen from the chip mounting surface side of the BGA. As shown in FIG. 6, conductor patterns 21 a to 21 d are formed on the base material 20. The conductor pattern 21a functions as a reference wiring for supplying a reference potential (GND) to the analog portion shown in FIG. 2, and the conductor pattern 21b is a reference for supplying the reference potential (GND) to the digital portion shown in FIG. It functions as wiring. Furthermore, the conductor pattern 21c is an example of a signal wiring that transmits a signal, for example, and the conductor pattern 21d is an example of a power supply wiring that supplies a power supply potential, for example. Since these conductor patterns 21a to 21d function as wirings for supplying different potentials, they are electrically separated from each other. Each of the conductor patterns 21 a to 21 d is electrically connected to a terminal 28 that is formed in a plurality on the periphery of the substrate 20.

  Here, the conductor pattern 21c functioning as the signal wiring and the conductor pattern 21d functioning as the power supply wiring have a small area, and one via 23 is connected to each of the conductor patterns 21c and 21d. On the other hand, the conductor patterns 21a and 21b that function as the reference wiring have a larger area than the conductor pattern 21c that functions as the signal wiring and the conductor pattern 21d that functions as the power supply wiring. In particular, the conductor pattern 21 a that functions as a reference wiring for supplying a reference potential to the analog portion is the largest among the conductor patterns formed on the chip mounting surface side of the base material 20. A plurality of vias 23 are connected to the large-area conductor patterns 21a and 21b.

  The reason why the areas of the conductor patterns 21a and 21b that function as the reference wiring are increased is as follows. That is, in RFIC, since a high frequency circuit is formed, the necessity for reducing noise is high. At this time, if the reference potential supplied to the high-frequency circuit is unstable, it may cause noise. In particular, when the reference wiring for supplying the reference potential has a high resistance, the voltage fluctuation increases, and the reference potential becomes unstable. Therefore, from the viewpoint of stabilizing the reference potential and reducing noise, it is necessary to reduce the resistance value of the reference wiring that supplies the reference potential. For this reason, the resistance values are lowered by increasing the areas of the conductor patterns 21a and 21b functioning as the reference wiring. For this reason, the conductor patterns 21a and 21b functioning as the reference wiring have a larger area than the conductor pattern 21d functioning as the power supply wiring and the conductor pattern 21c functioning as the signal wiring. As shown in FIG. 6, the conductor pattern 21a for supplying the reference potential to the analog portion and the conductor pattern 21b for supplying the reference potential to the digital portion are electrically separated. From the viewpoint of simply reducing the resistance of the reference wiring, it is conceivable to integrate the conductor pattern 21a for supplying the reference potential to the analog portion and the conductor pattern 21b for supplying the reference potential to the digital portion. This is because by integrating, the area of the conductor pattern is further increased and the resistance can be reduced.

  However, in the present embodiment, the conductor pattern 21a that supplies the reference potential to the analog portion and the conductor pattern 21b that supplies the reference potential to the digital portion are electrically separated. This is due to the following reason. In general, a rectangular waveform signal is used in a digital circuit. This rectangular waveform signal has a steep rise or fall. Considering this from the viewpoint of Fourier analysis, the rectangular waveform contains many high-frequency components. In this case, when the reference potential is integrated in the digital part and the analog part, a high frequency component included in the rectangular waveform signal is transmitted from the digital part to the analog part, causing high frequency noise in the analog part. That is, if the reference potential is shared between the digital part and the analog part, high frequency noise in the analog part becomes large, and it becomes difficult to realize noise reduction. Therefore, the conductor pattern 21a that supplies the reference potential to the analog portion and the conductor pattern 21b that supplies the reference potential to the digital portion are electrically separated. As described above, the analog part and the digital part are electrically separated, and the area of the conductor patterns 21a and 21b is made relatively large so that noise can be reduced in both the analog part and the digital part.

  Further, in the present embodiment, the area of the conductor pattern 21a that supplies the reference potential to the analog portion is larger than the area of the conductor pattern 21b that supplies the reference potential to the digital portion. This is because in the analog portion, it is necessary to stabilize the reference potential as much as possible to prevent noise generation. Specifically, there is an LNA (low noise amplifier) as one of the analog units of the receiving unit. The LNA is a circuit to which a received signal is first input in the RFIC. In this LNA, the received signal is amplified, but it is desirable that noise is not included as much as possible during this amplification. This is because the received signal amplified by the LNA 12 is demodulated by the direct conversion mixer 13 and further amplified by a PGA (Programmable Gain Amplifier) 14 as shown in FIG. That is, when the noise is amplified by the LNA 12 that first amplifies the received signal, the noise is further amplified at a later stage, and the noise component in the received signal is increased. Therefore, it is necessary to reduce the impedance of the conductor pattern 21a by increasing the area of the conductor pattern 21a that supplies the reference potential to the analog portion where the LNA 12 is formed, and to stabilize the reference potential of the analog portion. From the above, the conductor pattern 21a has the largest area among the conductor patterns formed on the chip mounting surface of the substrate 20.

  The reason why the occupation areas of the conductor patterns 21a and 21b are increased in this way is that the conductor patterns 21a and 21b function as reference wirings for supplying a reference potential. That is, by increasing the areas of the conductor patterns 21a and 21b, the impedance of the conductor patterns 21a and 21b can be reduced, so that the reference potential can be stabilized and the generation of noise can be suppressed.

  However, when the areas of the conductor patterns 21a and 21b that function as reference wirings for supplying a reference potential are increased, there is a concern about new problems. That is, in FIG. 6, conductor patterns 21a to 21d are formed on the base material 20, but a solder resist (protective film) (illustrated in FIG. 6) is formed on the base material 20 on which the conductor patterns 21a to 21d are formed. Not formed). Therefore, in the region where the conductor patterns 21a to 21d are formed, the solder resist comes into direct contact with the conductor patterns 21a to 21d. On the other hand, the solder resist is in direct contact with the base material 20 in regions where the conductor patterns 21a to 21d are not formed. At this time, the conductor patterns 21a to 21d are formed of a copper film, and the adhesive force between the conductor patterns 21a to 21d and the solder resist is weaker than the adhesive force when the substrate 20 and the solder resist are in direct contact. Tend. For this reason, when the area is formed large like the conductor patterns 21a and 21b, the adhesion between the conductor patterns 21a and 21b and the solder resist is peeled off, and the base material 20 on which the conductor patterns 21a and 21b are formed and the solder resist are peeled off. The problem is concerned.

<Characteristic configuration of the present invention>
Therefore, in the present embodiment, the following configuration is adopted. That is, in this embodiment, as shown in FIG. 6, there is one feature in that the opening 24 is provided in the conductor patterns 21a and 21b. The opening 24 is formed so as to open the conductor patterns 21 a and 21 b and reach the underlying base material 20. That is, the surface of the base material 20 is exposed at the bottom of the opening 24. When the solder resist is formed on the conductor patterns 21 a and 21 b by forming the openings 24 in the conductor patterns 21 a and 21 b as described above, the solder resist is also embedded in the openings 24. Therefore, the solder resist embedded in the opening 24 comes into direct contact with the base material 20 exposed at the bottom of the opening 24. Therefore, when the openings 24 are not provided in the large-area conductor patterns 21a and 21b, the conductor patterns 21a and 21b and the solder resist are in direct contact, but the openings 24 are formed in the conductor patterns 21a and 21b. In the case of providing, the conductor patterns 21 a and 21 b and the solder resist are in direct contact, and the base material 20 and the solder resist are in direct contact through the opening 24. Therefore, the contact between the conductor patterns 21a and 21b and the solder resist is reinforced by not only the direct contact between the conductor patterns 21a and 21b and the solder resist, but also the direct contact between the substrate 20 and the solder resist through the opening 24. Will be. That is, since the adhesive strength between the base material 20 and the solder resist is stronger than the adhesive strength between the conductor patterns 21a and 21b and the solder resist, in this embodiment, the adhesive strength between the conductor patterns 21a and 21b and the solder resist is increased. It is possible to improve, and the peeling between the conductor patterns 21a and 21b and the solder resist can be prevented.

  In the present embodiment, from the viewpoint of stabilizing the supply of the reference potential and reducing noise, the area of the conductor patterns 21a and 21b functioning as reference wirings is changed to other conductor patterns 21c and 21d functioning as power supply wirings and signal wirings. Compared to larger. As a side effect, there is a concern that the adhesive strength between the conductor patterns 21a and 21b and the solder resist is lowered. However, by providing the opening 24 in the inner region of the large-area conductor patterns 21a and 21b, the conductor patterns 21a and 21b An area in which the base material 20 and the solder resist are in direct contact with each other through the opening 24 is provided in the inner area of 21b. Thereby, the adhesive strength between the large-area conductor patterns 21a and 21b and the solder resist can be improved. That is, in the characteristic configuration according to the present embodiment, the conductor patterns 21a and 21b functioning as the reference wiring are made large in area to reduce the resistance of the conductor patterns 21a and 21b, and the large area conductor patterns 21a and 21b are arranged. Thus, it is possible to obtain a remarkable effect that the adhesive strength between the solder resist and the solder resist can be improved.

  One of the features of the present embodiment is that an opening 24 reaching the base material 20 is provided in the conductor patterns 21a and 21b functioning as the reference wiring. It is desirable to provide a plurality of openings 24 inside the conductor patterns 21a and 21b. By providing a plurality of openings 24, the contact area between the base material 20 having a strong adhesive force and the solder resist can be increased, and the adhesive strength between the large-area conductor patterns 21a and 21b and the solder resist can be improved. Because it can. Furthermore, from the viewpoint of increasing the contact area between the base material 20 and the solder resist through the opening 24, it is desirable to make the diameter of the opening 24 larger. Specifically, by making the diameter of each opening 24 larger than the diameter of the via 23, the adhesive strength between the conductor patterns 21a and 21b and the solder resist can be sufficiently improved. In addition, although the shape of the opening part 24 is made into circular shape, it is not restricted to this, For example, it can also be made into a square or a cross shape.

  Next, the position of the opening 24 formed in the conductor patterns 21a and 21b will be described. The opening 24 is preferably formed at the center of the conductor patterns 21a and 21b. Specifically, the opening 24 is desirably formed at an inner position closer to the center than the position where the via 23 is formed in the conductor patterns 21a and 21b. The reason for this will be described. As shown in FIG. 6, the conductor patterns 21 a and 21 b are formed as large-area conductor patterns, but the conductor patterns 21 a and 21 b are connected to the terminals 28 arranged on the periphery of the base material 20. Yes. The connection between the conductor patterns 21a and 21b and the terminal 28 is connected to the terminal 28 by a thin line extending from the peripheral area of the conductor patterns 21a and 21b. Therefore, if the conductive patterns 21a and 21b are formed not in the central portion but in the peripheral region (outer edge region), the path from the thin line to the central portions of the conductive patterns 21a and 21b becomes narrow. This means that the path from the terminal 28 to the central portion of the conductor patterns 21a and 21b via the thin wire is narrowed, and the resistance value is increased. That is, if the openings 24 are provided in the outer edge regions of the conductor patterns 21a and 21b even though the conductor patterns 21a and 21b are increased in area to reduce the resistance values of the conductor patterns 21a and 21b, the conductors from the thin wires to the conductors. The path to the central part of the patterns 21a and 21b becomes narrow, and the effect of reducing the resistance value cannot be obtained sufficiently. Thus, it can be seen that, from the viewpoint of sufficiently reducing the resistance values of the conductor patterns 21a and 21b, it is desirable that the opening 24 be provided not in the outer edge region of the conductor patterns 21a and 21b but in the region near the center.

  Further, another reason why the opening 24 is provided in the center of the conductor patterns 21a and 21b will be described. For example, when the opening 24 is formed in one outer edge region of the conductor patterns 21a and 21b, the opening 24 is formed at a position close to one outer edge region of the conductor patterns 21a and 21b. The distance between the outer edge region and the other outer edge region facing the outer edge region is increased. That is, since the distance between the opposite outer edge region and the opening 24 is increased, the effect of improving the adhesive force by directly contacting the base material 20 and the solder resist through the opening 24 is improved from the opening 24 to the other. In the region of the conductor patterns 21a and 21b reaching the outer edge region, the region becomes smaller. The area extending from the opening 24 to the other outer edge area becomes a large area, and the adhesion between the conductor patterns 21a and 21b and the solder resist is mainly performed. Therefore, it is difficult to improve the adhesive force in this area. On the other hand, when the opening 24 is provided at the center of the conductor patterns 21a and 21b, the area extending from the opening 24 to both outer edge areas has a substantially equal area, and reaches from the opening 24 to one outer edge area. It can suppress that the area of an area | region becomes extremely large. For this reason, since the reinforcement | strengthening of the adhesive force by making the base material 20 and a soldering resist contact through the opening part 24 is reflected substantially uniformly over the whole conductor pattern 21a, 21b, conductor pattern 21a, 21b is effective. It is possible to improve the adhesive strength between the solder resist and the solder resist. In other words, if the opening 24 is formed so as to be biased toward one outer edge region, the adhesion strength between the conductor patterns 21a and 21b and the solder resist in the other outer edge region away from the opening 24 cannot be achieved. For the above reasons, the opening 24 is preferably formed at the center of the conductor patterns 21a and 21b. In particular, the opening 24 has the vias 23 formed in the conductor patterns 21a and 21b. It can be seen that it is desirable to form the inner position closer to the center than the position.

  Next, feature points of the present embodiment will be described again using a cross-sectional view of the BGA. FIG. 7 is a cross-sectional view showing a part of the BGA. As shown in FIG. 7, a conductor pattern 21a is formed on a chip mounting surface (front surface) of a base material 20 made of an insulator, and a wiring board is formed by the base material 20 and the conductor pattern 21a. A via hole 22 is formed in the wiring board. That is, the via hole 22 is formed so as to penetrate the conductor pattern 21 a and the base material 20, and a conductor film is formed on the side surface of the via hole 22. And the solder resist 25 is formed so that both surfaces of a wiring board may be covered. The conductor pattern 21 a is covered with the solder resist 25, and the solder resist 25 is embedded in the via hole 22. A via 23 is formed by a via hole 22, a conductor film formed on a side surface of the via hole 22, and a solder resist 25 which is formed on the conductor film and fills the inside of the via hole 22. An insulating paste 26 is formed on the wiring substrate through the solder resist 25, and a semiconductor chip 27 is formed on the insulating paste 26. On the chip mounting surface side of the wiring board, a part of the solder resist 25 is removed, and the conductor pattern 21a formed in the lower portion is exposed. A terminal 28 is formed on the conductor pattern 21 a exposed by removing a part of the solder resist 25. The terminal 28 is made of, for example, a Ni / Au plating film.

  A pad (not shown) of the semiconductor chip 27 and the terminal 28 are connected by a wire 29. Therefore, the semiconductor chip 27 and the conductor pattern 21a are electrically connected. The semiconductor chip 27 is sealed with a resin 30 formed on the chip mounting surface of the wiring board.

On the other hand, external connection terminals 31 are formed on the back surface opposite to the chip mounting surface of the wiring board. That is, although the back surface of the wiring board is also covered with the solder resist 25, the solder resist 25 is removed and the external connection terminals 31 are exposed in some areas. The external connection terminal 31 is formed of a Ni / Au plated film, like the terminal 28 described above. The external connection terminal 31 is electrically connected to the conductor pattern 21a formed on the chip mounting surface of the wiring board via the conductor film forming the via 23. On the external connection terminal 31 , a solder ball 32 made of a metal such as solder is formed into a spherical shape. From the above configuration, the semiconductor chip 27 is electrically connected to the conductor pattern 21 a formed on the chip mounting surface of the wiring board via the wire 29, and the conductor pattern 21 a is wired via the via 23. It is electrically connected to the solder balls 32 formed on the back surface of the substrate. As a result, the semiconductor chip 27 is eventually electrically connected to the solder ball 32, and the semiconductor chip 27 is electrically connected to the outside by being connected to the mounting substrate via the solder ball 32. Can be connected to.

  In the BGA configured as described above, one of the features in the present embodiment is that the conductor pattern 21a is formed on the chip mounting surface of the base material 20, and the opening 24 is formed inside the conductor pattern 21a. It is a point provided. The opening 24 penetrates the conductor pattern 21a and exposes the surface of the base 20 on the chip mounting surface side. In FIG. 7, the opening 24 is provided between the two vias 23. By providing such an opening 24, the solder resist 25 formed on the conductor pattern 21 a is also embedded in the opening 24, and the base material 20 and the solder resist 25 are in direct contact with each other at the bottom of the opening 24. It will be. From this, when the opening 24 is not provided in the large-area conductor pattern 21a, the conductor pattern 21a and the solder resist are in direct contact, but when the opening 24 is provided in the conductor pattern 21a, the conductor The pattern 21 a and the solder resist 25 are in direct contact with each other, and the substrate 20 and the solder resist 25 are in direct contact through the opening 24. For this reason, the contact between the conductor pattern 21a and the solder resist 25 is reinforced by not only the direct contact between the conductor pattern 21a and the solder resist 25 but also the direct contact between the base material 20 and the solder resist 25 through the opening 24. Will be. That is, since the adhesive strength between the base material 20 and the solder resist 25 is stronger than the adhesive strength between the conductor pattern 21a and the solder resist 25, in this embodiment, the adhesive strength between the conductor pattern 21a and the solder resist 25 is improved. And the peeling between the conductor pattern 21a and the solder resist 25 can be prevented.

  FIG. 7 shows a state where the semiconductor chip 27 is mounted on the wiring board. FIG. 8 shows a plan view at this time. FIG. 8 is a plan view showing a state in which the semiconductor chip 27 is mounted on the chip mounting surface of the base material 20 on which the conductor pattern is formed. That is, FIG. 8 is a view showing a state in which the semiconductor chip 27 is mounted on the wiring board shown in FIG. As shown in FIG. 8, the semiconductor chip 27 is mounted in the center of the base material 20 on which the conductor pattern is formed. Since the semiconductor chip 27 and the wiring substrate are bonded with an insulating paste, there is no problem even if the semiconductor chip 27 is formed on the conductor pattern. A plurality of pads 27 a are arranged side by side in the outer edge region of the semiconductor chip 27, and the pads 28 a and the terminals 28 formed on the base material 20 are connected by wires 29. The terminal 28 which is a part of the conductor pattern is formed in a region which does not overlap with the semiconductor chip 27 when the semiconductor chip 27 is mounted on the wiring board. Thereby, the pad 27 a formed on the semiconductor chip 27 and the terminal 28 formed on the base material 20 can be connected by the wire 29. Since the terminal 28 is connected to the conductor pattern formed on the base material 20, the semiconductor chip 27 and the conductor pattern formed on the base material 20 are eventually connected via the wire 29 and the terminal 28. It will be electrically connected. As described above, the BGA in the present embodiment is configured.

<Usefulness of applying the present invention to BGA>
Conventionally, QFN (Quad Fiat Non-leaded package) has been mainly used as a package form of RFIC. FIG. 9A is a plan view of the QFN 35 as viewed from the terminal formation surface (the surface opposite to the chip mounting surface). As shown in FIG. 9A, in the QFN 35, a plurality of external connection terminals 37 are formed along the outer edge region of the square wiring board 35a. A large-area conductor pattern (solid pattern) 36 for supplying a reference potential is formed in the central region of the wiring board 35a. As described above, in the QFN 35, the impedance of the conductor pattern 36 can be reduced by forming the conductor pattern 36 having a large area for supplying the reference potential to the terminal formation surface, so that the reference potential of the RFIC can be stabilized. . That is, in the QFN 35, the conductor pattern 36 for supplying the reference potential is formed on the terminal formation surface (back surface) of the wiring board, and the conductor pattern 36 itself is not covered with the solder resist, so that the adhesion between the conductor pattern 36 and the solder resist is improved. There is no problem of deteriorating. Therefore, the improvement of the adhesive strength between the conductor pattern and the solder resist, which is the object of the present invention, is not a problem with QFN35.

  However, in recent years, in order to improve the function of the RFIC, it is required to increase the number of pins and reduce the size. It has become impossible to meet such a demand by setting the RFIC package form to QFN. For example, as shown in FIG. 9A, in the QFN 35, a plurality of external connection terminals 37 are provided in the outer edge region of the wiring board 35a. However, the number of external connection terminals 37 increases due to the increase in the number of pins of the semiconductor chip. Then, it is necessary to increase the size of the wiring board 35a, and it becomes impossible to satisfy the demand for downsizing the RFIC. That is, if the package form of the RFIC is QFN35, it is impossible to achieve both high pin count and miniaturization.

  Therefore, the RFIC package form has changed from QFN to BGA. FIG. 9B is a plan view seen from the terminal forming surface of BGA (surface opposite to the chip mounting surface). As shown in FIG. 9B, in the BGA, the solder balls 32 functioning as external connection terminals can be formed over the entire surface of the substrate 20. That is, in the BGA, the solder balls 32 can be arranged in a lattice pattern not only in the outer edge region of the base material 20 but also in the inner region. Therefore, even if the number of pins is increased, there is an advantage that the size of the base material 20 can be made smaller than that of the QFN 35. In other words, even if the number of pins of the semiconductor chip is increased by using BGA as the RFIC package form. Therefore, downsizing can be realized.

  However, if the RFIC package form is BGA, the solder balls 32 are arranged in a lattice pattern on the terminal forming surface of the BGA, so that a large-area conductor pattern 36 that functions as a reference wiring is formed like the QFN 35. I can't. Therefore, the impedance of the pattern that supplies the reference potential cannot be reduced by simply using the BGA, and the resistance value of the pattern that supplies the reference potential increases. Then, the reference potential fluctuates, and the high-frequency circuit constituting the RFIC is adversely affected by noise. For this reason, in the BGA, a conductor pattern for supplying a reference potential is formed not on the terminal forming surface side of the substrate 20 but on the chip mounting surface side of the substrate 20 (see the conductor pattern 21a in FIG. 6). Thus, the reference potential can be stabilized by forming a large-area conductor pattern on the chip mounting surface side of the substrate 20.

  However, when a large-area conductor pattern for supplying a reference potential is formed on the chip mounting surface side of the base material 20, as described above, a solder resist is formed so as to cover the conductor pattern. There is a concern that the base material 20 on which the conductor pattern is formed and the solder resist are peeled off due to the adhesion being peeled off. In other words, BGA can achieve downsizing and stabilization of the reference potential due to the increase in the number of pins, but as a new problem, there is a concern that the adhesive force between the large-area conductor pattern and the solder resist may be reduced. The

  Therefore, by applying the present invention to BGA, it is possible to improve the adhesive force between the conductor pattern and the solder resist. That is, by providing an opening reaching the base material inside the conductor pattern, the adhesive strength between the conductor pattern and the solder resist can be improved, and peeling between the conductor pattern and the solder resist can be prevented.

  From the above, a remarkable effect can be obtained particularly by applying the present invention to BGA. Specifically, in the BGA, it is possible to achieve downsizing and stabilization of the reference potential due to the increase in the number of pins, and by applying the present invention to the BGA, a large area conductor pattern and a solder resist can be realized. Adhesive strength can be improved.

<Modification of Embodiment>
FIG. 10 is a plan view showing a modification of the present embodiment. As can be seen by comparing FIG. 6 and FIG. 10, in FIG. 10, the conductor pattern 21a is further separated to form a conductor pattern 21e. Both the conductor pattern 21a and the conductor pattern 21e are conductor patterns that function as reference wirings for supplying a reference potential, and in particular, are conductor patterns for supplying a reference potential to an analog portion of the RFIC. And the conductor pattern 21a is a conductor pattern which supplies a reference potential to a receiving part among analog parts, and the conductor pattern 21e is a conductor pattern which supplies a reference potential to a transmission part among analog parts. As described above, in the modification shown in FIG. 10, the conductor pattern that supplies the reference potential to the analog unit is changed into the conductor pattern 21a that supplies the reference potential to the receiving unit and the conductor pattern 21e that supplies the reference potential to the transmitting unit. It is separated. Even in this case, the conductor pattern 21a and the conductor pattern 21e have a larger area than the conductor pattern 21d that functions as a power supply wiring and the conductor pattern 21c that functions as a signal wiring. Therefore, the opening part 24 which reaches a base material is provided in the inside of the conductor patterns 21a and 21e by applying the present invention. Thereby, the adhesive strength between the conductor patterns 21a and 21e and the solder resist can be improved, and the peeling between the conductor patterns 21a and 21e and the solder resist can be prevented.

  Here, the conductor pattern that supplies the reference potential to the analog portion is separated into a conductor pattern 21a that supplies the reference potential to the receiving portion and a conductor pattern 21e that supplies the reference potential to the transmitting portion. This is because the fluctuation of the reference potential supplied to the receiving unit is separated from the fluctuation of the reference potential supplied to the transmitting unit. That is, in the receiving unit, it is necessary to stabilize the reference potential as much as possible to prevent noise generation. Specifically, there is an LNA (low noise amplifier) as one of the analog units of the receiving unit. The LNA is a circuit to which a received signal is first input in the RFIC. In this LNA, the received signal is amplified, but it is desirable that noise is not included as much as possible during this amplification. Therefore, by separating the conductor pattern 21a that supplies the reference potential to the reception unit and the conductor pattern 21e that supplies the reference potential to the transmission unit, noise due to fluctuations in the reference potential in the transmission unit is included in the LNA included in the reception unit. Can be prevented from being transmitted to. From this point of view, it is possible to electrically separate the conductor pattern 21a and the conductor pattern 21e as in this modification. Even in this case, the present invention is applied to the conductor patterns 21a and 21e. be able to.

  In this embodiment, the BGA is described as an example of the RFIC package form. However, the present invention is not limited to this and can be applied to, for example, an LGA (Land Grid Array). Differences between BGA and LGA will be described with reference to the drawings. FIG. 11 is a cross-sectional view showing a cross section of a BGA. In FIG. 11, the BGA is characterized in that solder balls 32 are formed on the back surface of the substrate 20 (the surface opposite to the chip mounting surface). The height of the solder balls 32 is, for example, 0. A structure that is 1 mm or more is defined as BGA. On the other hand, FIG. 12 is a sectional view showing a section of the LGA. In FIG. 12, the LGA is characterized in that a solder ball (solder half ball) 33 having a low height is formed on the back surface (surface opposite to the chip mounting surface) of the substrate 20 or the solder ball 33 is A structure in which the height of the solder ball 33 is, for example, 0.1 mm or less is an LGA. This is the difference between BGA and LGA. Since other configurations are the same for BGA and LGA, the present invention can be applied to LGA.

<Manufacturing process of wiring board>
The semiconductor device in this embodiment is configured as described above. Next, a manufacturing process of a BGA as an example of the semiconductor device will be described with reference to the drawings. First, the manufacturing process of the wiring board which comprises BGA is demonstrated.

  As shown in FIG. 13, a wiring board in which a copper foil 41 is attached to both surfaces of a base material 40 is prepared. At this time, the base material 40 is made of, for example, a glass-BT material or a glass-heat resistant epoxy material. Subsequently, as shown in FIG. 14, a via hole 42 is formed in the via formation region. The via hole 42 is formed by drilling with a drill, and is formed so as to penetrate the base material 40 having the copper foil 41 attached on both sides.

  Next, as shown in FIG. 15, copper plating films 43 are formed on both surfaces of the copper foil 41 attached to the base material 40. The copper plating film 43 can be formed by, for example, an electroless plating method or an electrolytic plating method. The copper plating film 43 is also formed on the side surface of the via hole 42 that penetrates the base material 40.

  Subsequently, as shown in FIG. 16, after the surface of the copper plating film 43 is polished, a dry film 44 is pasted on the copper foils 41 on both sides. The dry film 44 is a film that cures when irradiated with ultraviolet rays, and is used to form a mask for patterning the copper foil 41.

  Thereafter, as shown in FIG. 17, masks 45a and 45b are arranged on both sides of the substrate 40, and ultraviolet rays are irradiated through the masks 45a and 45b. Thereby, the pattern formed on the masks 45 a and 45 b is transferred to the dry film 44. And as shown in FIG. 18, the dry film 44 is patterned by developing the dry film 44 to which the pattern was transferred. For example, the area of the dry film 44 that was not exposed to ultraviolet rays is removed by development processing. The patterning of the dry fill 44 is performed, for example, so that the opening 46 is formed at the center of the solid pattern.

  Next, as shown in FIG. 19, the copper foil 41 is etched using the patterned dry film 44 as a mask. Thereby, the pattern formed on the dry film 44 is reflected on the copper foil 41. Thereafter, as shown in FIG. 20, the patterned dry film 44 is removed. Thereby, a solid pattern is formed on the upper surface of the base material 40, and an opening 46 is formed at the center of the solid pattern. The opening 46 penetrates through the copper foil 41 and reaches the base material 40. At this stage, it is inspected whether the pattern is normally formed. For the inspection, for example, an optical inspection machine or the like is used.

  Subsequently, as shown in FIG. 21, solder resist 47 is applied to both surfaces of the wiring board. In order to apply the solder resist 47 to both sides of the wiring board, first, the solder resist 47 is applied to one side of the wiring board and temporarily dried. When the solder resist 47 is temporarily dried, the solder resist 47 is applied to the other surface of the wiring board and temporarily dried. Thereby, the solder resist 47 can be formed on both surfaces of the wiring board. At this time, as shown in FIG. 21, the solid pattern made of the copper film and the solder resist 47 are in contact with each other on the upper surface of the wiring board, but an opening 46 is provided in the center of the solid pattern. A solder resist 47 is also embedded in the portion 46. For this reason, the solder resist 47 and the base material 40 are in direct contact with each other through the opening 46, and the adhesive strength between the solid pattern and the solder resist 47 can be improved. Note that a solder resist 47 is also buried in the via hole 42 to form a via 48.

  Next, as shown in FIG. 22, an opening 49 for forming a terminal is formed in the solder resist 47 by using a photolithography technique. A part of the solid pattern made of the copper foil 41 is exposed on the bottom surface of the opening 49. Then, after the solder resist 47 is fully cured (mainly dried), a nickel / gold plating film is formed on the copper foil 41 exposed from the opening 49. In this way, a terminal having a nickel / gold plating film formed on the copper foil 41 can be formed. Then, the wiring board is completed by cleaning the wiring board and performing an appearance inspection.

<Manufacturing process of BGA>
Next, a manufacturing process for forming a BGA (semiconductor device) by using the above-described wiring board will be described with reference to the drawings. FIG. 23 is a flowchart showing the flow of the manufacturing process for forming the BGA. First, an integrated circuit constituting an RFIC is formed by forming a transistor (MISFET (Metal Insulator Semiconductor Field Effect Transistor) or multilayer wiring) on a semiconductor wafer by using a normal semiconductor manufacturing technique. The back surface is ground (back grinding) (S101).

  Next, the semiconductor wafer is diced into individual semiconductor chips (S102). Then, the separated semiconductor chip is mounted on the wiring board formed in the above-described process (die bonding) (S103). Adhesion between the semiconductor chip and the wiring board is performed by using an insulating paste. At this time, the wiring board is integrated so that a plurality of BGAs can be formed, and a semiconductor chip is mounted on each BGA acquisition region.

  Subsequently, the terminals formed on the wiring board and the pads of the semiconductor chip are connected by wires (wire bonding) (S104). Thereafter, the entire chip mounting surface of the wiring board is sealed with resin (mold) (S105). Then, a production number or the like is marked on the resin used for sealing with a laser or the like (S106).

  Next, solder balls are mounted on the back surface opposite to the chip mounting surface of the wiring board (S107). Then, the wiring board is diced so as to obtain individual BGAs (S108). In this way, the BGA can be manufactured, and the completed BGA is stored in the tray and shipped (S109).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a block diagram which shows the structure of the transmission / reception part of a mobile telephone. It is a block diagram which mainly shows the internal structure of RFIC. It is sectional drawing which shows schematic mounting structure (BGA) of RFIC. It is the top view seen from the solder ball mounting surface of BGA shown in FIG. It is the top view seen from the solder ball mounting surface of BGA like FIG. 4, and is the figure which removed the solder ball and the soldering resist. It is the top view seen from the chip | tip mounting surface side of BGA of this invention. It is sectional drawing which shows a part of BGA. It is a top view which shows the state which mounted the semiconductor chip on the chip | tip mounting surface of the base material in which the conductor pattern was formed. (A) is the top view seen from the terminal formation surface (surface on the opposite side to a chip mounting surface) of QFN, (b) is the terminal formation surface (surface on the opposite side to a chip mounting surface) of BGA. It is the top view seen from. It is a top view which shows the modification of embodiment. It is sectional drawing which shows the cross section of BGA. It is sectional drawing which shows the cross section of LGA. It is a perspective view which shows the manufacturing process of the wiring board in embodiment. FIG. 14 is a perspective view showing a manufacturing step of the wiring board following FIG. 13. FIG. 15 is a perspective view showing a manufacturing step of the wiring board following FIG. 14. FIG. 16 is a perspective view showing a manufacturing step of the wiring board following FIG. 15. FIG. 17 is a perspective view showing a manufacturing step of the wiring board following FIG. 16. FIG. 18 is a perspective view illustrating a manufacturing step of the wiring board following FIG. 17. FIG. 19 is a perspective view showing a manufacturing step of the wiring board following FIG. 18. FIG. 20 is a perspective view showing a manufacturing step of the wiring board following FIG. 19; FIG. 21 is a perspective view showing a manufacturing step of the wiring board following FIG. 20; FIG. 22 is a perspective view showing a manufacturing step of the wiring board following FIG. 21; It is a flowchart which shows the flow of the manufacturing process which forms BGA. It is sectional drawing which shows a part of BGA which this inventor examined.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Mobile phone 2 Application processor 3 Memory 4 Baseband part 5 RFIC
6 Power Amplifier 7 SAW Filter 8 Antenna Switch 9 Antenna 10 Control Unit 11 Interface Circuit 12 LNA
13 Direct conversion mixer 14 PGA
15 A / D converter circuit 16 Digital filter 17 Offset PLL circuit 18 Modulator 19 D / A converter circuit 20 Base material 21a Conductor pattern 21b Conductor pattern 21c Conductor pattern 21d Conductor pattern 21e Conductor pattern 22 Via hole 23 Via 24 Opening 25 Solder resist 26 Insulating paste 27 Semiconductor chip 27a Pad 28 Terminal 29 Wire 30 Resin 31 External connection terminal 31a Conductor pattern 32 Solder ball 33 Solder ball 35 QFN
36 Conductor Pattern 37 External Connection Terminal 40 Base Material 41 Copper Foil 42 Via Hole 43 Copper Plating Film 44 Dry Film 45a Mask 45b Mask 46 Opening 47 Solder Resist 48 Via 49 Opening 100 BGA
DESCRIPTION OF SYMBOLS 101 Base material 102 Conductor pattern 103 Via 103a Via hole 104 Solder resist 105 Insulation paste 106 Semiconductor chip 107 Terminal 108 Wire 109 Resin 110 External connection terminal 111 Solder ball

Claims (15)

(A) a semiconductor chip;
(B) and a wiring board for mounting the semiconductor chip,
The wiring board is
(B1) a flat substrate;
(B2) a first conductor pattern formed on the chip mounting surface of the substrate;
(B3) an opening that opens the first conductor pattern and reaches the surface of the base on the chip mounting surface side;
(B4) said embedding openings, and a protective film formed on the first conductor pattern,
(B5) having a via that penetrates the first conductor pattern and the base material and is included in the first conductor pattern in plan view ,
A plurality of the openings are formed in the first conductor pattern,
A plurality of the vias are formed,
The protective film and the base material are in direct contact with each other at the bottom surface of the opening ,
A plurality of external connection terminals are formed on the back surface of the wiring board opposite to the chip mounting surface, and the first conductor pattern and at least one of the external connection terminals are electrically connected by the vias. Connected to
Solder balls are formed on the external connection terminals,
The semiconductor device , wherein the at least one opening is disposed so as to overlap the at least one solder ball in a plan view . The semiconductor device according to claim 1,
On the chip mounting surface of the wiring board, a second conductor pattern that is electrically separated from the first conductor pattern is further formed,
The area of the first conductor pattern is a semiconductor device larger than the area of the second conductor pattern. The semiconductor device according to claim 2,
Wherein the first conductive pattern serves as a reference line that is a reference potential is supplied, it said second conductor pattern functions as a signal line for transmitting a power line or a signal power supply potential is supplied, the semiconductor device. The semiconductor device according to claim 1,
Wherein said chip mounting surface of the wiring board, said provided plurality of conductive patterns including a first conductor pattern is formed, the largest area of the first conductor pattern of the plurality of conductive patterns, the semiconductor device. The semiconductor device according to claim 1 ,
The opening is a semiconductor device formed between the plurality of vias. The semiconductor device according to claim 5 ,
The opening is formed on the inner side of a position closer to the central portion than a position where the via is formed among the first conductive pattern, the semiconductor device. The semiconductor device according to claim 1,
The semiconductor device is disposed so as to overlap at least one of the opening and at least one of the solder balls in a plan view. A semiconductor device according to any one of claims 1 to 7 ,
Before SL vias, a via hole penetrating the first conductive pattern and the substrate, a conductor film formed on the side surface of the via hole is formed in the conductive film is composed of the protective layer filling the via hole and it is, the semiconductor device. 9. The semiconductor device according to claim 8 , wherein
The opening and the via hole have a cylindrical shape,
The diameter of the opening is a semiconductor device larger than the diameter of the via hole. 9. The semiconductor device according to claim 8 , wherein
A part of the first conductor pattern is exposed from the protective film covering the first conductor pattern to form a terminal,
By electrically connecting the pads formed on the semiconductor chip and the terminals at the wire, the said first conductor pattern a semiconductor chip are electrically connected, the semiconductor device. The semiconductor device according to claim 10 ,
Wherein the terminal is a part of the first conductor pattern, when mounting the semiconductor chip on the wiring board is formed in a region not overlapping with the semiconductor chip and the plane, the semiconductor device. 9. The semiconductor device according to claim 8 , wherein
The semiconductor device , wherein the first conductor pattern is formed of a copper film, and the protective film is formed of a solder resist. 9. The semiconductor device according to claim 8 , wherein
An analog circuit and a digital circuit are formed on the semiconductor chip, a conversion circuit that performs an interconversion between an analog signal and a digital signal by the analog circuit and the digital circuit, and a modulation / demodulation that modulates or demodulates a transmission / reception signal that is an analog signal. circuit is formed, the semiconductor device. A semiconductor device according to claim 13 ,
It said first conductor pattern is formed from an electrically isolated reference potential supply pattern for the reference potential supply pattern and a digital circuit for analog circuits from each other, the semiconductor device. 15. The semiconductor device according to claim 14 , wherein
The analog circuit reference potential supply pattern further supplies an analog transmission circuit reference potential supply pattern that functions as a wiring for supplying a reference potential to the transmission circuit and is electrically separated from each other, and a reference potential to the reception circuit. are formed from the analog reception circuit reference potential supply pattern that functions as a wiring, a semiconductor device.

Images