JP5069711B2 - MOSFET model parameter extraction method - Google Patents

Description

  The present invention relates to a method for extracting parameters of a MOSFET model for circuit simulation.

In general, in the development of power supply devices such as inverters, SPICE (Simulat) for semiconductor integrated circuits
Similar to circuit simulation using ion Program with Integrated Circuit Emphasis) model, diode, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transisto
r) Using a model (device model) that simulates the electrical characteristics of power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), the circuit configuration that satisfies the design is analyzed by simulation, and the circuit function is prototyped. It is verified by evaluation.

In semiconductor integrated circuit modeling, for example, many physical parameters of a device are extracted and analyzed in cooperation with circuit simulation in order to simulate the operation of a MOSFET. The power electronics circuit simulation differs from the semiconductor integrated circuit simulation mainly in two respects. First, a designer of a power supply device such as an inverter is intended to perform a simulation for designing a circuit board, and is not intended to develop a power semiconductor device or an integrated circuit itself.
Therefore, there is no physical or structural information available for the device that is basically purchased, and power supply circuit designers generally do not need advanced semiconductor physics knowledge. Extracting physical parameters is difficult. Secondly, unlike a conventional semiconductor integrated circuit, a power device is a device having a withstand voltage of several tens of volts or more, and operates differently from a small signal model that is normally mounted on a general circuit simulator. Therefore, the existing model has low accuracy and the circuit simulation that satisfies the design specifications is insufficiently studied.

Power supply devices represented by inverters are strongly demanded for small size, high efficiency, and low cost. To this end, the optimal design of the power supply device is studied through simulation to reduce the number of prototypes, shorten the construction period, and limit operation design. It needs to be realized. Furthermore, there is a need for a device model that allows circuit designers of power supply devices to extract device model parameters without advanced knowledge of semiconductors and to perform circuit design with high accuracy.

  The most commonly used MOSFET simulation model is called the SPICE model, which is classified according to various levels. LEVEL 1 to 3 are standardly supported by circuit simulators such as PSPICE and Simplorer, and PSPICE is widely used as a standard parameter extraction tool for LEVEL 3 is prepared. Further, not only LEVEL 1 to 3, but various methods have been proposed as parameter extraction methods for various SPICE models (see, for example, Patent Document 1).

Originally, the SPICE model is intended to simulate an electronic circuit device used for signal processing, and therefore has a structure different from that of a high voltage / high current device used in power electronics. The signal processing MOSFET has a so-called “horizontal” structure, whereas the power MOSFET has a “vertical” structure in which the drain terminal faces the gate / source terminal in order to pass a large current.

The major difference between “horizontal” and “vertical” MOSFETs is whether or not a depletion layer is formed between the drain and gate terminals. In the “horizontal type” in which the gate, drain, and source terminals are arranged side by side, a depletion layer is not formed between the gate and the drain even when a large voltage is applied between the drain and the source. Therefore, the capacitance between the terminals is substantially constant at the capacitance equivalent to the oxide film regardless of the operating state of the main circuit (see Non-Patent Document 1, FIG. 3A).
On the other hand, in the “vertical type”, the drain terminal and the gate / source terminal face each other.
When a voltage is applied between the sources, a depletion layer is also formed between the drain and the gate. Therefore, the capacitance between the drain and the gate decreases as the voltage increases from the capacitance of the oxide film (see Non-Patent Document 1, FIG. 3B).

  A representative example developed to supplement the “vertical” characteristics with the “horizontal” characteristics of the SPICE model is the MODPEX model (Non-Patent Document 1). The MODPEX model consists of a main circuit part and sub-circuit part. Appropriate parameters extracted from the transfer characteristics and output characteristics described in the data sheet are extracted to MOSFET LEVEL 1 of the main SPICE model, and cannot be simulated by the SPICE model. It combines a sub-circuit that simulates dynamic characteristics, especially drain-gate capacitance, with a current source. The subcircuit uses the voltage-dependent capacitance characteristics of the SPICE model of the diode to calculate the current flowing through the drain-gate capacitance.

JP 2000-322456 A

IEEJ Vol. 126, No. 6 “Detailed Simulation Analysis Method for Power Semiconductor Device Level Power Electronics Circuits Coupled with Magnetic Field System” (page 357, right 12 to page 358, left 1)

As described above, it is difficult for a circuit designer of a power supply device that does not have advanced semiconductor knowledge to understand the physical meaning of most parameters in the prior art, for example, the one disclosed in Patent Document 1, and many parameters are extracted. In addition to the problem that it takes time to do so, the conventional SPICE model has a problem that it is difficult to model a power MOSFET. In Non-Patent Document 1, since the capacitance characteristics between the drain and the gate use the capacitance characteristics of the diode model, the capacitance characteristics when the drain-source voltage is low are completely simulated even though the tendency can be simulated. In addition, since the capacitance characteristics between the gate and the source are almost constant, the drain-source voltage cannot be completely simulated, so that the dynamic characteristics cannot be completely simulated.

The present invention has been made to solve the above problems, and is intended for power applications.
The purpose is to obtain a MOSFET model for circuit simulation and its parameter extraction method that can simulate MOSFET with high accuracy.

The MOSFET model parameter extraction method according to the present invention comprises a MOSFET SPICE model and a voltage-dependent variable capacitor connected between the electrode terminals of the MOSFET SPICE model. Capacitance Cdg between the gates is a MOSFET model parameter extraction method that extracts and corrects from the measured value of the drain-source output voltage Vds of the MOSFET in the MOSFET turn-off mirror period. In the extraction of the capacitance Cdg, from the relationship that the capacitance Cdg decreases as the drain-gate voltage Vdg of the MOSFET increases, the voltage characteristic formula or voltage characteristic of the capacitance Cdg with respect to the drain-gate voltage Vdg The feedback capacitance Crss obtained by measuring the table is equal to the MOSFET drain-gate capacitance Cds, and the drain-source A first step for determining that the voltage Vds is equal to the drain-gate voltage Vdg, and a second step for determining an approximate expression of the time function of the output voltage Vds from the measured waveform of the output voltage Vds when the MOSFET is turned off. The capacitance Cdg is obtained from actual measurement based on dVds / dt obtained by differentiating the approximate expression of the time function of the output voltage Vds with respect to time, the gate voltage Vgs of the MOSFET, and the gate input resistance of the MOSFET, Further, the drain-gate voltage Vdg is obtained from the actual measurement based on the approximate expression of the time function of the output voltage Vds and the measured value of the MOSFET gate voltage Vgs in the mirror period from the relationship between the MOSFET terminal voltages. 3 and the capacitance Cdg obtained in the third step and the drain-gate voltage Vdg to the drain-gate voltage Vdg. A voltage characteristic equation or a voltage characteristic table is obtained, the voltage characteristic equation or the voltage characteristic table is replaced with a corresponding part of the voltage characteristic equation or the voltage characteristic table obtained in the first step, and the drain-gate of the capacitance Cdg And a fourth step of correcting the voltage characteristic formula or the voltage characteristic table for the inter-voltage Vdg .

The MOSFET model parameter extraction method according to the present invention includes a MOSFET SPICE model and a voltage-dependent variable capacitor connected between electrode terminals of the MOSFET SPICE model. The drain-gate capacitance Cdg is a MOSFET model parameter extraction method having a temperature characteristic value depending on the temperature when the drain-gate voltage is 0 V. In the extraction of the capacitance Cdg, First, a voltage characteristic expression or a voltage characteristic table for the capacitance Cdg with respect to the drain-gate voltage Vdg is obtained from a relationship in which the capacitance Cdg decreases as the drain-gate voltage Vdg of the MOSFET increases. Step, the measured waveform of the MOSFET gate voltage Vgs when the MOSFET turn-on temperature is changed, and the capacitance obtained in the first step The gate voltage Vdg is 0 V so that the lengths of the MOSFET mirror periods coincide with each other by comparing a simulation waveform using a MOSFET model using a voltage characteristic table or a voltage characteristic table with respect to the drain-gate voltage Vdg of Cdg. A second step of determining a temperature characteristic value of the capacitance Cdg in FIG. 5 and differentiating an approximate expression of a time function of the output voltage Vds between the drain and the source of the MOSFET in the mirror period of the MOSFET turn-off with respect to time. Based on the obtained dVds / dt, the gate voltage Vgs of the MOSFET, and the gate input resistance of the MOSFET, the capacitance Cdg is obtained from an actual measurement, and the time function of the output voltage Vds is calculated from the relationship between the voltages across the terminals of the MOSFET. And a third step of obtaining the drain-gate voltage Vdg from the actual measurement based on the approximate expression of the MOSFET and the actual measurement value of the gate voltage Vgs of the MOSFET during the mirror period Based on the capacitance Cdg and the drain-gate voltage Vdg obtained in the third step, a voltage characteristic formula or a voltage characteristic table of the capacitance Cdg with respect to the drain-gate voltage Vdg is obtained in the second step. And a fourth step of correcting based on the temperature characteristic value of the electrostatic capacitance Cdg obtained in (5).

  According to the present invention, it is possible to easily obtain a MOSFET model for circuit simulation capable of simulating a MOSFET for power use with high accuracy, and to obtain a remarkable effect that the extraction of parameters set in the MOSFET model can be easily performed in a short time. Is.

It is a circuit block diagram which shows the MOSFET model by Embodiment 1 of this invention. It is a flowchart which shows the extraction method of the parameter for MOSFET static characteristic analysis by Embodiment 1 of this invention. It is an output characteristic graph of MOSFET which shows the extraction method of parameter RD by Embodiment 1 of this invention. It is a temperature characteristic graph which shows the extraction result of parameter RD by Embodiment 1 of this invention. 3 is a MOSFET transfer characteristic graph showing a method of extracting parameters KO and VTO according to the first embodiment of the present invention. It is a temperature characteristic graph which shows the extraction result of the parameter KP by Embodiment 1 of this invention. It is a temperature characteristic graph which shows the extraction result of the parameter VTO by Embodiment 1 of this invention. It is a flowchart which shows the extraction method of the parameter for MOSFET dynamic characteristic analysis by Embodiment 1 of this invention. 6 is a capacitance characteristic graph of a MOSFET when the drain-source voltage Vds is changed with the gate-source voltage Vgs = 0 according to the first embodiment of the present invention. It is a capacity | capacitance characteristic graph which shows the extraction result of the electrostatic capacitance Cds by Embodiment 1 of this invention. It is a capacity | capacitance characteristic graph which shows the extraction result of the electrostatic capacitance Cdg by Embodiment 1 of this invention. It is a circuit block diagram which shows the MOSFET model and drive circuit by Embodiment 1 of this invention. 4 is a waveform showing a rise of a drain-source voltage Vds and its approximate curve during a mirror period of MOSFET turn-off according to the first embodiment of the present invention. It is a capacity | capacitance characteristic graph which shows the extraction result of the electrostatic capacitance Cdg in the mirror period by Embodiment 1 of this invention. 6 is a capacitance characteristic graph of a MOSFET when the gate-source voltage Vgs is changed with the drain-source voltage Vds = 0 according to the first embodiment of the present invention. It is a capacity | capacitance characteristic graph which shows the extraction result of the electrostatic capacitance Cgs by Embodiment 1 of this invention. It is a circuit block diagram which shows the MOSFET model by Embodiment 2 of this invention. It is a flowchart which shows the extraction method of the parameter for MOSFET dynamic characteristic analysis by Embodiment 2 of this invention. It is a circuit block diagram which shows the MOSFET model and drive circuit by Embodiment 2 of this invention. It is an example of measured waveforms of the gate voltage Vgs, the output voltage Vds, and the drain current Id at the time of turn-on according to the second embodiment of the present invention. It is a circuit block diagram which shows the MOSFET model and drive circuit by Embodiment 2 of this invention.

Embodiment 1 FIG.
Hereinafter, a simulation method using a MOSFET model according to an embodiment of the present invention will be described using an N-type MOSFET as an example.
FIG. 1 is a circuit configuration diagram of a MOSFET model according to Embodiment 1 of the present invention. The SPICE model 1 of the MOSFET is one of NMOS LEVELs 1 to 3, and has three types of electrode terminals: a gate terminal G, a source terminal S, and a drain terminal D. Further, a capacitor 2 having a capacitance Cds between the drain terminal D and the source terminal S, a capacitor 3 having a capacitance Cdg between the gate terminal G and the drain terminal D, and a capacitance between the gate terminal G and the source terminal S are provided. A capacitor 4 having a capacitance Cgs is connected. Capacitors 2 to 4 are voltage-dependent variable capacitors in which the inter-terminal capacitances Cds, Cdg, and Cgs change according to the inter-terminal voltages Vds, Vdg, and Vgs applied thereto.
The MOSFET model configured as described above simulates the static characteristics of the MOSFET by the SPICE model 1 and the dynamic characteristics by the variable capacitors 2 to 4 by extracting parameters extracted by the parameter extraction method described later.

First, a method for extracting MOSFET static characteristic analysis parameters according to the embodiment of the present invention will be described in detail with reference to the flowchart of FIG.
There are many parameters to be extracted in SPICE model 1, but in the MOSFET model according to the present invention, RD (Drain Ohmic Resistance), KP (Transconductance Parameter) among parameters that can be extracted with NMOS LEVEL 1-3. : Mutual conductance parameter) and VTO (Threshold Voltage), extract only three types of parameters, and leave other parameters at their default values without extracting them.

The parameter RD corresponds to a resistance component present at the drain terminal D. Therefore, when the MOSFET is in a conductive state, the parameter RD affects the conductive resistance. For extracting the parameter RD, the gate voltage (gate-source voltage) Vgs shown in FIG. 3 is, for example, 20 V, that is, the MOSFET is in a conductive state, and the relationship between the output voltage (drain-source voltage) Vds and the drain current Id. The measured value of the output characteristic that represents is used. Here, the electrical resistance Ron described in the data sheet corresponds to the slope (ΔVds / ΔId) of the output characteristics. The parameter RD is obtained from the slope of the tangent line at the output characteristic origin (Vds = 0, Id = 0).
When the output characteristics are actually measured by changing the temperature T, a tendency as shown in FIG. 3 is shown, and the result of extracting the parameter RD for each temperature is as shown in FIG. That is, when the temperature T increases, the parameter RD also increases, and the conduction resistance Ron increases with the temperature T. An approximate expression for the temperature RD of the parameter RD is obtained from FIG. 4, and a temperature characteristic expression of the parameter RD or a table of temperature characteristics is obtained (FIG. 2: steps S11 and S12).

The parameter KP indicates a slope in the transfer characteristic, and the parameter VTO is a threshold voltage. Therefore, the parameters KP and VTO are extracted from the transfer characteristics. The previously extracted parameter RD is set in the SPICE model 1, the parameter VTO is assumed to be V0, and the transfer characteristic when the parameter KP is changed is obtained by simulation (FIG. 2: step S13).
Next, as shown in FIG. 5, the transmission characteristics by simulation and actual measurement are displayed on the same graph. Since the parameter KP is the slope of the transfer characteristic, the value of the parameter KP whose slope coincides with the actual measurement near the rated current is obtained (FIG. 2: step S14). In the example of FIG. 5, KP = b.
Next, the difference ΔV of the gate voltage Vgs is obtained by comparing the actual measurement and the transfer characteristic when KP = b from FIG. Therefore, the parameter VTO is set to VTO = V0 + ΔV by adding this difference ΔV to the temporary threshold voltage V0 (FIG. 2: step S15).

  Similarly, the parameters KP and VTO are extracted by changing the temperature, and the results are plotted on a graph to show the trends shown in FIGS. The parameter KP represents a phenomenon in which the value of the parameter KP decreases as the temperature increases, that is, the slope of the transfer characteristic decreases, and the parameter VTO exhibits a phenomenon that the threshold voltage decreases as the temperature increases. Similar to the parameter RD, the approximate expressions of the parameters KP and VTO with respect to the temperature T are obtained from FIGS.

According to the configuration of the SPICE model 1, the output characteristics of the MOSFET are determined by the parameter RD and the transfer characteristics are determined by the parameters KP and VTO. It will be simulated with parameters. Further, the parameter RD is extracted from the actual measurement value of the output characteristic, and the parameters KP and VTO are extracted from the actual measurement value of the transfer characteristic, so that the static characteristic of the MOSFET is simulated with high accuracy. Furthermore, the parameters RD, KP, and VTO are extracted in consideration of the static temperature characteristics and are extracted as a function of temperature, so that the temperature characteristics are also simulated with high accuracy.
Since other parameters of the SPICE model 1 are not extracted, the SPICE model 1 only simulates the static characteristics of the MOSFET, not the dynamic characteristics.

Next, a method for extracting MOSFET dynamic characteristic analysis parameters according to the embodiment of the present invention will be described in detail with reference to the flowchart of FIG.
In the MOSFET model according to the present invention, it is considered that the inter-terminal capacitances Cds, Cdg, and Cgs of the MOSFET depend on the inter-terminal voltages Vds, Vdg, and Vgs applied thereto, respectively. The inter-terminal capacitance of the MOSFET can be calculated from the capacitance characteristics described in the data sheet.

First, the capacitance Cds of the variable capacitor 2 is extracted by measuring the capacitance characteristics described in the data sheet. The capacitance characteristics shown in FIG. 9 are obtained by actually measuring the input capacitance Ciss, the output capacitance Coss, and the feedback capacitance Crss, and the relationship of Cds = Coss−Crss is generally established with the drain-source capacitance Cds. Therefore, the result of obtaining Cds by Coss-Crss from the capacitance characteristic of FIG. 9 is as shown in FIG. 10, and represents the characteristic of the capacitance Cds with respect to the output voltage Vds. A voltage characteristic formula or a voltage characteristic table for the output voltage Vds of the capacitance Cds is obtained from FIG. 10 (FIG. 8: Step S21).

Similarly, the capacitance Cdg of the variable capacitor 3 is extracted by measuring the capacitance characteristics described in the data sheet. The capacitance Cdg between the drain and the gate generally has a relationship of Cdg = Crss, and the feedback capacitance Crss directly corresponds to the capacitance Cds between the drain and the gate. The capacitance characteristics in FIG. 9 are values when the gate voltage Vgs is fixed to 0 and the output voltage Vds is changed. The drain-gate voltage Vdg applied to the variable capacitor 3 is a relational expression of the voltage between the MOSFET terminals.

Vds ＝ Vdg ＋ Vgs …… (1)

Therefore, Vds = Vdg. Therefore, when the capacitance characteristics of FIG. 9 are replaced with Crss = Cdg and Vds = Vdg, the result is as shown in FIG. 11, and represents the characteristics of the capacitance Cdg with respect to the drain-gate voltage Vdg. That is, the capacitance Cdg decreases as the drain-gate voltage Vdg increases. From FIG. 11, a voltage characteristic formula or a voltage characteristic table for the drain-gate voltage Vdg of the capacitance Cdg is obtained (FIG. 8: Step S22).

  The actual measurement value of the feedback capacitance Crss shown in FIG. 9 changes in a magnitude of two digits or more in the region where the output voltage Vds is low, and the accuracy is low due to the difficulty of the measurement. Accordingly, the voltage characteristic in the low voltage region is corrected for the capacitance Cdg of the variable capacitor 3. In the MOSFET model according to the present invention, Cdg is extracted from an actual switching waveform.

FIG. 12 shows the relationship between the gate current and each voltage / current in the MOSFET. In the figure, 5 indicates a gate power supply that outputs a voltage value Vgsmin when turned off and a voltage value Vgsmax when turned on, and 6 indicates a gate input resistance having a resistance value Rg.
First, as a current relationship, the gate current Ig is divided into a current Igd flowing to the drain terminal D through the capacitance Cdg and a current Igs flowing to the source terminal S through the capacitance Cgs. Therefore, the following equation holds.
Ig ＝ Igd ＋ Igs …… (2)
Here, each current is given by the following equation from FIG.
Ig = (Vgsmin−Vgs) / Rg (3)
Where Rg is the gate input resistance
Igs ＝ Cgs ・ dVgs / dt …… (4)
Igd = −Cdg ・ dVdg / dt = Cdg ・ d (Vgs−Vds) / dt (5)
In the mirror period in which the gate voltage Vgs is constant when the output voltage Vds rises when the MOSFET is turned off, the slope dVgs / dt is 0, and the following equation is obtained.
Cdg =-(Vgsmin-Vgs) / Rg / dVds / dt (6)

  Since the gate voltage Vgs is constant during the mirror period, Igs = 0 in equation (2), and the drain-gate capacitance Cdg is charged / discharged by the gate current Ig = Idg. Therefore, the length of the mirror period is related to the value of Cdg, and as Cdg increases, the mirror period also increases. Further, when the gate voltage Vgs rises when the MOSFET is turned on and the output voltage Vds drops to about several volts, Vds <Vgs, so the drain-gate voltage Vdg becomes 0 V or less from the relationship of the equation (1). At this time, Cdg increases as Vdg decreases, and when Vdg reaches 0 V, the drain-gate depletion layer disappears, and Cdg becomes a value corresponding to the gate oxide film capacitance. Since Vdg is 0V or less at the end of the mirror period at turn-on, the length of the mirror period can be adjusted by the value of Cdg at Vdg = 0V. Therefore, simulation is performed by changing the value of Cdg at Vdg = 0V, and Cdg is determined by matching the length of the mirror period with the actually measured waveform. When the length of the mirror period varies depending on the temperature, Cdg at Vdg = 0V varies depending on the temperature, and the temperature characteristic value of Cdg is determined.

  The capacitance Cdg is derived using Equation (6). The actually measured waveform of the output voltage Vds at the time of turn-off of the MOSFET shown in FIG. 13 is a rising waveform in the low voltage region in the mirror period, and an approximate expression of the time function is obtained for this (FIG. 8: Step S23). Substituting dVds / dt obtained by differentiating this approximate expression of Vds with respect to time into Expression (6) to obtain Cdg, and using the relational expression (1) of the voltage between MOSFET terminals, the approximate expression of Vds and the mirror period When Vdg = Vds−Vgs is obtained from the actually measured value of the gate voltage Vgs, the capacitance Cdg with respect to the drain-gate voltage Vdg is as shown in FIG. That is, the capacitance Cdg represents a characteristic that decreases as the drain-gate voltage Vdg increases (FIG. 8: step S24).

  When the voltage characteristic expression or voltage characteristic table for Cdg with respect to Vdg is obtained from FIG. 14 and replaced with a corresponding part of the voltage characteristic expression or voltage characteristic table obtained from the previously measured capacitance characteristic, the drain of the capacitance Cdg of the variable capacitor 3 is obtained. -The voltage characteristic formula or voltage characteristic table for the gate-to-gate voltage Vdg can be corrected (FIG. 8: step S25).

  Further, in order to match the simulation waveform of the gate voltage Vgs with the measured waveform of the gate voltage Vgs, a voltage / temperature characteristic formula or a voltage / temperature characteristic table can be obtained in consideration of the temperature dependence of the MOSFET dynamic characteristics. Comparing the measured waveform and simulation waveform of the gate voltage Vgs when the temperature is changed when the MOSFET is turned on, and determining Cdg at Vdg = 0 V so that the length of the mirror period matches, the capacitance Cdg is 14 (see the vicinity of the vertical axis in FIG. 14), and the temperature characteristic value of the capacitance Cdg can be obtained. Based on the temperature characteristic value of the capacitance Cdg, a voltage / temperature characteristic formula or a voltage / temperature characteristic table for the drain-gate voltage Vdg of the capacitance Cdg is obtained, and obtained from the previously measured capacitance characteristic. Replace the corresponding part of the voltage / temperature characteristic formula or voltage / temperature characteristic table, and correct the voltage / temperature characteristic formula or voltage / temperature characteristic table for the drain-gate voltage Vdg of the capacitance Cdg. As a result, the temperature dependence of the MOSFET dynamic characteristics can be simulated with high accuracy.

The capacitance Cgs of the variable capacitor 4 is extracted as a relational expression with respect to the gate voltage Vgs. However, the capacitance characteristics described in the data sheet are generally values when the gate voltage Vgs is fixed to 0 and the output voltage Vds is changed, and the capacitance Cgs of the variable capacitor 4 in the present invention is extracted. Is not enough. Therefore, when the capacitance characteristic when the output voltage Vds is fixed to 0 and the gate voltage Vgs is changed is actually measured, a result as shown in FIG. 15 is obtained. The capacitance Cgs between the gate and the source generally has a relationship of Cgs = Ciss−Crss between the input capacitance Ciss and the feedback capacitance Crss.
Therefore, the result of obtaining Cgs by Ciss-Crss from the capacitance characteristic of FIG. 15 is as shown in FIG. 16, and represents the characteristic of the capacitance Cgs with respect to the gate voltage Vgs. A relational expression of the capacitance Cgs with respect to the gate voltage Vgs is obtained from FIG. 16, and a voltage characteristic formula or a table of voltage characteristics of the capacitance Cgs of the variable capacitor 4 is obtained (FIG. 8: Step S26).

  According to the configuration of the MOSFET SPICE model 1, the change in the capacitance between terminals due to the voltage fluctuation between the MOSFET terminals is represented by three types of voltage-dependent variable capacitors 2 to 4, so that the dynamic characteristics of the MOSFET can be expressed. The simulation is performed using three types of parameters of the capacitances Cgs, Cdg, and Cds of the variable capacitors 2 to 4. The capacitances Cgs, Cdg, and Cds of the variable capacitors 2 to 4 are extracted using the measured values of the capacitance characteristics and the measured values of the output voltage Vds and the gate voltage Vgs when the MOSFET is turned off. Is simulated with high accuracy.

  As described above, the MOSFET characteristics are simulated as a model configuration in which the static characteristics of the MOSFET are simulated by any one of the LEVEL 1 to 3 of the SPICE model 1 and the dynamic characteristics are simulated by the variable capacitors 2 to 4 connected between the terminals. Since the three parameters KP, VTO, and RD of SPICE model 1 and the three capacitances Cgs, Cdg, and Cds of variable capacitors 2 to 4 are extracted from the measured values and simulated. High-precision simulation can be performed easily in a short time without the need for advanced semiconductor knowledge. In addition, the temperature dependence of MOSFET dynamic characteristics can be simulated with high accuracy.

Embodiment 2. FIG.
FIG. 17 is a circuit configuration diagram of a MOSFET model according to the second embodiment of the present invention. The difference from the first embodiment is that a parasitic resistance is connected to the gate terminal G and a parasitic inductance is connected to the source terminal S.
In FIG. 17, there are three types of terminals: a gate terminal G, a source terminal S, and a drain terminal D. The SPICE model 1 of the MOSFET is one of NMOS LEVELs 1 to 3, and has three types of electrode terminals: a gate terminal G ′, a source terminal S ′, and a drain terminal D. Further, a capacitor 2 having a capacitance Cds between the drain terminal D and the source terminal S ′, a capacitor 3 having a capacitance Cdg between the gate terminal G ′ and the drain terminal D, and a gate terminal G ′ and the source terminal S ′. A capacitor 4 having a capacitance Cgs is connected between them. Capacitors 2 to 4 are voltage-dependent variable capacitors in which the inter-terminal capacitances Cds, Cdg, and Cgs change according to the inter-terminal voltages Vds, Vdg, and Vgs applied thereto. Further, a parasitic resistance 7 having a resistance value Rp is connected between the gate terminals G and G ′, and a parasitic inductance 8 having an inductance value Lp is connected between the source terminals S and S ′. The MOSFET model configured as described above simulates the static characteristics of the MOSFET by the SPICE model 1 by extracting the parameters extracted by the parameter extraction method described later, the variable capacitors 2 to 4, the parasitic resistance 7, and the parasitic inductance. 8 simulates the dynamic characteristics.

The method for extracting the MOSFET static characteristic analysis parameters is the same as the method described in the first embodiment, and thus the description thereof is omitted here. Next, the method for extracting the MOSFET dynamic characteristic analysis parameters according to the embodiment of the present invention will be described in detail with reference to the flowchart of FIG. First, the parasitic resistance Rp is extracted by actually measuring a mirror voltage at which the gate voltage Vgs becomes a constant value during the mirror period during switching. That is, it is calculated from the difference between the mirror voltage obtained from the transfer characteristic and the actually measured mirror voltage Vmsw. The value of the gate voltage corresponding to the drain current Id when the MOSFET is on is read from the transfer characteristic and is set as Vmt (FIG. 18: step S18). As shown in FIG. 19, this corresponds to the voltage between the gate terminal G ′ and the source terminal S ′. What is actually obtained is the voltage between the gate terminal G and the source terminal S. As shown in FIG. 20, when the measured value of the mirror voltage at the time of switching is Vmsw, the drain current Id does not change and the parasitic inductance Lp. Since no potential difference occurs, the difference between Vmsw and Vmt is applied to the parasitic resistance Rp. The gate current Ig at this time is measured or calculated from the gate power supply voltage Vgsmax and the gate input resistance Rg when turned on, and as a result, the parasitic resistance Rp of the gate terminal is derived from the following formula (7) or formula (8) The obtained gate input resistance Rg is obtained by Expression (9) substituted in Expression (7) (FIG. 18: Step S19).
Rp = (Vmsw−Vmt) / Ig (7)
Ig = (Vgsmax−Vmsw) / Rg (8)
Rp ＝ Rg ・ (Vmsw−Vmt) / (Vgsmax−Vmsw) ...... (9)

Further, since the parasitic inductance Lp of the source terminal is common between both the gate terminal G and the source terminal S and between the drain terminal D and the source terminal S, a sudden change in the drain current Id occurs. As a result, the gate-source voltage changes. FIG. 20 is an example of measured waveforms of the gate-source voltage Vgs and the drain current Id during switching. As the drain current Id flows through the parasitic inductance Lp, the gate voltage Vgs rises from Vmsw to Vml. Using this, the parasitic inductance Lp of the source terminal is obtained from the equation (10) (FIG. 18: step S20).
Lp ・ dId / dt = Vml−Vmsw …… (10)

  Next, in the MOSFET model according to the present invention, the inter-terminal capacitances Cds, Cdg, Cgs of the MOSFET are extracted. The method of extracting the capacitance Cds of the variable capacitor 2 is the same as the method described in the first embodiment and is shown in step S21 in FIG. Similar to the capacitance Cds of the variable capacitor 2, the capacitance Cdg of the variable capacitor 3 is extracted by measuring the capacitance characteristics described in the data sheet. The capacitance Cdg between the drain and the gate generally has a relationship of Cdg = Crss, and the feedback capacitance Crss directly corresponds to the capacitance Cds between the drain and the gate. The capacitance characteristics in FIG. 9 are values when the gate voltage Vgs is fixed to 0 and the output voltage Vds is changed. The drain-gate voltage Vdg applied to the variable capacitor 3 is a relational expression of the voltage between the MOSFET terminals. From the equation (1) shown in the first embodiment, Vds = Vdg. Accordingly, as in the first embodiment, when the capacitance characteristics of FIG. 9 are replaced with Crss = Cdg and Vds = Vdg, the result is as shown in FIG. 11, which represents the characteristics of the capacitance Cdg with respect to the drain-gate voltage Vdg. That is, the capacitance Cdg decreases as the drain-gate voltage Vdg increases. From FIG. 11, a voltage characteristic formula or a voltage characteristic table for the drain-gate voltage Vdg of the capacitance Cdg is obtained (FIG. 18: Step S22).

  The actual measurement value of the feedback capacitance Crss shown in FIG. 9 of the first embodiment changes in a magnitude of two digits or more in a region where the output voltage Vds is low, and the accuracy is low due to the difficulty of the measurement. Accordingly, the voltage characteristic in the low voltage region is corrected for the capacitance Cdg of the variable capacitor 3. In the MOSFET model according to the present invention, Cdg is extracted from an actual switching waveform.

FIG. 21 shows the relationship between the gate current and each voltage / current in the MOSFET. In the figure, 5 indicates a gate power supply that outputs a voltage value Vgsmin when turned off and a voltage value Vgsmax when turned on, and 6 indicates a gate input resistance having a resistance value Rg.
First, as a current relationship, the gate current Ig is divided into a current Igd flowing to the drain terminal D through the capacitance Cdg and a current Igs flowing to the source terminal S ′ through the capacitance Cgs. Accordingly, the following equation holds for the relationship Ig = Igd + Igs, similar to equation (2) of the first embodiment.

Here, each current is given by Equation (11), Equation (12), and Equation (13) from FIG.
Ig = (Vgsmin−Vgs) / (Rg + Rp) (11)
Igs ＝ Cgs ・ dVgs / dt …… (12)
Igd = −Cdg ・ dVdg / dt = Cdg ・ d (Vgs−Vds) / dt (13)
In the mirror period in which the gate voltage Vgs is constant when the output voltage Vds rises when the MOSFET is turned off, the slope dVgs / dt is 0, and Equation (14) is obtained.
Cdg =-(Vgsmin-Vgs) / (Rg + Rp) / dVds / dt (14)

  Since the gate voltage Vgs is constant during the mirror period, Igs = 0 in equation (2), and the drain-gate capacitance Cdg is charged / discharged by the gate current Ig = Idg. Therefore, the length of the mirror period is related to the value of Cdg, and as Cdg increases, the mirror period also increases. Further, when the gate voltage Vgs rises when the MOSFET is turned on and the output voltage Vds drops to about several volts, Vds <Vgs, so the drain-gate voltage Vdg becomes 0 V or less from the relationship of the equation (1). At this time, Cdg increases as Vdg decreases, and when Vdg reaches 0 V, the drain-gate depletion layer disappears, and Cdg becomes a value corresponding to the gate oxide film capacitance. Since Vdg is 0V or less at the end of the mirror period at turn-on, the length of the mirror period can be adjusted by the value of Cdg at Vdg = 0V. Therefore, simulation is performed by changing the value of Cdg at Vdg = 0V, and Cdg is determined by matching the length of the mirror period with the actually measured waveform. When the length of the mirror period varies depending on the temperature, Cdg at Vdg = 0 V varies depending on the temperature.

  The capacitance Cdg is derived using Equation (14). The actually measured waveform of the output voltage Vds at the time of turn-off of the MOSFET shown in FIG. 13 of the first embodiment is a rising waveform in the low voltage region in the mirror period, and an approximate expression of the time function is obtained for this (FIG. 18: Step S23). Substituting dVds / dt obtained by differentiating this approximate expression of Vds with respect to time into Expression (14) to obtain Cdg, and using the relational expression (1) of the voltage between MOSFET terminals, the approximate expression of Vds and the mirror period When Vdg = Vds−Vgs is obtained from the actually measured value of the gate voltage Vgs, the capacitance Cdg with respect to the drain-gate voltage Vdg is as shown in FIG. 14 of the first embodiment. That is, the capacitance Cdg represents a characteristic that decreases as Vdg increases (FIG. 18: step S24).

  When the voltage characteristic formula or voltage characteristic table for Cdg with respect to Vdg is obtained from FIG. 14 of the first embodiment and replaced with a corresponding part of the voltage characteristic formula or voltage characteristic table obtained from the previously measured capacitance characteristic, the static capacity of the variable capacitor 3 is reduced. The voltage characteristic formula or voltage characteristic table for the drain-gate voltage Vdg of the capacitance Cdg can be corrected (FIG. 18: step S25).

  Further, in order to match the simulation waveform of the gate voltage Vgs as shown in FIG. 20 with the measured waveform of the gate voltage Vgs, a voltage / temperature characteristic formula or a voltage / temperature characteristic table is obtained in consideration of the temperature dependence of the MOSFET dynamic characteristics. You can also. Comparing the measured waveform and simulation waveform of the gate voltage Vgs when the temperature is changed when the MOSFET is turned on, and determining Cdg at Vdg = 0 V so that the length of the mirror period matches, the capacitance Cdg is 14 (see the vicinity of the vertical axis in FIG. 14), and the temperature characteristic value of the capacitance Cdg can be obtained (see FIG. 18: Step S24 ′). Based on the temperature characteristic value of the capacitance Cdg, a voltage / temperature characteristic formula or a voltage / temperature characteristic table for the drain-gate voltage Vdg of the capacitance Cdg is obtained, and obtained from the previously measured capacitance characteristic. Replace the corresponding part of the voltage / temperature characteristic formula or voltage / temperature characteristic table, and correct the voltage / temperature characteristic formula or voltage / temperature characteristic table for the drain-gate voltage Vdg of the capacitance Cdg. As a result, the temperature dependence of the MOSFET dynamic characteristics can be simulated with high accuracy.

The method for extracting the capacitance Cgs of the variable capacitor 4 is the same as the method described in the first embodiment and is shown in step S26 in FIG. According to the configuration of the SPICE model 1 of the MOSFET as described above, in consideration of the parasitic resistance and the parasitic inductance, the change in the capacitance between the terminals due to the voltage fluctuation between the MOSFET terminals is changed into three types of voltage-dependent variable capacitors 2 to 4. Therefore, the dynamic characteristics of the MOSFET are simulated by three types of parameters of the capacitances Cgs, Cdg, and Cds of the variable capacitors 2 to 4. The capacitances Cgs, Cdg, and Cds of the variable capacitors 2 to 4 are extracted using the measured values of the capacitance characteristics and the measured values of the output voltage Vds and the gate voltage Vgs when the MOSFET is turned off. Is simulated with high accuracy.

  As described above, the MOSFET characteristics are simulated as a model configuration in which the static characteristics of the MOSFET are simulated by any one of the LEVEL 1 to 3 of the SPICE model 1 and the dynamic characteristics are simulated by the variable capacitors 2 to 4 connected between the terminals. Since the three parameters KP, VTO, and RD of SPICE model 1 and the three capacitances Cgs, Cdg, and Cds of variable capacitors 2 to 4 are extracted from the measured values and simulated. In addition, high-precision simulation can be performed in a short time and easily without requiring advanced semiconductor knowledge, and the temperature dependence of MOSFET dynamic characteristics can be simulated with high accuracy.

1 SPICE model of MOSFET 2 Drain-source variable capacitor Cds
3 Drain-gate variable capacitor Cdg
4 Gate-source variable capacitor Cgs
5 Gate power supply 6 Gate input resistance 7 Parasitic resistance 8 Parasitic inductance

Claims (5)

A MOSFET SPICE model and a voltage-dependent variable capacitor connected between electrode terminals of the MOSFET SPICE model, and the capacitance Cdg between the drain and the gate of the MOSFET of the variable capacitor is A parameter extraction method for a MOSFET model that is extracted and corrected from an actual measurement value of the drain-source output voltage Vds of the MOSFET in a mirror period of turn-off,
In the extraction of the capacitance Cdg,
From the relationship in which the capacitance Cdg decreases as the drain-gate voltage Vdg of the MOSFET increases, a voltage characteristic formula or a voltage characteristic table for the capacitance Cdg with respect to the drain-gate voltage Vdg can be obtained by actual measurement. A first step in which the feedback capacitance Crss is equal to the MOSFET drain-gate capacitance Cds and the drain-source voltage Vds is equal to the drain-gate voltage Vdg ;
A second step of obtaining an approximate expression of a time function of the output voltage Vds from an actually measured waveform of the output voltage Vds when the MOSFET is turned off;
The capacitance Cdg is obtained by actual measurement based on dVds / dt obtained by differentiating the approximate expression of the time function of the output voltage Vds with respect to time, the gate voltage Vgs of the MOSFET, and the gate input resistance of the MOSFET, and Based on the relation between the MOSFET terminal voltages, the drain-gate voltage Vdg is obtained from the actual measurement based on the approximate expression of the time function of the output voltage Vds and the actual measurement value of the MOSFET gate voltage Vgs in the mirror period. And the steps
A voltage characteristic formula or a voltage characteristic table for the capacitance Cdg with respect to the drain-gate voltage Vdg is obtained from the capacitance Cdg and the drain-gate voltage Vdg obtained in the third step, and the voltage characteristic formula is obtained. Alternatively, the voltage characteristic table is replaced with the voltage characteristic expression obtained in the first step or a corresponding part of the voltage characteristic table, and the voltage characteristic expression or the voltage characteristic table for the drain-gate voltage Vdg of the capacitance Cdg is corrected. A MOSFET model parameter extraction method comprising: a fourth step. In the third step, the parameter extraction method of MOSFET model of claim 1, wherein the determining the capacitance Cdg by formula (A).
Cdg = − (Vgsmin−Vgs) / Rg / (dVds / dt) −−− (A)
Vgsmin is the gate voltage when the MOSFET is off. A MOSFET SPICE model and a voltage-dependent variable capacitor connected between electrode terminals of the MOSFET SPICE model, and the capacitance Cdg between the drain and gate of the MOSFET of the variable capacitor is the drain- A MOSFET model parameter extraction method having a temperature characteristic value depending on temperature when the voltage between the gates is 0V,
In the extraction of the capacitance Cdg,
Drain of the electrostatic capacitance Cdg said MOSFET - the pressure characteristic expression or voltage characteristics table conductive with respect to the gate voltage Vdg - the drain of the electrostatic capacitance Cdg from the relationship decreases with increasing gate voltage Vdg A first step to find,
A voltage characteristic expression or voltage characteristic table for the drain-gate voltage Vdg of the capacitance Cdg obtained in the first step and the measured waveform of the gate voltage Vgs of the MOSFET when the temperature at the turn-on of the MOSFET is changed A second step of comparing the simulation waveform using the MOSFET model used and determining the temperature characteristic value of the capacitance Cdg when the gate voltage Vdg is 0 V so that the lengths of the MOSFET mirror periods coincide with each other. When,
DVds / dt obtained by differentiating an approximate expression of the time function of the drain-source output voltage Vds of the MOSFET in the mirror period of the MOSFET turn-off with respect to time, the gate voltage Vgs of the MOSFET, and the gate input resistance of the MOSFET The capacitance Cdg is obtained from the actual measurement based on the above, and further, an approximate expression of the time function of the output voltage Vds and the measured value of the gate voltage Vgs of the MOSFET in the mirror period are obtained from the relationship between the MOSFET terminal voltages. A third step of obtaining the drain-gate voltage Vdg from the actual measurement based on
Based on the capacitance Cdg obtained in the third step and the drain-gate voltage Vdg, a voltage characteristic expression or a voltage characteristic table for the capacitance Cdg with respect to the drain-gate voltage Vdg is obtained in the second step. And a fourth step of correcting based on the obtained temperature characteristic value of the capacitance Cdg . In the MOSFET model, a parasitic resistance is connected to the gate terminal of the MOSFET, a parasitic inductance is connected to the source terminal of the MOSFET, and the parasitic resistance Rp of the gate terminal extracted from the measured voltage waveform of the gate voltage of the MOSFET is a parameter. In the extraction of the parasitic resistance Rp of the gate terminal,
Reading the MOSFET gate voltage value Vmt corresponding to the drain current Id at the turn-on of the MOSFET from the transfer characteristics;
Measure the mirror voltage Vmsw when the MOSFET is turned on, based on the gate voltage value Vmt, the mirror voltage Vmsw, the gate power supply voltage Vgsmax when the MOSFET is turned on, and the gate input resistance Rg of the MOSFET, or the gate parameter extracting method according to claim 1 or 3 MOSFET model described, characterized in that it comprises the step of determining the parasitic resistance Rp on the basis of the gate current Ig is measured as a voltage value Vmt and the mirror voltage Vmsw. The parasitic resistance Rp is obtained by an expression (B) based on the gate input resistance Rg or an expression (C) based on the gate current Ig, and the capacitance Cdg is obtained by an expression (D). 4. The MOSFET model parameter extraction method according to 4.
Rp = Rg · (Vmsw−Vmt) / (Vgsmax−Vmsw) −−− (B)
Rp = (Vmsw−Vmt) / Ig −−− (C)
Cdg = − (Vgsmin−Vgs) / (Rg + Rp) / dVds / dt −−− (D)
Vgsmin is the gate voltage when the MOSFET is off.