JP5063936B2 - Manufacturing method of TFT array substrate - Google Patents

Description

  The present invention relates to a TFT array substrate, a manufacturing method thereof, and a display device using the same.

  TFT active matrix array substrate (hereinafter referred to as TFT) for a display device using a thin film transistor (hereinafter referred to as TFT: Thin Filmed Transistor) using amorphous silicon (hereinafter referred to as a-Si) as a switching element. An array substrate) is generally manufactured using five photolithography processes (photoengraving processes). An example of the conventional example is disclosed in Patent Document 1. FIG. 6 shows a TFT portion of a TFT array substrate according to Patent Document 1, and is a cross-sectional view showing a general cross-sectional structure of a TFT.

  The TFT array substrate shown in FIG. 6 includes an insulating substrate 21, a gate electrode 22, a gate insulating film 23, a semiconductor active film 24, an ohmic contact film 25, a source electrode 26, a drain electrode 27, a passivation film 28, and a pixel electrode 29. Is arranged. The insulating substrate 21 is formed of a glass substrate or the like. The gate electrode 22 is formed of, for example, a Cr film. The gate insulating film 23 is made of, for example, silicon nitride (hereinafter referred to as SiN). The semiconductor active film 24 is an a-Si film. The ohmic contact film 25 is an n-type a-Si film doped with phosphorus for obtaining an ohmic contact between the semiconductor active film 24 and the upper metal. A semiconductor region is formed by the semiconductor active film 24 and the ohmic contact film 25, and both may be collectively referred to as a semiconductor layer. The source electrode 26 and the drain electrode 27 are formed of, for example, a Cr film. The pixel electrode 29 is made of, for example, ITO (Indium Tin Oxide) which is an oxide of indium and tin. Patent Document 1 discloses a technique for reducing the number of manufacturing steps by increasing the photolithography process of the TFT array substrate five times in order to improve the productivity of the display device.

  In addition, Patent Document 2 discloses a technique related to a TFT array substrate. Patent Document 2 discloses a structure (not shown) that prevents variation in electrical characteristics due to a load applied to a TFT due to a hang shape of a passivation film covering a source and drain electrodes. In Patent Document 2, after forming a pattern of a semiconductor layer, an ITO film and a metal film for source and drain electrodes are formed in the next layer process. The ITO film is disposed between the source and drain electrodes and the semiconductor layer, and is shifted from the end of the source and drain electrodes on the semiconductor layer to the channel region side. Thereby, the steps from the source and drain electrodes to the semiconductor layer are relaxed, and the passivation film is not hung.

Japanese Patent No. 3234168 JP 2000-101091 A

  However, the inventor has found that the prior art has the following problems. Generally, wet etching with an etchant is used for patterning the metal film for the gate electrode, the source electrode, and the drain electrode. In recent years, with the miniaturization of pattern dimensions, patterning by dry etching using an etching gas is increasing. However, when a metal film that is etched with a halogen gas containing chlorine atoms or fluorine atoms is used for the source electrode and the drain electrode, the following problems occur. At the time of etching the source electrode and the drain electrode, a halogen gas containing chlorine atoms or fluorine atoms has a poor etching selectivity with respect to the underlying semiconductor layer, and thus the semiconductor layer is over-etched up to the portion where the channel is formed. Therefore, the channel digging amount in the semiconductor layer becomes non-uniform, and the electrical characteristics of the TFT are not stable. For this reason, dry etching is not easily used, which hinders miniaturization of pattern dimensions.

  In order to solve this problem, an etch stopper film made of an oxide film may be provided on the semiconductor layer serving as a channel region. However, in this case, a new problem arises that the number of photolithography steps is increased once, resulting in poor production efficiency.

  An object of the present invention is to provide a TFT array substrate having excellent characteristics, a manufacturing method thereof, and a display device using the TFT array substrate by paying attention to the above-described problems.

The TFT array substrate according to the first aspect of the present invention includes:
A TFT array substrate having a channel region disposed between a source region and a drain region,
A gate electrode formed on the substrate;
A gate insulating film formed to cover the gate electrode;
A semiconductor layer provided on the gate electrode through the gate insulating film;
A source electrode having a metal film provided on the source region of the semiconductor layer;
A drain electrode having a metal film provided on the drain region of the semiconductor layer;
Between the source electrode and the source region, and a transparent conductive layer disposed between the drain electrode and the drain region,
The section of the semiconductor layer that protrudes from the transparent conductive film has a forward tapered shape.

The manufacturing method of the TFT array substrate according to the second aspect of the present invention is as follows:
A method of manufacturing a TFT array substrate having a channel region disposed between a source region and a drain region,
Forming a gate electrode on the substrate;
A step of continuously forming a gate insulating film, a semiconductor layer including a semiconductor active film and an ohmic contact film , and a transparent conductive film on the gate electrode;
Etching the transparent conductive film into an island shape using the first photoresist pattern formed on the transparent conductive film;
Etching the semiconductor layer using a laminated mask of the first photoresist pattern and the transparent conductive film;
After forming a metal film on the substrate including the first photoresist pattern is removed the transparent conductive film, the transparent conductive film and the metal film using the second photoresist pattern is dry etched Forming a source electrode and a drain electrode thereon;
Etching the transparent conductive film formed on the channel region of the semiconductor active film ;
Etching the ohmic contact film formed on the channel region of the semiconductor active film to form the channel region of the semiconductor active film .

  According to the present invention, it is possible to provide a TFT array substrate having excellent characteristics, a method for manufacturing the TFT array substrate, and a display device using the TFT array substrate with the above configuration.

  The preferred embodiments of the present invention will be described below. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary.

Embodiment 1 FIG.
First, a display device using a TFT array substrate according to the present invention will be described with reference to FIG. FIG. 1 is a front view showing a configuration of a TFT array substrate used in a display device. The display device according to the present invention will be described using a flat display device (flat panel display) such as a liquid crystal display device or an organic EL display device as an example. The overall configuration of this TFT array substrate is common to the first to third embodiments described below.

  The liquid crystal display device according to the present invention has a substrate 1. The substrate 1 is, for example, a TFT array substrate. The substrate 1 is provided with a display area 111 and a frame area 110 provided so as to surround the display area 111. In the display area 111, a plurality of gate lines (scanning signal lines) 113 and a plurality of source lines (display signal lines) 114 are formed. The plurality of gate wirings 113 are provided in parallel. Similarly, the plurality of source lines 114 are provided in parallel. The gate wiring 113 and the source wiring 114 are formed so as to cross each other. The gate wiring 113 and the source wiring 114 are orthogonal to each other. A region surrounded by the adjacent gate wiring 113 and source wiring 114 is a pixel 117. Therefore, on the substrate 1, the pixels 117 are arranged in a matrix.

  Further, a scanning signal driving circuit 115 and a display signal driving circuit 116 are provided in the frame region 110 of the substrate 1. The gate wiring 113 extends from the display area 111 to the frame area 110. The gate wiring 113 is connected to the scanning signal driving circuit 115 at the end of the substrate 1. Similarly, the source line 114 extends from the display area 111 to the frame area 110. The source wiring 114 is connected to the display signal driving circuit 116 at the end of the substrate 1. In the vicinity of the scanning signal driving circuit 115, an external wiring 118 is connected. An external wiring 119 is connected in the vicinity of the display signal driving circuit 116. The external wirings 118 and 119 are wiring boards such as FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal driving circuit 115 and the display signal driving circuit 116 via the external wirings 118 and 119. The scanning signal driving circuit 115 supplies a gate signal (scanning signal) to the gate wiring 113 based on an external control signal. The gate wiring 113 is sequentially selected by this gate signal. The display signal driving circuit 116 supplies a display signal to the source wiring 114 based on an external control signal or display data. Thereby, a display voltage corresponding to the display data can be supplied to each pixel 117. Note that the scanning signal driving circuit 115 and the display signal driving circuit 116 are not limited to the configuration arranged on the substrate 1. For example, the drive circuit may be connected by TCP (Tape Carrier Package).

  At least one TFT 120 is formed in the pixel 117. The TFT 120 is disposed near the intersection of the source wiring 114 and the gate wiring 113. The TFT 120 has a channel region disposed between the source region and the drain region. For example, the TFT 120 supplies a display voltage to the pixel electrode. That is, the TFT 120 which is a switching element is turned on by a gate signal from the gate wiring 113. Thereby, a display voltage is applied from the source wiring 114 to the pixel electrode connected to the drain electrode of the TFT 120. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. An alignment film (not shown) is formed on the surface of the substrate 1.

  Further, a counter substrate is disposed opposite to the substrate 1. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed. The counter electrode may be disposed on the substrate 1 side. Then, a liquid crystal layer is sandwiched between the substrate 1 and the counter substrate. That is, liquid crystal is injected between the substrate 1 and the counter substrate. Furthermore, a polarizing plate, a phase difference plate, and the like are provided on the outer surfaces of the substrate 1 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel.

  The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarization state of light that has been linearly polarized after passing through the polarizing plate is changed by the liquid crystal layer. Specifically, light from the backlight unit becomes linearly polarized light by the polarizing plate on the array substrate side. Then, the polarization state changes as this linearly polarized light passes through the liquid crystal layer.

  Therefore, the amount of light passing through the polarizing plate on the counter substrate side changes depending on the polarization state. That is, the amount of light that passes through the polarizing plate on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

  In the present invention, the above-described substrate 1 will be described as a TFT array substrate having a bottom gate type structure used in a liquid crystal display device. Note that a display device using a TFT array substrate is not limited to a liquid crystal display device, and may be an organic EL display or the like. The TFT array substrate according to the first embodiment will be described with reference to the drawings. 2A to 2E are cross-sectional views showing the procedure of the method for manufacturing the TFT array substrate according to the first embodiment.

  First, a Cr film, for example, with a thickness of 200 nm is formed on the substrate 1 by sputtering. Then, a gate electrode pattern is formed on the Cr film by a first photolithography process, and etching is performed using a ceric ammonium nitrate aqueous solution. The gate electrode 2 is formed by the above process. The gate electrode 2 extends from, for example, the gate wiring 113 shown in FIG. The substrate 1 is made of an insulating material such as glass. The gate electrode 2 is not limited to the Cr film, and other metals that can be used for the TFT array substrate can be used. The film thickness of the gate electrode 2 is not limited to 200 nm. Similarly, when the gate electrode 2 is a Cr film, etching is performed with a ceric ammonium nitrate aqueous solution. When a metal other than Cr is used, an etching solution corresponding to the metal is used.

  Next, the gate insulating film 3 is continuously formed to a thickness of 400 nm, the semiconductor active film 4 is 200 nm, and the ohmic contact film 5 is 50 nm thick so as to cover the gate electrode 2 by plasma CVD. The gate insulating film 3 is made of, for example, a SiN film. The semiconductor active film 4 is a channel film formed of an a-Si film. The ohmic contact film 5 is an n-type a-Si film doped with phosphorus in order to obtain an ohmic contact between the semiconductor active film 4 and the upper metal. A semiconductor region is formed by the semiconductor active film 4 and the ohmic contact film 5, and both are collectively referred to as a semiconductor layer. After the gate insulating film 3, the semiconductor active film 4, and the ohmic contact film 5 are continuously formed, a first transparent conductive film 10 is further formed by a sputtering method with a thickness of 100 nm.

  As described above, one of the features of the first embodiment is that the first transparent conductive film 10 is continuously formed together with the gate insulating film 3, the semiconductor active film 4, and the ohmic contact film 5. The effect will be described later. In addition, it is important to use a material that is difficult to be etched by the halogen gas containing chlorine atoms or fluorine atoms for the first transparent conductive film 10. For example, it is desirable to use an ITO (Indium Tin Oxide) film which is an oxide of indium and tin. The effect will be described later. In addition, each film thickness mentioned above is illustrated and it cannot be overemphasized that another film thickness can be used.

  Next, a resist film is applied on the first transparent conductive film 10, and exposure and development are performed. As a result, a first photoresist pattern 11 is formed, resulting in the configuration shown in FIG. As will be described below, the first photoresist pattern 11 is formed in an island shape in order to pattern the semiconductor active film 4, the ohmic contact film 5, and the first transparent conductive film 10. Further, the first photoresist pattern 11 is formed so as to protrude from one pattern of the gate electrode 2.

  In the second photolithography step, the first transparent conductive film 10 is etched by wet etching using, for example, oxalic acid via the first photoresist pattern 11. Thereby, the first transparent conductive film 10 is patterned. As a result, the configuration shown in FIG. Here, the laminated structure of the first transparent conductive film 10 and the first photoresist pattern 11 serves as a mask when the semiconductor active film 4 and the ohmic contact film 5 are etched. That is, on the semiconductor active film 4 and the ohmic contact film 5, an island-like pattern of a laminated mask composed of the first transparent conductive film 10 and the first photoresist pattern 11 is formed. At this time, the end of the first transparent conductive film 10 is etched so as to recede from the end of the first photoresist pattern 11. Accordingly, the first photoresist pattern 11 is formed in a bowl shape with respect to the first transparent conductive film. That is, the end portion of the first transparent conductive film 10 is formed inside the end portion of the first photoresist pattern 11 by side etching. In other words, the pattern of the first transparent conductive film 10 is smaller than the pattern of the first photoresist pattern 11 by the amount of side etching, and the pattern of the first transparent conductive film 10 is the pattern of the first photoresist pattern 11. The structure is included in the pattern.

Next, the ohmic contact film 5 and the semiconductor active film 4 are etched by the laminated mask pattern of the first transparent conductive film 10 and the first photoresist pattern 11. Then, the first photoresist pattern 11 is removed. Here, for example, when dry etching using a mixed gas of SF ₆ and HCl is performed, the islanding pattern of the semiconductor active film 4 and the ohmic contact film 5 having a forward tapered shape that is gentler than that of the first transparent conductive film 10. Can be formed. The reason why the forward tapered island formation pattern can be formed will be described with reference to FIG.

  FIG. 3 is an enlarged cross-sectional view of end portions of the semiconductor active film 4, the ohmic contact film 5, the first transparent conductive film 10, and the first photoresist pattern 11 shown in FIG. Here, a laminated structure of the semiconductor active film 4 and the ohmic contact film 5 is a semiconductor layer 30. At the end of the first transparent conductive film 10 etched using the first photoresist pattern 11 as a mask, a gap with a width X is formed by side etching. Here, X is a side etching amount indicating the amount of recession from the end of the first photoresist pattern 11. In this way, a space immediately below the ridge portion of the first photoresist pattern 11 becomes a gap.

  When the semiconductor layer 30 is etched using the laminated mask pattern of the first photoresist pattern 11 and the first transparent conductive film 10, the etching gas enters the gap. The side surface of the semiconductor layer 30 is sequentially etched in the lateral direction by the etching gas that has entered the gap, and at the same time, the outer region of the side surface is etched in the film thickness direction. Therefore, the island pattern of the semiconductor layer 30 is formed, and the side surface of the semiconductor layer 30 is formed in a forward tapered shape according to the side etching amount X. When the total film thickness of the semiconductor active film 4 and the ohmic contact film 5 shown in FIG. 3 is Y, the taper angle θ is controlled by Equation 1 by adjusting the side etching amount X of the first transparent conductive film 10. Is possible. Formula 1 is shown below. Here, the cross-sectional shape of the semiconductor layer 30 composed of the ohmic contact film 5 and the semiconductor active film 4 is characteristically a forward tapered shape.

  X = Y / tan θ (Formula 1)

  As described above, since the laminated mask including the first transparent conductive film 10 is used, the semiconductor layer 30 is patterned in substantially the same shape as the first transparent conductive film 10. In other words, the outer edge of the pattern of the semiconductor layer 30 substantially coincides with the first transparent conductive film 10. However, the pattern of the semiconductor layer 30 is slightly protruded from the first transparent conductive film 10 by the first photoresist pattern 11 formed in a bowl shape on the first transparent conductive film 10. In the protruding portion, the cross section of the semiconductor layer 30 becomes a forward tapered shape by the etching gas that has entered the gap in the flange portion. Further, the amount of protrusion of the semiconductor layer 30 is an amount based on the shape of the first photoresist pattern 11. Here, the positions of the pattern ends on the upper surface of the semiconductor layer 30 and the pattern ends on the lower surface of the first transparent conductive film 10 coincide.

  Returning to the description of FIG. In FIG. 2D, the source electrode 6 and the drain electrode 7 are formed on the first transparent conductive film 10 after etching the semiconductor layer 30. Here, description will be made using Mo as the material of the source electrode 6 and the drain electrode 7, for example. The source electrode 6 is extended from, for example, the source wiring 114 shown in FIG. First, a Mo film is formed to a thickness of 200 nm by sputtering on the substrate 1 from which the first photoresist pattern 11 has been removed. Then, in the third photolithography process, a second photoresist pattern 12 for forming the source electrode 6 and the drain electrode 7 is formed. That is, a resist film is applied on the metal film, and exposure and development are performed. Here, as shown in FIG. 2D, the second photoresist pattern 12 is formed on the source region 41 and the drain region 42 of the semiconductor active film 4. That is, the second photoresist pattern 12 is formed so that the first transparent conductive film 10 on the channel region 43 is exposed. The source region 41 and the drain region 42 are part of the semiconductor active film 4 and indicate diffusion regions formed at both ends of the channel region 43. The source region 41 is formed below the source electrode 6, and the drain region 42 is formed below the drain electrode 7.

Then, for example, using a mixed gas of SF _6, the Mo film is etched by dry etching. As described above, the first transparent conductive film 10 is made of a material that is not easily etched by a halogen gas containing fluorine atoms. Therefore, it becomes an etch stopper film for the mixed gas of SF ₆ and it is possible to protect the etching to the channel region 43 and the ohmic contact film 5. As a result, the configuration shown in FIG. Thereafter, the first transparent conductive film 10 formed on the channel region 43 is removed by wet etching using oxalic acid. Then, the ohmic contact film 5 formed on the channel region 43 is removed by dry etching using HCl gas. Thus, the first transparent conductive film 10 and the ohmic contact film 5 located between the source electrode 6 and the drain electrode 7 are removed. As a result, the semiconductor active film 4 is exposed, and a channel region 43 is formed between the source region 41 and the drain region 42. The source electrode 6 is connected to the source region 41 through the first transparent conductive film 10. The drain electrode 7 is connected to the drain region 42 via the first transparent conductive film 10.

The material used for the source electrode 6 and the drain electrode 7 is not limited to Mo, and an alloy containing Mo as a main component can also be used. Similarly, it is also possible to use Ti and Ta and alloys containing them as main components. Furthermore, Al or an alloy containing Al as a main component may be used. Any metal can be used as long as it is a metal that is etched by an etching gas containing chlorine atoms or fluorine atoms. Therefore, any metal film containing Al, Ti, Ta, and Mo as main components may be used. Thereby, the process by an etching can be performed easily. The source electrode 6 and the drain electrode 7 may have a laminated structure of metal films. The etching gas for the source electrode 6 and the drain electrode 7 is not limited to the SF ₆ mixed gas as long as it is an etching gas containing chlorine atoms or fluorine-based atoms, and other etching gases can be used.

Next, a SiN film 8 serving as a passivation film is formed with a thickness of 300 nm by a CVD method. Thereafter, a contact hole pattern is formed in a fourth photolithography process, and the SiN film 8 is etched by dry etching using, for example, a mixed gas of CF ₄ to form the contact hole 13. The material and film thickness of the passivation film, the method for forming the contact hole 13 and the etching gas are illustrated, and it can be said that other methods, materials, and structures used for the TFT array substrate can be used. Not too long.

  Finally, the second transparent conductive film 9 is formed with a thickness of 100 nm by sputtering to form a pixel electrode. The second transparent conductive film 9 is made of, for example, ITO which is an oxide of indium and tin. The second transparent conductive film 9 can be made of the same material as the first transparent conductive film 10. A pixel electrode pattern is formed on the second transparent conductive film 9 by a fifth photolithography process, and a pixel electrode is formed by etching using oxalic acid. With the above method, the TFT array substrate according to the first embodiment is completed.

  As described above, the first transparent conductive film 10 is made of a material that is difficult to be etched by a halogen gas containing chlorine atoms or fluorine atoms. Therefore, when the source electrode 6 and the drain electrode 7 are dry-etched, the first transparent conductive film 10 becomes an etch stopper film for the semiconductor active film 4 and the ohmic contact film 5. That is, when a metal film that needs to be etched with a halogen gas containing a chlorine atom or a fluorine atom is used for the source electrode 6 and the drain electrode 7, the etching selectivity with respect to the semiconductor active film 4 and the ohmic contact film 5 can be provided. . Therefore, it is possible to stabilize the channel digging amount. As a result, a TFT array substrate having excellent characteristics can be formed. The source electrode 6 and the drain electrode 7 that need to be etched with a halogen gas containing chlorine atoms or fluorine atoms can be processed by dry etching, and a fine pattern can be formed.

  In addition, the first transparent conductive film 10 is continuously formed together with the semiconductor active film 4 and the ohmic contact film 5, and a pattern is formed in the same photolithography process. Therefore, it is not necessary to increase the photolithography process in order to form the first transparent conductive film 10 that is an etch stopper film. The manufacturing method of the TFT array substrate according to the present embodiment is the same as the prior art (Patent Document 1) because the photolithography process is performed five times. Therefore, an etch stopper film can be formed without increasing the number of manufacturing steps. Thereby, a TFT array substrate having stable characteristics can be manufactured without reducing productivity.

  The first transparent conductive film 10 also serves as a stopper for preventing contamination from the metal used for the source electrode 6 and the drain electrode 7 to the semiconductor active film 4 and the ohmic contact film 5. Accordingly, it is possible to manufacture a TFT array substrate having good TFT characteristics and high reliability.

  In addition, the TFT array substrate formed in the first embodiment can form the semiconductor active film 4 and the ohmic contact film 5 having a forward tapered shape with a desired angle. As a result, the coverage with the source electrode 6 and the drain electrode 7 can be improved, and the connectivity can be improved. The source electrode 6 and the drain electrode 7 can also use Al or an alloy containing Al as a main component. As a result, in addition to reducing the resistance of the contact, it is possible to realize a low resistance wiring.

  In the first embodiment, the first transparent conductive film 10 is continuously formed together with the semiconductor active film 4 and the ohmic contact film 5 and then patterned. Thereafter, the source electrode 6 and the drain electrode 7 are patterned by forming a metal film as the next layer layer. That is, since the formation timings of the first transparent conductive film 10 and the source electrode 6 and the drain electrode 7 are different, the formation regions of the first transparent conductive film 10, the source electrode 6 and the drain electrode 7 can be changed. That is, the first transparent conductive film 10, the source electrode 6 and the drain electrode 7 are patterned by different photolithography processes. This is a feature of the present invention that is different from the prior art (Patent Document 2). Thereby, the 1st transparent conductive film 10, the source electrode 6, and the drain electrode 7 can be made into a different pattern shape.

Embodiment 2. FIG.
The TFT array substrate according to the second embodiment will be described with reference to the drawings. The second embodiment is also a technique related to a TFT array substrate and a method for manufacturing the same, as in the first embodiment. In addition, description is abbreviate | omitted about the same component, function, and manufacturing procedure as 1st Embodiment.

  A TFT array substrate according to the second embodiment will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a part of the manufacturing procedure of the TFT array substrate according to the second embodiment. The manufacturing procedure of the TFT array substrate according to the second embodiment is the same as that of the first embodiment from FIGS. 2 (a) to 2 (d). In the second embodiment, the procedure of FIG. 4 is used instead of FIG. 2 (e) shown in the first embodiment. In the second embodiment, the cross-sectional configuration of the TFT array substrate shown in FIG. 4 is characteristic.

In FIG. 4, the pixel electrode is directly connected to the first transparent conductive film 10 immediately below the drain electrode 7. The steps until the source electrode 6 and the drain electrode 7 are formed are the same as those shown in FIGS. First, a SiN film 8 serving as a passivation film is formed with a thickness of 300 nm by a CVD method. The process up to this point is the same as in the first embodiment. Thereafter, a contact hole pattern is formed in a fourth photolithography step, and the SiN film 8 and the Mo film that becomes the drain electrode 7 under the SiN film 8 are etched by, for example, dry etching using a mixed gas of CF ₄ . Thereby, the contact hole 15 is formed. The number of photolithography steps is counted from the first step of forming the gate electrode 2 on the substrate 1 shown in FIG.

  Here, the second embodiment is characterized in that the contact hole 15 penetrates not only the SiN film 8 but also the drain electrode 7 made of the underlying Mo film and reaches the first transparent conductive film 10. is doing. That is, after forming the SiN film 8 having the contact hole 15, a through hole reaching the first transparent conductive film 10 is provided in the drain electrode 7. Since the through hole is formed via the contact hole 15, the position of the through hole coincides with the contact hole 15 of the SiN film 15. The material and film thickness of the SiN film 8 that is a passivation film, the formation method of the contact hole 13 and the etching gas are illustrated, and other methods, materials, and structures used for the TFT can be used. Needless to say.

  Finally, the second transparent conductive film 14 is formed with a thickness of 100 nm by sputtering to form a pixel electrode. The second transparent conductive film 14 is made of ITO, which is an oxide of indium and tin, for example. The second transparent conductive film 14 is embedded in the contact hole 15. As a result, the second transparent conductive film 14 serving as the pixel electrode is in contact with the first transparent conductive film 10. In the second embodiment, it is desirable to use the same material for the second transparent conductive film 14 used for the pixel electrode and the first transparent conductive film 10. Then, a pixel electrode pattern is formed on the second transparent conductive film 14 by a fifth photolithography process, and a pixel electrode is formed by etching using oxalic acid. With the above method, the TFT array substrate according to the second embodiment is completed.

  As described above, in the second embodiment, the second transparent conductive film 14 which is a pixel electrode is directly connected to the first transparent conductive film 10. Here, since the materials of the second transparent conductive film 14 and the first transparent conductive film 10 which are the material of the pixel electrode are the same, the resistance of the contact can be reduced. That is, the resistance value is lower when the second transparent conductive film 14 which is a pixel electrode is directly contacted with the first transparent conductive film 10 than when the second transparent conductive film 14 is connected to the drain electrode 7 at the side and bottom surfaces of the minute contact hole 15. Become. Further, since the first transparent conductive film 10 is connected to the upper drain electrode 7 in a wide area, the contact resistance between the second transparent conductive film 14 and the drain electrode 7 is improved as a result. A second transparent conductive film 14 is embedded in a through hole provided in the drain electrode 7 below the contact hole 15. Therefore, the second transparent conductive film 14 is in contact with the side surface of the drain electrode 7 in the through hole.

  As described above, the TFT array substrate using the second embodiment can improve the electrical characteristics by reducing the contact resistance in addition to the effects of the first embodiment. The photolithography process according to the second embodiment is the same number of times as the process according to the first embodiment. That is, the contact resistance can be reduced without increasing the number of photolithography processes.

  Here, as in the first embodiment, the source electrode 6 and the drain electrode 7 are etched with a resist pattern different from that of the first transparent conductive film 10. Therefore, the first transparent conductive film 10 is not equivalent to the formation region of the source electrode 6 and the drain electrode 7, and a part of the source electrode 6 is formed to be in direct contact with the gate insulating film 3. This is possible because the first transparent conductive film 10 and the source electrode 6 and the drain electrode 7 are formed at different times. The source electrode 6 and the drain electrode 7 can also use Al or an alloy containing Al as a main component. As a result, in addition to reducing the resistance of the contact, it is possible to realize a low resistance wiring.

Embodiment 3 FIG.
A TFT array substrate according to the third embodiment will be described with reference to the drawings. The third embodiment is also a technique related to a TFT array substrate and a method for manufacturing the same, as in the first embodiment. In addition, description is abbreviate | omitted about the same component, function, and manufacturing procedure as 1st Embodiment.

  The third embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a part of the manufacturing procedure of the TFT array substrate according to the third embodiment. The manufacturing procedure of the TFT array substrate according to the third embodiment is the same as that of the first embodiment up to FIGS. In the third embodiment, the procedure of FIG. 5 is used instead of the procedure of FIG. The third embodiment is characterized by a manufacturing procedure and a cross-sectional configuration of the TFT array substrate shown in FIG.

  In FIG. 5, the manufacturing method of the TFT array substrate after the formation of the source electrode 6 and the drain electrode 7 will be described. Since the previous steps are the same as those in FIGS. 2A to 2C, description thereof will be omitted. From the state of FIG. 2C, a Mo film is formed to a thickness of 200 nm on the substrate 1 from which the first photoresist pattern 11 has been removed by sputtering. Then, in the third photolithography step, a second photoresist pattern 12 for forming the source electrode 6 and the drain electrode 7 is formed. The number of photolithography processes is counted from the first process of forming the gate electrode 2 on the substrate 1 shown in FIG. The process up to this point is the same as in the first embodiment.

Here, the film thickness of a part of the second photoresist pattern 12 on the drain electrode 7 (referred to as a photoresist pattern 12l) is set so as to be thinner than other regions of the second photoresist pattern 12. Patterning is performed using a stepwise exposure technique (for example, a halftone mask or a gray tone mask). That is, the film thickness of the second photoresist pattern 12 is made two steps by two-step exposure. Then, for example, using a mixed gas of SF _6, the Mo film is etched by dry etching. As described above, the first transparent conductive film 10 is made of a material that is not easily etched by a halogen gas containing fluorine atoms. Therefore, the first transparent conductive film 10 becomes an etch stopper film, and it is possible to protect etching of the semiconductor active film 4 and the ohmic contact film 5 in the channel region. As a result, the configuration shown in FIG.

  Next, the first transparent conductive film 10 formed on the semiconductor active film 4 is etched to remove the photoresist pattern 12l. First, oxalic acid is used to remove the first transparent conductive film 10 formed on the semiconductor active film 4 that becomes the channel region. Then, the ohmic contact film 5 formed on the semiconductor active film 4 is removed by dry etching using HCl gas, and a channel region of the TFT is formed. Thereafter, the photoresist pattern 12l is removed by ashing. That is, the second photoresist pattern 12 is thinned by half ashing. Thereby, the thin second photoresist pattern 121 is completely removed, and the Mo film is exposed. On the other hand, in the portion where the second photoresist pattern 12 is thick, the second photoresist pattern 12 is not completely removed and becomes thin. For example, the second photoresist pattern 12 on the source electrode 6 remains thin. As a result, the configuration shown in FIG.

  Next, after the drain electrode 7 is etched, the second photoresist pattern 12 is removed. First, the drain electrode 7 in the region where the photoresist pattern 12l has been removed is removed by etching. Thereby, a part of the drain electrode 7 is removed. Therefore, the drain electrode 7 is removed and the first transparent conductive film 10 is exposed on a part of the drain region 42. For the etching, for example, wet etching using a mixed solution of phosphoric acid and nitric acid is used. Thereafter, the second photoresist pattern 12 is removed. As a result, the configuration shown in FIG. As described above, a part of the drain electrode 7 can be removed by forming the thin photoresist pattern 12l. Note that the use of the above-described method does not increase the photoresist process.

  Here, as in the first embodiment, the source electrode 6 and the drain electrode 7 are etched with a resist pattern different from that of the first transparent conductive film 10. Therefore, the first transparent conductive film 10 is not equivalent to the formation region of the source electrode 6 and the drain electrode 7, and a part of the source electrode 6 is formed to be in direct contact with the gate insulating film 3. This is possible because the first transparent conductive film 10 and the source electrode 6 and the drain electrode 7 are formed at different times.

  Next, a SiN film 8 having a contact hole is formed, and the drain electrode 7 and the pixel electrode are connected. This process will be described in detail below. In the third embodiment, the contact hole 16 is formed in a region where the drain electrode 7 is removed. That is, the third embodiment is characterized in that the pixel electrode is not directly connected to the drain electrode 7 but is connected via the transparent conductive film 10.

First, a SiN film 8 serving as a passivation film is formed with a thickness of 300 nm by a CVD method. Thereafter, a contact hole pattern is formed in a fourth photolithography process, and the SiN film 8 is etched by dry etching using, for example, a mixed gas of CF ₄ to form the contact hole 16. The contact hole 16 is formed in a region where the drain electrode 7 is removed. That is, the drain electrode 7 is removed at the peripheral portion of the contact hole 16. Here, in the third embodiment, since the Mo film is not etched through the contact hole as in the second embodiment, there is an effect that the contact hole 16 can be easily formed finely. That is, even when the contact hole 16 is made small, the connection can be made reliably. The material and film thickness of the passivation film, the method for forming the contact hole 16 and the etching gas are illustrated, and other methods, materials, and structures used for the TFT array substrate can be used. Needless to say.

  Finally, the second transparent conductive film 17 is formed with a thickness of 100 nm by sputtering to form a pixel electrode. The second transparent conductive film 17 is made of ITO, which is an oxide of indium and tin, for example. In the third embodiment, as in the second embodiment, it is desirable to use the same material for the second transparent conductive film 17 and the first transparent conductive film 10 used for the pixel electrode. A pixel electrode pattern is formed on the second transparent conductive film 17 by the fifth photolithography process, and the pixel electrode is formed by etching using oxalic acid. With the above method, the TFT array substrate according to the third embodiment is completed.

  Thus, in Embodiment 3, the second photoresist pattern 12 is formed on the Mo film by two-step exposure. Here, the thickness of the second photoresist pattern 12 is reduced in the contact hole portion where the contact hole 16 of the SiN film 8 is formed. That is, in the contact hole portion, the second photoresist pattern 12l having a smaller film thickness than that in other portions is formed. Then, the Mo film is dry-etched through the second photoresist pattern 12. Here, the pattern of the source electrode 6 is formed. After the dry etching, a part of the second photoresist pattern 12 is ashed. Thereby, the second photoresist pattern 121 having a small thickness is removed. Therefore, the Mo film dry-etched in the contact hole portion is exposed. Then, the Mo film is etched to expose the first transparent conductive film 10. As a result, the Mo film is etched in a part on the drain region 42, and the pattern of the drain electrode 7 is formed.

  As described above, in the third embodiment, the drain electrode 7 and the second transparent conductive film 17 that is the pixel electrode are not directly connected but connected via the first transparent conductive film 10. However, the materials of the second transparent conductive film 17 and the first transparent conductive film 10 are the same, and the first transparent conductive film 10 is connected to the drain electrode 7 formed in the upper layer in a wide area. . Therefore, even if the second transparent conductive film 17 and the drain electrode 7 are not directly connected, the resistance of the contact can be reduced as in the second embodiment.

  In the third embodiment, when the contact hole 16 is formed, it is not necessary to etch the drain electrode 7, so that an effect that the contact hole can be formed finely is obtained. That is, before the SiN film 8 having the contact hole 16 is formed, a part of the drain electrode 7 is etched to expose the first transparent conductive film 10. The photolithography process according to the third embodiment is the same number of times as the processes according to the first and second embodiments. That is, the contact resistance can be reduced without increasing the number of photolithography processes, and the contact hole can be finely processed.

  Here, the formation regions of the first transparent conductive film 10 and the source electrode 6 and the drain electrode 7 are different. This is because the formation time of the source electrode 6 and the drain electrode 7 is different from that of the first transparent conductive film 10, unlike the conventional technique (Patent Document 2) as described above. Therefore, the first transparent conductive film 10 is not equivalent to the formation region of the source electrode 6 and the drain electrode 7, and a part of the source electrode 6 is formed to be in direct contact with the gate insulating film 3.

  Note that the source electrode 6 and the drain electrode 7 may be made of Al or an alloy containing Al as a main component. As a result, in addition to reducing the resistance of the contact, it is possible to realize a low resistance wiring.

  The present invention is not limited to the above embodiments. Within the scope of the present invention, each element of the above-described embodiment can be changed, added, or converted into contents that can be easily considered by those skilled in the art.

FIG. 3 is a plan view showing a configuration of a TFT array substrate according to the first exemplary embodiment. FIG. 6 is a manufacturing process sectional view of the TFT array substrate according to the first embodiment. It is sectional drawing which showed the taper shape of the semiconductor layer concerning this invention. FIG. 10 is a manufacturing process sectional view of the TFT array substrate according to the second embodiment. FIG. 10 is a manufacturing process cross-sectional view of the TFT array substrate according to the third embodiment. It is sectional drawing of the TFT array substrate which concerns on a prior art.

Explanation of symbols

1 insulating substrate, 2 gate electrode,
3 gate insulating film, 4 semiconductor active film,
5 ohmic contact film, 6 source electrode,
7 drain electrode, 8 SiN film,
9, 14, 17 Second transparent conductive film, 10 First transparent conductive film,
11 first photoresist pattern, 12 second photoresist pattern,
13, 15, 16 contact holes,
21 insulating substrate, 22 gate electrode,
23 gate insulating film, 24 semiconductor active film,
25 ohmic contact film, 26 source electrode,
27 drain electrode, 28 SiN film,
29 second transparent conductive film, 30 semiconductor layer 41 source region, 42 drain region, 43 channel region,
110 frame area, 111 display area,
113 gate wiring, 114 source wiring,
115 scanning signal driving circuit, 116 display signal driving circuit,
117 pixels, 118, 119 external wiring, 120 TFT

Claims (9)

A method of manufacturing a TFT array substrate having a channel region disposed between a source region and a drain region,
Forming a gate electrode on the substrate;
A step of continuously forming a gate insulating film, a semiconductor layer including a semiconductor active film and an ohmic contact film, and a transparent conductive film on the gate electrode;
Etching the transparent conductive film into an island shape using the first photoresist pattern formed on the transparent conductive film;
Etching the semiconductor layer using a laminated mask of the first photoresist pattern and the transparent conductive film;
After removing the first photoresist pattern and forming a metal film on the substrate including the transparent conductive film, the metal film is dry-etched using the second photoresist pattern to form the transparent conductive film. Forming a source electrode and a drain electrode thereon;
Etching the transparent conductive film formed on the channel region of the semiconductor active film;
Etching the ohmic contact film formed on the channel region of the semiconductor active film to form the channel region of the semiconductor active film. Forming a passivation film on the substrate after forming the channel region;
Forming a contact hole that penetrates the passivation film and the drain electrode;
The method of manufacturing a TFT array substrate according to claim 1 , further comprising: forming a pixel electrode directly connected to the transparent conductive film through the contact hole on the passivation film. In the step of etching the transparent conductive film into an island shape, patterning is performed so that a part of the transparent conductive film protrudes from directly below the drain electrode,
After forming the channel region, forming a passivation film having a contact hole that leads to a protruding portion of the transparent conductive film from the drain electrode on the substrate; and on the passivation film via the contact hole And a step of forming a pixel electrode directly connected to the transparent conductive film. The method of manufacturing a TFT array substrate according to claim 1 . In the step of forming the source electrode and the drain electrode,
Forming a second photoresist pattern having a thin film thickness on a contact hole portion where the contact hole is formed in the passivation film on the metal film by two-step exposure;
Etching the metal film through the second photoresist pattern, and
After the step of forming the source electrode and the drain electrode,
Etching the transparent conductive film formed on the channel region;
Ashing a portion of the second photoresist pattern to expose the metal film in the contact hole portion;
Etching the exposed metal film to expose the transparent conductive film of the contact hole portion;
The method of manufacturing a TFT array substrate according to claim 3 , further comprising a step of forming the channel region. 5. The method for manufacturing a TFT array substrate according to claim 2 , wherein the same material is used for the pixel electrode and the transparent conductive film. The semiconductor layer is amorphous silicon;
6. The method of manufacturing a TFT array substrate according to claim 1 , wherein the TFT array substrate is etched by dry etching having a gas containing chlorine or fluorine, or wet etching using an etching solution having hydrofluoric acid. . The TFT array according to claim 1, wherein the source electrode and the drain electrode contain at least one of Ti, Ta, Mo, Al, and an alloy containing them as a main component. A method for manufacturing a substrate. In the step of etching the transparent conductive film, side etching is performed so that an end portion of the transparent conductive film recedes from an end portion of the first photoresist pattern,
The method for manufacturing a TFT array substrate according to claim 1 , wherein in the step of etching the semiconductor layer, etching is performed so that a cross section of the semiconductor layer has a forward taper shape. 9. The method of manufacturing a TFT array substrate according to claim 1 , wherein a gas containing chlorine or fluorine is used as an etching gas for dry etching the metal film.

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