JP5052215B2 - Semiconductor switch circuit - Google Patents

Description

  The present invention relates to a semiconductor switch circuit that switches a high-frequency signal of a mobile communication device such as a mobile phone or a high-frequency device, and in particular, improves isolation characteristics without impairing insertion loss characteristics, handling power characteristics, and distortion characteristics. The present invention relates to a semiconductor switch circuit.

  In cellular phones and mobile radio communication devices that handle high-frequency signals, semiconductor switch circuits that use field-effect transistors such as MESFETs and HEMTs made of compound semiconductors such as GaAs are used to switch high-frequency signals. ing. The electrical characteristics required for the semiconductor switch circuit include insertion loss characteristics, isolation characteristics, handling power characteristics, distortion characteristics, and the like. An example of such a semiconductor switch circuit is disclosed in Patent Document 1 and the like.

  A conventional example of this type of semiconductor switch circuit is shown in FIG. The semiconductor switch circuit shown in FIG. 5 includes a first field effect transistor 103 and a second field effect transistor 104 connected in series between a first input / output terminal 101 and a second input / output terminal 102. From the first switch element 11 and the second switch element 12 including the third field effect transistor 105 and the fourth field effect transistor 106 connected in series between the second input / output terminal 102 and the ground. It is configured.

  For example, a control voltage higher than the pinch-off voltage of the first and second field effect transistors 103 and 104 is applied to the first control terminal 107 via the resistors R1 and R2, respectively, and the first and second field effects are applied. While the impedance between the drain and the source of the transistors 103 and 104 is set to a low impedance, a control voltage lower than the pinch-off voltage of the third and fourth field effect transistors 105 and 106 is applied to the second control terminal 108 and the resistors R3 and R3, respectively. The voltage is applied via R4 so that the drain and source of the third and fourth field effect transistors 105 and 106 have high impedance. As a result, the first input / output terminal 101 and the second input / output terminal 102 can be in a conductive state (hereinafter referred to as “the semiconductor switch circuit is in an on state”).

  Also, a control voltage lower than the pinch-off voltage of the first and second field effect transistors 103 and 104 is applied to the first control terminal 107, and the drain-source between the first and second field effect transistors 103 and 104 is applied. , A control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 105, 106 is applied to the second control terminal 108, and the third and fourth field effect transistors 105, The impedance between the drain and the source 106 is set to a low impedance. As a result, the first input / output terminal 101 and the second input / output terminal 102 can be in a non-conductive state (hereinafter referred to as “semiconductor switch circuit is in an off state”).

  In the semiconductor switch circuit having such a configuration, when a high-frequency signal is input from the first input / output terminal 101 when the semiconductor switch circuit is in an off state, the third and fourth field effect transistors 105 and 106 are in an on state. For this reason, the first and second field effect transistors 103 and 104 are not cut off and the leaked power flows to the ground potential. As a result, high isolation is ensured between the first input / output terminal 101 and the second input / output terminal 102.

Incidentally, the maximum power that can be handled in such a semiconductor switch circuit can be generally expressed by Equation 1.
Pmax = 2 {n (Vp−Vgs _(off) )} ² / Zo (Formula 1)
Here, n is the number (number of stages) of field effect transistors connected in series constituting the switch element, Vp is the pinch-off voltage of the field effect transistor, and Vgs _(off) is applied to the gate of the field effect transistor in the off state. Bias voltage, Zo, is the characteristic impedance of the system.

  According to the above formula 1, in order to increase the maximum power (handling power) that can be handled in the semiconductor switch circuit, (1) increase the number (number of stages) of field effect transistors connected in series, (2) It can be understood that a field effect transistor having a shallow pinch-off voltage Vp is used, and (3) the bias voltage is increased.

  However, in reality, the pinch-off voltage Vp of the field effect transistor is determined by the process used in the manufacturing process and is difficult to change greatly. As for the bias voltage, if it is assumed to be used in a mobile phone, the battery is normally driven at about 3 V, and it is difficult to increase the bias voltage. Therefore, it is common to increase the handling power characteristic of the semiconductor switch circuit by increasing the number n of field effect transistors connected in series.

On the other hand, mobile phones and mobile wireless devices are becoming multiband and multimode. For example, in the GSM (Global System for Mobile Communications) and UMTS (Universal Mobile Telecommunications System) multimode terminals, the GSM transmission frequency and a part of the UMTS frequency band are shared, and the band to be used can be changed using a semiconductor switch circuit. The usage mode is switched.
Japanese Patent Laid-Open No. 2002-164772

  In a semiconductor switch circuit used in a multi-mode terminal of GSM and UMTS, such as a cellular phone that has become multi-band and multi-mode, if the isolation characteristic is poor, GSM leakage to the UMTS terminal during GSM transmission There is a problem in that power may be input and an external circuit connected to the UMTS terminal may be destroyed. Further, even when the frequency bands are different, an external circuit connected to the semiconductor switch circuit may be destroyed in the same manner. An object of the present invention is to provide a semiconductor switch circuit that can realize high isolation characteristics without impairing insertion loss characteristics, handling power characteristics, and distortion characteristics required for the semiconductor switch circuits.

To achieve the above object, the invention according to claim 1, between each of the at least one common input-output terminal and two or more separate input and output terminals, constituted by a plurality of field effect transistors respectively connected in series When the first switch element is composed of a plurality of field effect transistors connected in series between the individual input / output terminal and the ground, the first switch element has a high impedance when viewed from the common input / output terminal. Doo and second switching elements ing, the between the first switching element and the connection point of the second switch element and the individual input and output terminals, said first switch is composed of one field effect transistor comprising a third switching element that will be the same impedance as the device, the signal input and output is between the common input-output terminal and one of the individual input and output It is characterized in.

The invention according to claim 2, in the semiconductor switching circuit of claim 1, the gate width of the field effect transistors constituting the third switch element, said field effect transistors constituting the first switching element It is characterized by being equal to the gate width.

  According to the present invention, there is an advantage that isolation characteristics can be improved without deteriorating insertion loss characteristics, handling power characteristics, and distortion characteristics required for a semiconductor switch circuit. In addition, since only one field effect transistor needs to be added to improve the isolation characteristic, there is an advantage that it can be realized without greatly increasing the chip size.

  The semiconductor switch element of the present invention includes a first switch element connected between two input / output terminals, a second switch element connected between one input / output terminal and ground, and a first switch element, The third switch element is connected between the connection point of the second switch element and the input / output terminal. The third switch element is composed of one field effect transistor.

  According to the configuration of the present invention, the isolation characteristic can be improved by adding the third switch element. On the other hand, the insertion loss characteristic is only increased by the insertion loss of one field effect transistor and does not increase greatly. Further, since the added third switching element does not contribute to fluctuations in handling power characteristics and distortion characteristics, these characteristics are not impaired. Hereinafter, the semiconductor switch circuit of the present invention will be described in detail.

  FIG. 1 is an explanatory diagram of a first embodiment of the present invention. The semiconductor switch circuit of the present invention shown in FIG. 1 includes a first field effect transistor 103 and a second field effect transistor connected in series between a first input / output terminal 101 and a second input / output terminal 102. 104 between the first switch element 11 composed of 104, the third switch element 13 composed of the fifth field effect transistor 109, the connection point of the first switch element 11 and the third switch element 13, and the ground. The second switch element 12 includes a third field effect transistor 105 and a fourth field effect transistor 106 connected in series.

  Here, the gate width of the fifth field effect transistor 109 is set in consideration of the following conditions. First, when the gate width of the fifth field effect transistor 109 is made narrower than the gate width per one of the first field effect transistor 103 and the second field effect transistor 104, the insertion loss characteristic and the distortion characteristic deteriorate. Therefore, the lower limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit. On the other hand, if the gate width of the fifth field effect transistor 109 is larger than the gate width of each of the first field effect transistor 103 and the second field effect transistor 104, the effect of improving the isolation characteristics is reduced. Therefore, the upper limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit.

  In a normal semiconductor switch circuit, it is preferable that the deterioration amount of the insertion loss is 0.05 dB or less. Further, since it is necessary to secure an isolation characteristic of about 35 dB, it is preferable that the gate width of the fifth field effect transistor 109 is equal to the gate widths of the first field effect transistor 103 and the second field effect transistor 104. It is.

  Next, the operation of the semiconductor switch circuit of the present invention will be described. A control voltage higher than the pinch-off voltage of the first and second field effect transistors 103 and 104 is applied to the first control terminal 107 via the resistors R11 and R12, respectively, and the first and second field effect transistors 103 are applied. , 104 has a low impedance between the drain and the source, while a control voltage lower than the pinch-off voltage of the third and fourth field effect transistors 105 and 106 is applied to the second control terminal 108, and resistors R13 and R14 are respectively provided. Between the drain and the source of the third and fourth field effect transistors 105 and 106 to provide high impedance. At the same time, a control voltage higher than the pinch-off voltage of the fifth field effect transistor 109 is applied to the third control terminal 110 via the resistor R15. As a result, the semiconductor switch circuit can be turned on.

  A control voltage lower than the pinch-off voltage of the first and second field effect transistors 103 and 104 is applied to the first control terminal 107 via the resistors R11 and R12, respectively, and the first and second field effects are applied. While the drain and source of the transistors 103 and 104 have high impedance, the second control terminal 108 is supplied with a control voltage higher than the pinch-off voltage of the third and fourth field effect transistors 105 and 106, respectively, by the resistor R13. And R14 to make the impedance between the drain and source of the third and fourth field effect transistors 105 and 106 low. At the same time, a control voltage lower than the pinch-off voltage of the fifth field effect transistor 109 is applied to the third control terminal 110 via the resistor R15. As a result, the semiconductor switch circuit can be turned off.

  In the semiconductor switch circuit having such a configuration, the first input / output terminal 101 and the second input / output terminal 102 operate as signal passing paths when the semiconductor switch circuit is in an ON state, as in the conventional example. At this time, the insertion loss characteristic is degraded by the amount of addition of the third switch element 13. However, when the number of field effect transistors constituting the switch element is one, that is, it is composed of one field effect transistor 109, the insertion loss characteristic is not greatly deteriorated as compared with the conventional circuit.

  On the other hand, when a high frequency signal is input from the first input / output terminal 101 when the semiconductor switch circuit is in the off state, the third and fourth field effect transistors 105 and 106 are in the on state. The electric power leaked without being blocked by the field effect transistors 103 and 104 flows to the ground potential, and high isolation is ensured between the first input / output terminal 101 and the second input / output terminal 102. Further, the leaked high frequency signal is blocked by the third switch element 13, and the isolation characteristic between the first input / output terminal 101 and the second input / output terminal 102 is improved.

  Next, the handling power characteristics will be compared with the conventional example. In this type of semiconductor switch circuit, it is known that in order to improve the handling power characteristics, the number (number of stages) of field effect transistors directly connected to the signal passing path may be increased. More specifically, the handling power characteristics can be improved by increasing the number of field effect transistors that are directly connected to the signal passing path and are in an off state. Therefore, in the present embodiment, the number of field effect transistors (corresponding to the field effect transistors constituting the second switch element 12) that are directly connected to the signal passing path and turned off is not changed. It can be understood that there is no deterioration.

  The distortion characteristic is a component generated in the nonlinear region of the passing power, and that the handling power does not deteriorate, that is, the distortion characteristic does not deteriorate.

  Next, a second embodiment will be described. FIG. 2 is an explanatory diagram of the second embodiment of the present invention. The semiconductor switch circuit of the present invention shown in FIG. 2 includes a common input / output terminal 201, a first individual input / output terminal 212, and a second individual input / output terminal 222, and the common input / output terminal 201 and the first individual input / output terminal. A first switch element 11A composed of a sixth field effect transistor 213 and a seventh field effect transistor connected in series between the output terminal 212 and a third switch composed of a tenth field effect transistor 219 It is composed of an eighth field effect transistor 215 and a ninth field effect transistor 216 connected in series between the element 13A, the connection point of the first switch element 11A and the third switch element 13A, and the ground. The second switch element 12A is provided.

  Further, the first switch element 11B including the eleventh field effect transistor 223 and the twelfth field effect transistor 224 connected in series between the common input / output terminal 201 and the second individual input / output terminal 222. A thirteenth switch element 13B composed of a fifteenth field effect transistor 229, a connection point of the first switch element 11B and the third switch element 13B, and the thirteenth connected in series. The second switch element 12B including the field effect transistor 225 and the fourteenth field effect transistor 226 is provided.

  As in the first embodiment, when the gate width of the tenth field effect transistor 219 is narrower than the gate width per one of the sixth field effect transistor 213 and the seventh field effect transistor 214, the insertion loss characteristics and distortion are reduced. Characteristics deteriorate. Therefore, the lower limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit. On the other hand, if the gate width of the tenth field effect transistor 219 is wider than the gate width of each of the sixth field effect transistor 213 and the seventh field effect transistor 214, the effect of improving the isolation characteristics is reduced. Therefore, the upper limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit.

  Similarly, if the gate width of the fifteenth field effect transistor 229 is narrower than the gate width per one of the eleventh field effect transistor 223 and the twelfth field effect transistor 224, the insertion loss characteristic and the distortion characteristic deteriorate. . Therefore, the lower limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit. On the other hand, if the gate width of the fifteenth field effect transistor 229 is wider than the gate width per one of the eleventh field effect transistor 223 and the twelfth field effect transistor 224, the effect of improving the isolation characteristics is reduced. Therefore, the upper limit of the gate width is set within an allowable range according to the use conditions of the semiconductor switch circuit.

  Also in the present embodiment, it is preferable that the deterioration amount of the insertion loss is 0.05 dB or less in the normal semiconductor switch circuit. In addition, since it is necessary to secure an isolation characteristic of about 35 dB, the gate widths of the tenth field effect transistor 219 and the fifteenth field effect transistor 229 are the field effect transistors 213 constituting the first switch elements 11A and 11B, It is preferable that the gate width per one of 214, 223, and 224 is equal.

  Next, the operation of the semiconductor switch circuit of the present invention will be described by taking as an example a case where a signal passing path is provided between the common input / output terminal 201 and the first individual input / output terminal 212. The basic operation is as described in the first embodiment. A control voltage higher than the pinch-off voltage of the sixth and seventh field effect transistors 213 and 214 is applied to the fourth control terminal 217 via the resistors R21 and R22, and the sixth and seventh field effect transistors 213, While the drain-source impedance of 214 is low impedance, a control voltage lower than the pinch-off voltage of the eighth and ninth field effect transistors 215 and 216 is applied to the fifth control terminal 218 via the resistors R23 and R24, respectively. This is applied to make the drain and source of the eighth and ninth field effect transistors 215 and 216 have high impedance. At the same time, a control voltage higher than the pinch-off voltage of the tenth field effect transistor 219 is applied to the sixth control electrode 220 via the resistor R25. As a result, the common input / output terminal 210 and the first individual input / output terminal 212 can be turned on.

  On the other hand, a control voltage lower than the pinch-off voltage of the eleventh and twelfth field effect transistors 223 and 224 is applied to the seventh control terminal 227 via the resistors R31 and R32, and the eleventh and twelfth field effect transistors 223 are applied. 224 has a high impedance between the drain and source, and a control voltage higher than the pinch-off voltage of the thirteenth and fourteenth field effect transistors 225 and 226 is applied to the eighth control terminal 228 via R33 and R34, respectively. This is applied to make the impedance between the drain and source of the thirteenth and fourteenth field effect transistors 225 and 226 low. At the same time, a control voltage lower than the pinch-off voltage of the fifteenth field effect transistor 229 is applied to the ninth control terminal 230 via the resistor R35. As a result, the common input / output terminal 210 and the 222 second individual input / output terminals can be turned off.

  In the semiconductor switch circuit having such a configuration, the common input / output terminal 201 in the on state and the first individual input / output terminal 212 operate as a signal passing path. At this time, the insertion loss characteristic is degraded by the amount of addition of the third switch element 13A. However, it is possible to obtain substantially the same insertion loss characteristic as that of the conventional circuit by forming the field effect transistor constituting the switch element in one stage, that is, by configuring it with one field effect transistor.

  On the other hand, between the common input / output terminal 201 in the OFF state and the second individual input / output terminal 222, the leaked power flows to the ground potential without being blocked by the eleventh and twelfth field effect transistors 223 and 224, and the common input High isolation is ensured between the output terminal 201 and the second individual input / output terminal 222. Further, the leaked high frequency signal is blocked by the third switch element 13B, and the isolation characteristic between the common input / output terminal 201 and the second individual input / output terminal 222 is improved.

  In FIG. 3, when the common input / output terminal 201 and the first individual input / output terminal 212 are in the on state and the common input / output terminal 201 and the second individual input / output terminal 222 are in the off state, The insertion loss characteristic with respect to the frequency between the two individual input / output terminals 212 and the isolation characteristic with respect to the frequency between the common input / output terminal 201 and the second individual input / output terminal 222 are shown.

  In FIG. 3, the horizontal axis represents frequency (GHz), the left vertical axis represents insertion loss (dB), and the right vertical axis represents isolation (dB). The characteristics of the semiconductor switch circuit of the present invention are represented by a solid line, and the characteristics of the conventional circuit are plotted with dots. As shown in FIG. 3, it can be seen that the insertion loss of the semiconductor switch circuit of the present invention is equivalent to that of the conventional circuit, and the isolation characteristics are reliably improved. Specifically, the amount of improvement in isolation was 15 dB or more at 1 GHz and 10 dB or more at 2 GHz.

  In the present embodiment, the number (stage number) of field effect transistors constituting the switch elements (second switch elements 12 and 12A) that are directly connected to the signal passing path and turned off is not changed. There is no deterioration in handling power characteristics.

  FIG. 4 shows that the common input / output terminal 201 and the first individual input / output terminal 212 are on and the common input / output terminal 201 and the second individual input / output terminal 222 are off. 2 shows insertion loss characteristics with respect to input power between one individual input / output terminal 212 and distortion characteristics of input power, second harmonic and third harmonic generated in the common input / output terminal 201.

  In FIG. 4, the horizontal axis represents input power (dBm), the left vertical axis represents insertion loss (dB), and the right vertical axis represents input power and harmonic difference (dBc). The characteristics of the semiconductor switch circuit of the present invention are represented by a solid line, and the characteristics of the conventional circuit are plotted with dots. As shown in FIG. 4, it can be seen that the insertion loss of the semiconductor switch circuit of the present invention is equivalent to that of the conventional circuit, and the change (distortion characteristic) of the difference between the input power and the harmonic is also equivalent to that of the conventional circuit.

  As described above, it has been confirmed that the semiconductor switch circuit of the present invention can improve the isolation characteristics without deteriorating the insertion loss characteristics, the handling power characteristics, and the distortion characteristics.

  Further, since only one field effect transistor is added to improve the isolation characteristics, there is an advantage that it can be realized without greatly increasing the chip size. Further, the third switch element added according to the present invention can be controlled in phase with the first switch element, and if the control terminal is shared, it is not necessary to increase the control signal and the control terminal pad. This does not increase the chip size.

  Of course, the semiconductor switch circuit is not limited to the SPDT switch for switching the on / off state between one common input / output terminal and two individual input / output terminals. Further, a switch for switching with a negative voltage does not require a capacitor for blocking DC voltage, and the effect of the present invention is not impaired by the presence or absence thereof.

It is explanatory drawing of the 1st Example of this invention. It is explanatory drawing of the 2nd Example of this invention. It is a characteristic diagram which showed the insertion loss characteristic and isolation characteristic in 2nd Example of this invention. It is a characteristic diagram which showed the insertion loss characteristic and distortion characteristic in the 2nd Example of this invention. It is explanatory drawing of the conventional semiconductor switch element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11: 1st switch element, 12: 2nd switch element, 13: 3rd switch element, 101: 1st high frequency input / output terminal, 102: 2nd high frequency input / output terminal, 103: 1st electric field Effect transistor 104: second field effect transistor 105: third field effect transistor 106: fourth field effect transistor 107: first control terminal 108: second control terminal 109: fifth 110: third control terminal, 201: common input / output terminal, 212: first individual input / output terminal, 213: sixth field effect transistor, 214: seventh field effect transistor, 215: Eighth field effect transistor, 216: ninth field effect transistor, 217: fourth control terminal, 218: fifth control terminal, 219: tenth field effect transistor 220, sixth control terminal, 222: second individual input / output terminal, 223: eleventh field effect transistor, 224: twelfth field effect transistor, 225: thirteenth field effect transistor, 226: first 14 field effect transistors, 227: seventh control terminal, 228: eighth control terminal, 229: fifteenth field effect transistor, 230: ninth control terminal

Claims (2)

A first switch element composed of a plurality of field effect transistors connected in series between at least one common input / output terminal and each of the two or more individual input / output terminals; between a second switch element and the constituted by a plurality of field effect transistors connected in series a first switch element that Do a low impedance when the high impedance viewed from the common input-output terminal, said first switch between elements and the connection point of the second switch element and the individual output terminals, comprising a third switch element that will be the same impedance with said consists of one field effect transistor the first switching element and, wherein the common input-output terminal and one of the semiconductor switching circuit according to claim Rukoto signal input and output is between the individual input and output. The semiconductor switch circuit according to claim 1 .
The semiconductor switch circuit, wherein a gate width of the field effect transistor constituting the third switch element is equal to a gate width of the field effect transistor constituting the first switch element.

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