JP5040170B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device such as a field effect transistor having an LDD structure.

  In a field effect transistor (FET), an electric field is strong because a change in an impurity profile is steep in the vicinity of a drain electrode. Electrons having high energy (hot electrons) accelerated by the high electric field collide and ionize atoms in the vicinity of the drain electrode to generate electron / hole pairs. Electrons are sucked into the drain electrode, but since holes have a low mobility, they accumulate in the channel region and significantly deteriorate the electrical characteristics of the FET. In order to solve this problem, an LDD (Lightly-doped drain) structure in which a lightly doped region is formed in the vicinity of the drain electrode is used. That is, the generation of hot electrons is suppressed by suppressing the change of the impurity profile and relaxing the electric field.

FIG. 6 shows a method of manufacturing a semiconductor device having an LDD structure as a first example according to the prior art. First, as shown in FIG. 6A, the metal electrode 102 is formed on the substrate 101. Next, as shown in FIG. 6B, impurity ions 201 are implanted using the metal electrode 102 as a mask to form a low concentration impurity implanted region 103. Next, as shown in FIG. 6C, the SiO ₂ film 104 is formed by CVD (Chemical Vapor Deposition) to cover the entire surface. Next, as shown in FIG. 6D, the SiO ₂ film 104 is etched back by the reactive ion beam 202 to form a SiO ₂ sidewall 105 on the side wall of the metal electrode 102. Next, as shown in FIG. 6E, impurity ions 203 are further implanted using this as a mask to form a region 106 into which impurities are implanted at a relatively high concentration. When the last remaining SiO ₂ sidewall 105 is removed, an LDD structure having a low impurity concentration in the vicinity of the drain electrode is formed as shown in FIG.

  As a second example of the prior art, a method of forming a two-step recess on a substrate is shown in FIG. First, a resist 107 is patterned on the substrate 101 as shown in FIG. Next, as shown in FIG. 7B, a recess 301 is mainly dug in the vertical direction using an etching solution having a fast etching rate with respect to the crystal orientation in the vertical direction on the substrate 101. Next, as shown in FIG. 7C, a recess 302 is dug mainly in the horizontal direction using an etching solution having a high etching rate with respect to the crystal orientation in the horizontal direction on the substrate 101. Finally, when the resist 107 is removed, a two-step recess structure as shown in FIG. 7D is obtained.

  As a third example of the prior art, when a recess is formed on a substrate and a metal used for an electrode or the like is deposited on the substrate, a space must be provided between the recess side wall and the deposited metal so as not to come into contact. In this case, FIG. 8 shows a method of forming a shape (eave shape) in which the resist protrudes by isotropic unit etching. That is, first, after patterning the resist 108 on the substrate 101 as shown in FIG. 8A, isotropic wet etching is performed, so that the resist 108 is formed on the upper edge of the recess 303 as shown in FIG. An eaves 108a having a protruding structure is formed.

  In addition, as a fourth example of the prior art, there is a method of forming an eaves shape using a two-layer resist structure. That is, when a resist having a low dissolution rate in a developing solution is used as an upper layer and a fast resist is used as a lower layer and developed after exposure, an eaves shape is obtained. The size of the eaves is controlled by the baking temperature after application of the lower layer resist. When the baking temperature is high, the resist is cured and the dissolution rate in the developer is slowed, so that the eaves are shortened.

  As a conventional pattern formation method, after stably forming a large through hole of about limit resolution in a resist on an n-type semiconductor substrate having a step by wiring or the like, the entire surface of a cresol novolac-naphthoquinonediazide-based positive resist is formed. A polymer material is deposited, an intermix layer is formed between the resist and the polymer material, and the water-soluble polymer material is immersed in water to dissolve it. There is one in which the mixed layer is left to make the diameter of the through hole smaller than the limit resolution (for example, see Patent Document 1).

JP-A-9-270377 (first page, FIGS. 1 and 2)

In the case of the above prior art 1, the lateral dimension of the LDD region affects the FET characteristics in terms of electrical resistance, but the lateral dimension varies due to the use of a method of etching back SiO ₂ with a reactive ion beam. There is a problem that the reproducibility of stable FET characteristics is lacking. Moreover, in the case of the prior art 2, since it is a method using wet etching, there existed a subject that exact dimension control of a recess structure was difficult. In the case of the prior art 3, when the metal used for the electrode is deposited in the recess, the lateral dimension of the electrode greatly affects the FET characteristics. Therefore, it is necessary to accurately control the dimension of the resist shape of the resist. Since the process of forming the eaves and the process of forming the eaves mold cannot be separated, there is a problem that it is difficult to control the dimensions of the eaves mold. Furthermore, in the prior art 4, there is a problem that fine dimensional control is difficult because the dimensional control of the eaves-shaped shape is performed by temperature. The technique described in Patent Document 1 is intended to eliminate the inaccuracy of pattern formation between different surfaces having steps, and is completely different from that used for forming the LDD structure.

  The present invention has been made to solve the above-described problems of the prior art, and it is a first object of the present invention to provide a method of manufacturing a semiconductor device having an LDD structure in which dimensional control of the LDD region is easy and characteristics are stable. The purpose is. It is a second object of the present invention to provide a method for manufacturing a semiconductor device capable of forming recess dimensions with high accuracy. It is a third object of the present invention to provide a method of manufacturing a semiconductor device in which the dimension of the recess sidewall and the metal sidewall portion can be easily controlled when depositing metal on the recess. It is a fourth object of the present invention to provide a method for manufacturing a semiconductor device in which the eaves dimension can be easily controlled.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming a metal electrode on a semiconductor substrate by patterning, a step of forming a resist on the metal electrode, and impurity ions or impurities using the metal electrode and the resist as a mask. A step of implanting atoms to form a first impurity implantation region on the surface of the semiconductor substrate; and a step of increasing a dimension of the resist by a pattern shrink agent to obtain a structure provided with eaves with respect to the metal electrode Then, impurity ions or impurity atoms are implanted using the resist increased in the form of eaves as a mask to form a second impurity implantation region on the surface of the semiconductor substrate, and the first impurity region is formed in the vicinity of the metal electrode. And a step of obtaining a formed LDD structure .

  In the present invention, by increasing the resist size with the pattern shrink agent, the size control of the eaves portion becomes easy, so that the size of the LDD region can be controlled with high accuracy, and therefore the semiconductor device having the LDD structure with stable characteristics can be obtained. A manufacturing method can be provided.

Embodiment 1 FIG.
FIG. 1 is a process diagram schematically showing a main part of a method of manufacturing a semiconductor device having an LDD structure according to Embodiment 1 of the present invention. As a semiconductor device, GaAsFET will be described as an example. First, as shown in FIG. 1A, a metal electrode (material: Au, film thickness: about 3000 mm) 2 is formed on a substrate 1 by patterning, and a resist (film thickness: about 1 μm) 3 is provided on the metal electrode 2. . Next, as shown in FIG. 1B, impurity ions (Si ⁺ ) 4 (or impurity atoms) are implanted using the metal electrode 2 and the resist 3 in the electrode portion as a mask, and a low concentration impurity implantation region is formed on the surface of the substrate 1. 5 is formed. Next, as shown in FIG.1 (c), the pattern shrink agent 6 is apply | coated about 0.3 micrometer in thickness so that these whole may be covered. In addition, as what can be preferably used as the said pattern shrink agent, AZ R500 (brand name) etc. can be mentioned, for example.

  Next, in the state shown in FIG. 1 (c), baking (referred to as mixing baking, for example, heating at a temperature of about 120 ° C. for a predetermined time) causes a cross-linking reaction between the resist 3 and the pattern shrink agent 6, and a hardened layer 7 is formed on the boundary surface. Is formed (for example, about 0.2 μm thick). Since the pattern shrink agent itself is water-soluble, development with water increases the dimension of the resist 3 part by 7 minutes (about 0.2 μm) as shown in FIG. A structure provided with eaves is obtained. In addition, the method using a pattern shrink agent in this way is called a RELACS (Resolution Enhanced Lithographic Assisted by Chemical Schink) method, and the process is called a RELACS process. The first resist that generates an acid component and the second resist mainly composed of a crosslinkable material that crosslinks in the presence of an acid are used when a resist pattern is miniaturized. .

Next, impurity ions (Si ⁺ ) 4A are implanted again by using the resist 3 having an eaves shape increased by the dimension of the hardened layer 7 by the RELACS process as a mask, so that a high concentration is obtained as shown in FIG. Impurity implanted region 8 is formed. Finally, the hardened layer 7 and the resist 3 are removed to obtain an LDD structure in which a low concentration impurity implanted region 5a is formed in the vicinity of the metal electrode 2 as shown in FIG. 1 (f). Note that if the lateral dimension of the low-concentration impurity implantation region 5a, which is the LDD region, changes, the electrical resistance changes, which greatly affects the electrical characteristics of the FET. However, in the RELACS process, the temperature of the above-mentioned mixing bake and the number of RELACS process repetitions (the cured layer thickness increases as the number of RELACS processes is repeated) are adjusted to accurately control the amount of increase in resist size, that is, the thickness of the cured layer. Therefore, the lateral dimension of the LDD region can be accurately and stably reproduced. The position accuracy of the LDD structure also affects the device characteristics. However, since the self-aligned structure is used with the metal electrode 2 as a mask during the first impurity ion 4 implantation, the position of the LDD structure can be determined with high accuracy. .

  As described above, according to the first embodiment, in the manufacturing method of the GaAsFET having the LDD structure, the step of increasing the size of the resist 3 by the pattern shrink agent 6 is performed, thereby increasing the amount of increase in the resist size, that is, the eaves portion. The thickness of the hardened layer 7 to be formed can be easily and accurately controlled. Therefore, an FET having an LDD structure with stable characteristics can be obtained. Note that the method shown in the first embodiment as described above is performed by using a MOSFET having single crystal silicon as an active layer, an FET having a silicon-based compound (for example, silicon carbide SiC) as an active layer, amorphous silicon, or polycrystalline silicon. The present invention can be similarly applied to MOSTFTs used as active layers, FETs using compound semiconductors (for example, gallium nitride GaN) as active layers, and various electric effect devices.

Embodiment 2. FIG.
FIG. 2 is a process diagram schematically showing a main part of a method of manufacturing a semiconductor device having an LDD structure according to Embodiment 2 of the present invention. The second embodiment shows an example of forming a multi-LDD structure using the RELACS method. After performing the same process as in the first embodiment up to the structure shown in FIG. 1C, mixing baking is performed at a lower temperature (for example, about 100 ° C.) and developed with water as shown in FIG. 2A. In addition, an eaves structure in which the thickness of the hardened layer 7A is thinner than that of the first embodiment is obtained. Next, using this as a mask, a second implantation of impurity ions (Si ⁺ ) 4B is performed as shown in FIG. 2B to form an intermediate concentration impurity (Si ⁺ ) implantation region 9 having a medium concentration.

Next, as shown in FIG. 2 (c), when the pattern shrink agent 6A is applied again, mixing baking (about 100 ° C.) is performed, and development with water further increases the thickness by the amount of the secondary cured layer 7B. Eaves structure such as) is obtained. Next, by implanting impurity ions (Si ⁺ ) 4C for the third time, a high concentration impurity implantation region 8A is obtained as shown in FIG. 2 (e), and finally the secondary hardened layer 7B, hardened layer 7A, and By peeling the resist layer made of the resist 3, a multi-LDD structure is obtained in which the impurity ion implantation concentration changes stepwise as shown in FIG. In this example, the case of forming a double LDD structure has been described. However, by increasing the number of RELACS processes in the same manner, a multiple LDD structure can be formed.

  As described above, according to the second embodiment, the process of increasing the resist size by the pattern shrink agent and the step of implanting impurity ions is repeated a plurality of times, so that the impurity concentration in the vicinity of the electrodes is decreased stepwise. The LDD structure can be easily formed. This method is applicable to MOSFETs using single crystal silicon as an active layer, FETs using silicon-based compounds (for example, silicon carbide SiC) as active layers, MOSTFTs using amorphous silicon or polycrystalline silicon as active layers, compound semiconductors (for example, Needless to say, the present invention can be preferably applied to FETs having various active layers such as gallium arsenide (GaAs) or gallium nitride (GaN), or various electric effect devices. The impurity ions may be impurity atoms.

Embodiment 3 FIG.
FIG. 3 is a process diagram schematically showing a main part of a method for forming a multi-stage recess structure using the RELACS method according to the third embodiment of the present invention. The inventions after the third embodiment are applied inventions of the first embodiment. First, a resist 3A is patterned on the substrate 1 to form a structure as shown in FIG. Next, a recess 11 is formed on the substrate 1 by processing with the reactive ion beam 10 to obtain a first-stage recess structure as shown in FIG. Next, a pattern shrink agent 6B is applied (FIG. 3C). Next, baking is performed at a predetermined temperature to form a hardened layer (thickness: about 0.2 μm) 7C, and development is performed with water to form eaves on the upper edge of the recess 11 as shown in FIG. Get the structure. The processing is performed again with the reactive ion beam 10A, and the second-stage recess 12 is formed at the bottom of the first-stage recess 11 (FIG. 3E). Finally, the resist 3A and the hardened layer 7C are peeled off, and a two-step recess structure as shown in FIG. 3F can be formed with high dimensional accuracy.

  As described above, according to the third embodiment, since the dimensional accuracy of the two-step recess is good, it is possible to stably obtain a semiconductor device with uniform characteristics. Such a recess structure is often used for a field effect transistor in which a compound semiconductor or the like having a large surface level is used as an active layer. For example, in an FET in which a gate electrode is provided in the lower stage of the recess 12, the resistance between the source electrode and the gate electrode (not shown) is reduced, and the leakage current flowing on the semiconductor surface is reduced. A transistor with improved resistance can be obtained. In the third embodiment, the case where the two-stage recess structure is formed is exemplified. However, an arbitrary multi-stage recess structure can be formed by repeating the same process. It can also be combined with the first or second embodiment.

Embodiment 4 FIG.
FIG. 4 is a process diagram schematically showing a recess eaves dimension control method using the RELACS method according to Embodiment 4 of the present invention. When depositing metal (for example, Al) on the bottom of the recess formed on the substrate, it is often necessary to control the distance between the recess sidewall and the metal sidewall (approximately 0.2 μm). Form 4 can be preferably used in such a case. First, a recess 11 having a desired size is formed on the substrate 1 provided with the resist 3A in the same flow as in FIG. 3D, and then a hardened layer 7C is formed to a desired thickness by RELACS processing. A mold shape is formed (FIG. 4A).

  The eaves dimension t is controlled by controlling the thickness of the hardened layer 7C by the mixing bake temperature or the number of repetitions of the RELACS process. Next, the metal film 13 is deposited as shown in FIG. 4B, and the metal film 13, the hardened layer 7C, and the resist 3A are removed by lift-off, so that the side wall of the recess 11 as shown in FIG. Thus, a structure is obtained in which the distance t1 (t≈t1) between the metal 13a deposited on the bottom of the recess 11 and the side wall thereof is controlled to a desired value. According to the fourth embodiment, since the structural dimensional control can be performed with high accuracy, a semiconductor device having stable electrical characteristics can be obtained. The fourth embodiment can be combined with the first to third embodiments.

Embodiment 5 FIG.
FIG. 5 is a process diagram schematically showing the eaves dimension control method for a two-layer resist structure using the RELACS method according to Embodiment 5 of the present invention. First, as shown in FIG. 5A, a first resist 14 having a high dissolution rate with respect to the developer is applied to the substrate 1, and a second resist 15 having a low dissolution rate with respect to the developer is applied thereon (two layers). Both are exposed to a predetermined light 16 after the film thickness is about 1 μm. Since the second resist 15 having a low dissolution rate is applied to the upper layer and the first resist 14 having a high dissolution rate is applied to the lower layer, the periphery of the first and second resists as shown in FIG. A structure having an eaves 15 a in which the upper portion of the recess 17 surrounded by 14, 15 is formed by the second resist 15 can be formed.

  The projecting dimension a toward the center of the eaves 15a formed by the second resist 15 due to the difference in dissolution rate is controlled by the baking temperature after the first resist 14 is applied. It can only be roughly adjusted. Therefore, the RELACS process capable of performing the next fine dimension control is used. That is, when the pattern shrink agent 6C is applied as shown in FIG. 5C, and after development after mixing baking, the dimension is controlled by the hardened layer 7D on the center side of the eaves 15a as shown in FIG. Is obtained in a desired size. Thus, the dimension-controlled eaves structure can be preferably used when, for example, a wiring of various semiconductor devices such as FETs is deposited. The quality of the obtained semiconductor device can be made uniform because the dimensional control of the eaves can be performed with high accuracy. In addition, it is also free to combine this Embodiment 5 with the said Embodiment 1-4.

Process drawing which shows typically the principal part of the manufacturing method of the semiconductor device which has the LDD structure concerning Embodiment 1 of this invention. Process drawing which shows typically the principal part of the manufacturing method of the semiconductor device which has the LDD structure concerning Embodiment 2 of this invention. Process drawing which shows typically the principal part of the multistage recess structure formation method using the RELACS method which concerns on Embodiment 3 of this invention. Process drawing which shows typically the eaves dimension control method of a recess using the RELACS method by Embodiment 4 of this invention. FIG. 5 is a process diagram schematically showing the eaves dimension control method for a two-layer resist structure using the RELACS method according to Embodiment 5 of the present invention. Process drawing which shows the manufacturing method of the semiconductor device which has LDD structure as a 1st example by a prior art. Process drawing which shows the method of forming a 2 step | paragraph recess in the board | substrate as a 2nd example by a prior art. The process figure which shows the method of comprising the eaves-shaped shape in the case of forming a recess in the board | substrate as a 3rd example by a prior art, and depositing the metal used for an electrode etc. there.

Explanation of symbols

  1 substrate, 2 metal electrode, 3, 3A resist, 4, 4A, 4B, 4C impurity ions (or impurity atoms), 5, 5a low concentration impurity implantation region, 6, 6A, 6B, 6C pattern shrink agent, 7, 7A 7C, 7D hardened layer, 7B secondary hardened layer, 8A high concentration impurity implantation region, 9 medium concentration impurity implantation region, 10, 10A reactive ion beam, 11 recess, 12 recess (multi-step recess), 13 metal film, 13a Metal, 14 first resist, 15 second resist, 15a eaves, 16 light, 17 recesses.

Claims (2)

Forming a metal electrode on a semiconductor substrate by patterning;
Forming a resist on the metal electrode;
Implanting impurity ions or impurity atoms using the metal electrode and the resist as a mask to form a first impurity implantation region on the surface of the semiconductor substrate;
Increasing the size of the resist with a pattern shrink agent to obtain a structure provided with eaves with respect to the metal electrode;
Impurity ions or impurity atoms are implanted using the resist increased in the form of eaves as a mask to form a second impurity implantation region on the surface of the semiconductor substrate, and the first impurity region is formed in the vicinity of the metal electrode. And a step of obtaining an LDD structure . After increasing the size of the resist by the pattern shrink agent, by repeating several times the step of implanting impurity ions or impurity atoms, semiconductor according to claim 1, characterized in that to form the LDD structure of the multiple Device manufacturing method.

Images