JP4934396B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device including a constant current circuit.

For example, Patent Document 1 discloses a bias circuit including a first bias circuit, a second bias circuit, a current summing circuit, a first pull-down unit, a second pull-down unit, and an automatic pulse generator. The first bias circuit generates a current having a positive temperature characteristic, the second bias circuit generates a current having a negative temperature characteristic, and the current summing circuit generates the currents of the first and second bias circuits. Add together and output the first bias current. The first and second pull-down means drop the terminal voltages in the first and second bias circuits, respectively, in response to the start pulse from the automatic pulse generator, and start these circuits. By using such a configuration, the bias current can quickly reach a predetermined level when transitioning from the power-down state to the active state.
JP 2000-242347 A

  In recent years, demand for mobile devices such as mobile phones has increased. In particular, since mobile devices are driven by a battery, low power consumption is strongly required. Therefore, in LSIs mounted on mobile devices, etc., for example, the interior is divided into a plurality of circuit blocks, and circuit blocks that are not used in a certain time zone are put into a standby state to reduce power consumption. Yes.

  FIG. 13 is a circuit diagram showing an example of a schematic configuration of a semiconductor integrated circuit device studied as a premise of the present invention. The semiconductor integrated circuit device shown in FIG. 13 includes a circuit block BLK provided between a power supply voltage VDD and a ground voltage VSSM, and a plurality of power switches (NMOS transistors) PSW1 to PSWn that connect this VSSM to a common ground voltage VSS. And a power switch controller VSWC that controls ON / OFF of PSW1 to PSWn. The VSWC includes PMOS transistors MP11 and MP12 connected in parallel between the gate VSWGT of the PSW1 to PSWn and the power supply voltage VCC, and an NMOS transistor MN7 connected between VSWGT and VSS, and controls on / off of these transistors. Thus, on / off of PSW1 to PSWn (that is, BLK active / sleep) is controlled.

  FIG. 14 is a waveform diagram showing an operation example of the circuit of FIG. First, when the signal req is asserted from the sleep state, the wake-up state is entered. In the wake-up state, first, MP11 is driven on and MN7 is driven off via the driver circuit DV1, and MP11 functions as the PMOS drive element IS_ref to charge the gate capacitance of VSWGT. However, since the drive capability of MP11 is designed to be low, some time (corresponding to time T10) is required until PSW1 to PSWn exceed the threshold value.

  When PSW1 to PSWn exceed the threshold value, the charge stored in VSSM or the like (charge charged to the VCC level) is discharged toward VSS at time T11. As a result, an inrush current is generated. At this time T11, the potential of VSWGT does not increase with the discharge of the electric charge, and is maintained at a substantially constant potential. When the discharge of the electric charge is completed, the potential of VSWGT gradually increases again at time T12. When the potential of the signal VSWMO (signal for monitoring the farthest end potential of VSWGT) exceeds the threshold value of the Schmitt trigger circuit SCH1, the MP12 is driven to turn on via the NAND circuit ND3.

  MP12 is designed to have a higher driving capability than MP11. When MP12 is turned on, the potential of VSWGT rises rapidly, and PSW1 to PSWn are driven to a strong on state (corresponding to time T13). Then, when the potential of VSWMO exceeds a predetermined detection potential (for example, a potential close to VCC) by the comparator circuit CMP1, the signal ack is asserted, whereby wakeup is completed and BLK transitions to an active state. When the signal req is negated, MP11 and MP12 are turned off, MN7 is driven on, and BLK transitions to the sleep state.

  In such a power switch controller VSWC, the wake-up time (that is, the transition time from the power-off state to the power-return state) is shortened as much as possible, and the peak of the inrush current generated due to the power-return is as much as possible. It is required to suppress. However, both are in a trade-off relationship. For example, when the VSWGT of FIG. 13 is rapidly charged in a short time in order to shorten the wake-up time, the peak of the inrush current described above increases. In this case, for example, a large noise wraps around other circuit blocks connected to the VSS, thereby causing a malfunction or the like. On the other hand, in order to suppress the peak of the inrush current, it is necessary to control the charging speed of the VSWGT to some extent. However, if this is done, the wake-up time becomes longer and the convenience of the mobile device or the like decreases.

  Therefore, in FIG. 13 and FIG. 14, the VSWGT is charged in two stages by MP11 and MP12 in order to maintain the trade-off balance described above. However, in this circuit, for example, variations in the wake-up time and inrush current may occur due to variations in the PMOS drive element IS_ref. That is, in the PMOS transistor MP11 in IS_ref, when process variation, power supply voltage VCC variation, temperature dependency, or the like occurs, a situation occurs in which the wake-up time becomes excessive or the inrush current becomes excessive. As a result of simulation studies taking such variations into consideration, it has been found that the wake-up time T1 (and the peak value of the inrush current) varies about 3 to 5 times as shown by the solid line and the wavy line in FIG. did. Normally, reliability is emphasized, and the wake-up time is often sacrificed in order to design the inrush current so as not to exceed the standard value even if variations occur (that is, to narrow down the MP11 drive capability). .

  In order to solve such a problem, for example, a technique of driving the power supply switches PSW1 to PSWn with a stable bias current using a technique such as Patent Document 1 can be considered. However, in the technique of Patent Document 1, once the bias circuit is activated by the start pulse, a steady current continues to flow through the bias circuit while the power supply voltage is turned on, so that sufficient power consumption can be reduced. There is no fear. Further, when a load circuit having a large load capacity, such as a power switch, is driven, it may not be possible to shorten the time until the load circuit is brought into a stable state (ie, corresponding to the wake-up time described above). Furthermore, since the current of the second bias circuit is generated using the current of the first bias circuit, there is a possibility that sufficient temperature compensation characteristics cannot be obtained.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can make a load stable in a short time. Another object of the present invention is to realize low power consumption of a semiconductor integrated circuit device equipped with a bias circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor integrated circuit device according to the present invention includes a pulse generation circuit, a first circuit and a second circuit, a first transistor and a second transistor, a first switch circuit and a second switch circuit, a first precharge circuit, and a first precharge circuit. It is a constant current circuit having two precharge circuits. The pulse generation circuit generates a one-shot pulse signal when the first signal is activated. The first transistor is driven by the first circuit to output a first current, and the second transistor is driven by the second circuit to output a second current. The first circuit drives the first transistor such that the first current has a positive or negative temperature characteristic, and conversely, the second circuit causes the second current to have a negative or positive temperature characteristic. To drive the second transistor. Then, a constant current output is obtained by adding the first current and the second current. The first switch circuit and the second switch circuit are provided in the power supply paths (that is, between the power supply voltage and the ground voltage) of the first circuit and the second circuit, respectively, and when the first signal is deactivated And the power supply to the first circuit and the second circuit is cut off. The first and second precharge circuits receive the one-shot pulse signal from the pulse generation circuit, respectively, and overdrive the first and second transistors during the pulse period.

  By using such a constant current circuit, it is possible to generate a constant current with little variation without depending on temperature or the like. Further, when driving a load with such a constant current circuit, the load can be stabilized in a short time. That is, by performing initial charge of the load capacitance by the first and second precharge circuits, it is possible to create a state in which the load can be stably driven with a constant current in a short time. Furthermore, when there is no need to drive a load, the first and second switch circuits can reduce power consumption.

  Here, as the first circuit, for example, a current mirror circuit composed of two PMIS transistors and a current mirror circuit composed of two NMIS transistors are connected in two stages, and the current value is set to the source of one NMIS transistor. The structure which added this 1st resistance is mentioned. In this case, if the resistance has no temperature dependence, the power supply voltage and process dependence are small, and a current having a positive temperature characteristic can be generated. By driving the first transistor with this current, the first transistor is driven. One current also has a positive temperature characteristic. On the other hand, as the second circuit, for example, a configuration in which a plurality of diode-connected PMIS transistors are connected in series, and the second transistor is driven with a potential based on a threshold value obtained thereby. In this case, the second current also has a negative temperature characteristic along with the negative temperature characteristic of the threshold value. Thus, by generating currents having positive or negative temperature characteristics with independent circuit configurations, it is possible to generate a constant current having no temperature dependence with high accuracy.

  The semiconductor integrated circuit device according to the present invention includes a circuit block that can be powered off by a power switch, and is configured to drive the power switch in parallel with the third transistor and the constant current circuit as described above. . Here, in the process of transitioning the power switch from OFF to ON, first, the power switch is turned on to some extent while being driven while being suppressed by a constant current circuit to prevent a large inrush current from flowing through the power switch. Then, driving by the third transistor is started. At this time, by using the first and second precharge circuits of the constant current circuit as described above, the time until the power switch having a large capacity exceeds the threshold can be shortened. In addition, since the current variation of the constant current circuit is small, the variation of the inrush current value and the length of the period is small in the period until the drive by the third transistor is started, and the average of the period The value can also be shortened. Furthermore, the power consumption can be reduced by stopping the operation of the constant current circuit with the first and second switch circuits described above while the power switch is turned off or after it is sufficiently turned on.

  A brief description of effects obtained by typical ones of the inventions disclosed in the present application can realize a semiconductor integrated circuit device capable of setting a load in a stable state in a short time. In addition, power consumption of the semiconductor integrated circuit device can be reduced.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like exist. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  In the following embodiments, a PMOS (P-Metal Oxide Semiconductor) transistor is used as an example of a p-channel type MIS (Metal Insulator Semiconductor) transistor (PMIS transistor), and an n-channel type MIS transistor (NMIS transistor). As an example, an NMOS transistor is used. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. The semiconductor integrated circuit device shown in FIG. 1 is a constant current circuit IS that receives an enable signal EN and starts outputting a constant current I. The constant current circuit IS includes a startup circuit ST-UP, a current bias circuit IBIAS, a temperature correction circuit T-CPS, switch circuits SW1 and SW2, precharge circuits PC1 and PC2, and an output transistor (here, a PMOS transistor). It consists of MP1, MP2, etc. MP1 and MP2 have a source connected to the power supply voltage VCC and a drain connected in common.

  The start-up circuit ST-UP outputs a one-shot pulse signal when the enable signal EN is activated. The current bias circuit IBIAS is activated in response to the activation of the output signal from the ST-UP and the enable signal EN, and drives the control input node (gate) of the MP1 so that the MP1 outputs the current I1. The temperature correction circuit T-CPS is activated in response to the activation of the enable signal EN, and drives the control input node (gate) of the MP2 so that the MP2 outputs the current I2. The switch circuit SW1 is provided in the power supply path of IBIAS (that is, between IBIAS and the power supply voltage or between the ground voltage). Here, the NMOS transistor MN1 is provided between IBIAS and the ground voltage VSS, and the connection between IBIAS and VSS is disconnected in response to the deactivation of the enable signal EN. Similarly, the switch circuit SW2 is provided in the power supply path of the T-CPS. Here, the NMOS transistor MN2 is provided between the T-CPS and VSS, and the connection between the T-CPS and VSS is disconnected in response to the deactivation of the enable signal EN.

  The precharge circuit PC1 is connected to the gate of MP1. Here, the NMOS transistor MN3 is provided between the gate of MP1 and VSS, and the gate of MP1 is driven to VSS based on the pulse width of the one-shot pulse signal from ST-UP. That is, MP1 is overdriven for a time determined by ST-UP, and the load capacitance at the output node (drain) of MP1 is precharged. Similarly, the precharge circuit PC2 is connected to the gate of MP2. Here, the NMOS transistor MN4 is provided between the gate of MP2 and VSS, and the gate of MP2 is driven to VSS based on the pulse width of the one-shot pulse signal from ST-UP. That is, MP2 is overdriven for a time determined by ST-UP, and the load capacitance at the output node (drain) of MP2 is precharged.

  FIG. 2 is a conceptual diagram showing the basic concepts of the current bias circuit and the temperature correction circuit in FIG. In FIG. 2, the current I is generated by adding (ADD) the main current bias circuit IBIASm that generates the current I1 and the sub current bias circuit IBIASs that generates the current I2. The IBIASm has a positive temperature characteristic in which the current I increases as the temperature increases, or a negative temperature characteristic in which the current I decreases as the temperature increases. On the other hand, IBIASs has a negative temperature characteristic when IBIASm has a positive temperature characteristic, and has a positive temperature characteristic when IBIASm has a negative temperature characteristic. Then, the combined current I (= I1 + I2) can be a constant current independent of temperature.

  This IBIASm corresponds to IBIAS and MP1 in FIG. 1, and IBIASs corresponds to T-CPS and MP2 in FIG. The magnitude of each current may be designed, for example, such that the current I1 from IBIASm is larger than the current I2 from IBIASs. That is, first, IBIASm is designed, and IBIASs is designed so that the temperature dependent gradient of the output current I1 can be canceled by the temperature dependent gradient of the current I2. Here, IBIASs does not use the current of IBIASm as in Patent Document 1 described above, and is a circuit completely independent from IBIASm, so that the temperature-dependent gradient can be determined by IBIASs alone. This makes it possible to design a constant current having no temperature dependency easily or with high accuracy.

  As described above, for example, the following effects can be obtained by using the constant current circuit as shown in FIG. First, the start-up circuit ST-UP activates the current bias circuit IBIAS and overdrives the output transistors MP1 and MP2 via the precharge circuits PC1 and PC2, so that the load can be stabilized in a short time. It becomes possible to. That is, for example, when it is desired to drive a transistor having a large load capacity in a stable bias state, it takes time to exceed the threshold value of the transistor as an initial stage. If the configuration of FIG. 1 is used, this time can be shortened, and the time until the load becomes stable can also be shortened. In addition, when the constant current circuit has temperature dependence, the time until the load is brought into a stable state increases as the current I varies. When the configuration of FIG. 1 is used, such a variation can be suppressed, and the load can always be stabilized in a short time.

  Secondly, when the switch circuits SW1 and SW2 are driven off by the enable signal EN, the power consumption of the current bias circuit IBIAS and the temperature correction circuit T-CPS can be reduced, and there is no need to operate the constant current circuit IS. In addition, low power consumption can be achieved. That is, normally, the bias circuit (constant current circuit) is often used while it is always turned on because it takes time to reach a stable state. However, if the configuration of FIG. 1 is used, even if the operation of IBIAS or T-CPS is stopped when it is not necessary, the subsequent recovery time (that is, from when the constant current circuit IS is started until the load is stabilized) ) Can be shortened, and no particular problem occurs.

  FIG. 3 is a circuit diagram showing an example of a detailed configuration of the semiconductor integrated circuit device of FIG. In FIG. 3, the setup circuit ST-UP includes, for example, a one-shot pulse generation circuit PG and a PMOS transistor MP7 having a gate connected to the output node Na and a source connected to the power supply voltage VCC. PG is a circuit that performs an NAND operation on the enable signal EN and a signal obtained by delaying EN by an odd number (in this case, five stages) of inverter circuits. The pulse width of one shot pulse depends on the number of stages of these inverter circuits. Is determined.

  The current bias circuit IBIAS includes a two-stage current mirror circuit in which a current mirror circuit composed of PMOS transistors MP3 and MP4 is stacked on a current mirror circuit composed of NMOS transistors MN5 and MN6, and a resistor R1 for setting a current value. It has become a preparation. The sources of MP3 and MP4 are connected to the power supply voltage VCC, the gates of MP3 and MP4 are connected in common, the drain of MP3 is connected to the drain of MN5, and the drain of MP4 is connected to the drain of MN6 and the gate of MP4. . The drain of MN5 is connected to the drain of MP3 and the gate of MN5, the gate of MN5 is connected in common to the gate of MN6, the source of MN5 is connected to the common node Nc, and the drain of MN6 is connected to the drain of MP4. The source of MN6 is connected to Nc via resistor R1.

  For such IBIAS, the drain output of MP7 in ST-UP is input to the drains of MP3 and MN5, the drain output of PMOS transistor MP8 having the enable signal EN as the gate input and the power supply voltage VCC as the source input is MP3. , MP4 are input to the gates. On the other hand, the node Nb serving as the drain output of MP4 and MN6 is connected to the gate of the output transistor (PMOS transistor) MP1. Further, an NMOS transistor MN2 serving as a switch circuit SW2 is provided between the common node Nc and the ground voltage VSS. The source of the MN2 is connected to VSS, the drain is connected to Nc, and the gate is connected to EN.

  The temperature correction circuit T-CPS is, for example, a circuit in which the diode-connected PMOS transistors MP5 and MP6 and the resistor R2 are directly connected. That is, the source of MP5 is connected to the power supply voltage VCC, the gate and drain of MP5 are connected in common, the source of MP6 is connected to the gate and drain of MP5, the gate and drain of MP6 are connected in common and the resistance Connected to one end of R2. The drain output of MP6 is input to the gate of the output transistor (PMOS transistor) MP2. Further, an NMOS transistor MN1 serving as a switch circuit SW1 is provided between the other end of the resistor R2 and the ground voltage VSS. The source of the MN1 is connected to VSS, the drain is connected to R2, and the gate is connected to EN.

  On the other hand, the NMOS transistor MN3 serving as the precharge circuit PC1 is connected to the gate of the output transistor MP1, and the NMOS transistor MN4 serving as the precharge circuit PC2 is connected to the gate of the output transistor MP2. MN3 has a source connected to VSS and a drain connected to the gate of MP1, and a signal obtained by inverting the output of the one-shot pulse generation circuit PG by the inverter circuit IV1 is input to the gate. Similarly, the source of MN4 is connected to VSS, the drain is connected to the gate of MP2, and a signal obtained by inverting the output of PG by IV1 is input to the gate. Further, the MP1 and MP2 gates are provided with MP9 having the MP1 gate as a drain and the power supply voltage VCC as a source, and MP10 having the MP2 gate as a drain and the power supply voltage VCC as a source. , Connected to the enable signal EN. Thereby, when EN is inactive, MP1 and MP2 are turned off.

  Next, the operation of the semiconductor integrated circuit device of FIG. 3 will be described. 4 shows a part of the semiconductor integrated circuit device of FIG. 3 extracted. FIG. 4A is a circuit diagram around the current bias circuit, and FIG. 4B is a circuit diagram around the temperature correction circuit. . As shown in FIG. 4A, the gate-source voltage of MN5 in the current bias circuit IBIAS is Vgs1, the gate-source voltage of MN6 is Vgs2, and the source-drain currents of MN5 and MN6 are Ia and If it is set to Ib, the relationship of Formula (1) will be materialized.

Vgs1 = Vgs2 + Ib × R1 (1)
Considering that the element size (W / L) of MN6 is N times the element size of MN5 and that MN5 and MN6 operate in the saturation region based on Expression (2), the relational expression of Expression (2) is By substituting into equation (1), equation (3) is obtained.

Ids = μ × Cox / 2 × (W / L) × (Vgs−Vth) ² (2)

ここで、ＭＰ３とＭＰ４の素子サイズ（Ｗ／Ｌ）が同一と仮定すると、Ｉａ＝Ｉｂであることを要求する。したがって、Ｉｂは、式（４）で与えられる。

Here, assuming that the element sizes (W / L) of MP3 and MP4 are the same, it is required that Ia = Ib. Therefore, Ib is given by equation (4).

式（４）において、移動度μは温度に反比例するため、Ｉｂは温度に比例し、正の温度特性を持つ。したがって、Ｉｂを出力トランジスタＭＰ１によってミラーリングした電流Ｉ１も、正の温度特性を持つことになる。

In equation (4), since mobility μ is inversely proportional to temperature, Ib is proportional to temperature and has a positive temperature characteristic. Therefore, the current I1 obtained by mirroring Ib by the output transistor MP1 also has a positive temperature characteristic.

  On the other hand, in FIG. 4B, when the gate-source voltage of the output transistor MP2 is Vgs3 and MP2 operates in the saturation region in a steady state, the source-drain current I2 of MP2 is given by the equation (2) described above. Is given by equation (5).

I2 = μ × Cox / 2 × (W / L) × (Vgs3-Vth) ² (5)
Here, Vgs3 becomes Vgs3 = 2Vth by MP5 and MP6, which are diode-connected in the temperature correction circuit T-CPS. Therefore, substituting this into equation (5) yields equation (6).

I2 = μ × Cox / 2 × (W / L) × (Vth) ² (6)
In the equation (6), the mobility μ is inversely proportional to the temperature, and the threshold value Vth decreases as the temperature rises. Therefore, I2 is inversely proportional to the temperature and has a negative temperature characteristic. Therefore, by adjusting the element size (W / L) of MP2 and the like so that the above-described positive temperature characteristic of I1 can be canceled by the negative temperature characteristic of I2, I1 and I2 as shown in FIGS. Can be a constant current having no temperature dependency. Further, the current I1 is generated by the circuit configuration as shown in FIG. 4A, so that it hardly depends on the power supply voltage VCC or process variations. Or a constant current almost independent of process variations.

  Here, the current I1 from the current bias circuit IBIAS is assumed to have a positive temperature characteristic, but Ib in equation (4) may have a negative temperature characteristic depending on the material of the resistor R1, etc. Accordingly, I1 may have a negative temperature characteristic. In this case, the temperature correction circuit T-CPS may be formed of a generally known circuit having positive temperature characteristics.

  FIG. 5 is a waveform diagram for explaining an operation example related to the startup circuit of FIG. FIG. 5 shows the enable signal EN, the output node Na of the one-shot pulse generation circuit PG, the output node Nb of the current bias circuit IBIAS, and the output current I from the output transistors MP1 and MP2 in FIG. When EN transitions from the “L” level (deactivation level) to the “H” level (activation level), the switch circuit SW2 (MN2) of IBIAS and the switch circuit SW1 (MN1) of the temperature correction circuit T-CPS are turned on. As a result, these become operable, and a one-shot pulse signal of 'L' level is output by PG. Upon receiving this one-shot pulse signal, its drain node is driven to the power supply voltage VCC via MP7, and its drain node Nb is driven to the ground voltage VSS via MN3. As a result, the bias point is instantaneously biased to a bias point at which the IBIAS can normally operate, and a start-up state in which a predetermined current can flow can be obtained. Further, the T-CPS is activated in accordance with the transition of EN to the “H” level.

  On the other hand, during the period when the one-shot pulse signal is at the “L” level, the output transistors MP1 and MP2 are overdriven by turning on MN3 and MN4 (that is, the precharge circuits PC1 and PC2), and a relatively large current I is output. . As a result, even when a load circuit having a large load capacity is connected to the drains of MP1 and MP2, the load circuit can be quickly shifted to the start-up state.

  After that, when the 1-shot pulse signal transitions from 'L' level to 'H' level, the overdrive by MN3 and MN4 stops, and the output node Nb of IBIAS also becomes a predetermined level between VCC and VSS. A stable constant current I determined by the characteristics of IBIAS and T-CPS is output. As a result, the load circuit is also driven in a stable state. In FIG. 5, as a comparison target, a waveform example when the start-up circuit ST-UP is not provided is shown by a broken line, but in this case, a stable constant current I is obtained as compared with the case where the ST-UP is provided. There may be a delay of, for example, several hundred ns until output is possible.

  As described above, by using the semiconductor integrated circuit device according to the first embodiment, a constant current with little variation can be generated at high speed. In addition to this high-speed constant current generation, the function of the precharge circuit described above makes it possible to stabilize the load circuit in a short time even when driving a load circuit with a constant current and a large load capacity. . Further, the function of the switch circuit described above can realize low power consumption when there is no need to generate a constant current.

  Here, the current source PMOS transistors MP1 and MP2 are used as the output transistors in FIG. 1, but in some cases, a current sinking NMOS transistor may be used. In this case, for example, the precharge circuits PC1 and PC2 and the switch circuits SW1 and SW2 may be configured by PMOS transistors whose sources are the power supply voltage VCC. In this case, in FIG. 3, for example, the resistor R1 in the current bias circuit IBIAS is installed on the source side of the PMOS transistor, the temperature correction circuit T-CPS is configured by diode connection of the NMOS transistor, The element may be moved and changed so that the polarities and the like match as appropriate.

(Embodiment 2)
In the second embodiment, a case will be described in which the constant current circuit IS described in the first embodiment is applied to control for shutting down an internal power supply. FIG. 6 is a block diagram showing an example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. A semiconductor integrated circuit device (semiconductor chip CP) shown in FIG. 6 includes a plurality of circuit blocks BLK1 to BLK3, BLK_cm, and BLK_ag, a plurality of systems of power supply voltages VDD and VCCA, and a plurality of systems of ground voltages VSSM1 to VSSM3, VSS, and VSSA. And various power cut-off circuits for controlling the power cut-off of each circuit block.

  The power cutoff circuit includes a plurality of power switches PSW_BK1 to PSW_BK3, a plurality of power switch controllers VSWC1 to VSWC3, a system controller SYSC, and the like. PSW_BK1 to PSW_BK3 are, for example, thick-film MOS transistors or thin-film MOS transistors. From the viewpoint of reducing gate leakage current, it is desirable to use thick-film MOS transistors.

  BLK1 operates with VDD and VSSM1, BLK2 operates with VDD and VSSM2, and BLK3 operates with VDD and VSSM3. BLK1 to BLK3 are, for example, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), a RAM (Random Access Memory), and other specific application IP (Intellectual Property), and perform transmission / reception of data signals and the like. BLK_cm is a clock circuit or RAM that operates in VDD and VSS and is commonly used in each circuit block. BLK_ag operates with VCCA and VSSA, and is an analog circuit such as an ADC (Analog Digital Converter), for example. Such a clock system circuit, an analog circuit, and the like are normally used in a constantly powered state.

  PSW_BK1 is provided between VSSM1 and VSS, PSW_BK2 is provided between VSSM2 and VSS, and PSW_BK3 is provided between VSSM3 and VSS. By individually controlling on / off of the PSW_BK1 to PSW_BK3, it is possible to individually shift to the power shut-off state (sleep state) in a period when the BLK1 to BLK3 are not used. On / off of PSW_BK1 is controlled by VSWC1, on / off of PSW_BK2 is controlled by VSWC2, and on / off of PSW_BK3 is controlled by VSWC3. For example, the SYSC transmits a signal req to the VSWC1 when it is desired to return the BLK1 from the sleep state, and receives the signal ack from the VSWC1 when the power recovery of the BLK1 is completed and becomes the active state. Similarly, SYSC sends signal req to VSWC2 when returning BLK2, and sends signal req to VSWC3 when returning BLK3, and receives signal ack after completion. To do.

  FIG. 7 is a schematic diagram showing an example of the layout configuration of the semiconductor integrated circuit device of FIG. In FIG. 7, the circuit blocks BLK1 to BLK3, BLK_cm, and BLK_ag as described above and the power switch controllers VSWC1 to VSWC3 are arranged in the semiconductor chip CP. On both sides of each of the circuit blocks BLK1 to BLK3, a region of the power switch PSW_BK as described above is provided. In FIG. 6, the description is omitted and one power switch (for example, PSW_BK1) is provided for each circuit block (for example, BLK1). However, actually, a plurality of power switches are used instead of one. Provided in parallel, the plurality of power switches are arranged in the power switch region of FIG.

  FIG. 8 is a circuit diagram showing a configuration example of the power switch controller in the semiconductor integrated circuit device of FIG. The power switch controller VSWC shown in FIG. 8 includes an output transistor (PMOS transistor) MP12, an NMOS transistor MN7, a Schmitt trigger circuit SCH1, a comparator circuit CMP1, an AND circuit AD1, a NAND circuit ND2, and inverter circuits IV2 and IV3. And a constant current circuit IS. The constant current circuit IS is a circuit as shown in FIG. 1 or 3 described in the first embodiment. Then, a plurality of power switches (NMOS transistors) PSW1 to PSWn (for example, corresponding to PSW_BK1 in FIG. 6) are controlled by a signal (signal node) VSWGT which is an output of VSWC, and the circuit block BLK (for example, BLK1 in FIG. 6) is controlled. Applicable) sleep state and active state are controlled.

  The output of the AND circuit AD1 is input to the constant current circuit IS, and the output of the IS is connected to VSWGT. In AD1, one input is a signal req, and the other input is a signal obtained by inverting the signal ack with IV2. The MP12 has a source connected to the power supply voltage VCC, a drain connected to VSWGT, and a gate connected to the output of ND2. In MN7, the source is connected to the ground voltage VSS, the drain is connected to VSWGT, and a signal obtained by inverting the signal req at IV3 is input to the gate. One input of the ND2 is the signal req, and the other input is the output of the Schmitt trigger circuit SCH1. A signal VSWMO which is a feedback signal for monitoring the farthest end potential of VSWGT is input to SCH1. VSWMO is also input to the other end of the comparator circuit CMP1, which has a predetermined detection potential input to one end, and a signal ack is output by CMP1.

  In such a configuration, when the initial state of the circuit block BLK is set to the sleep state, both req and ack are at the ‘L’ level, MN7 is on, and MP12 is off. In the constant current circuit IS, the “L” level is input to the enable signal EN of FIGS. 1 and 3 in accordance with the “L” level of req, and the current bias circuit IBIAS and the temperature correction are performed by the functions of the switch circuits SW1 and SW2. The operation of the circuit T-CPS is stopped. Therefore, in addition to reducing the power consumption of the circuit block BLK as the power switches PSW1 to PSWn are turned off, the power consumption of the constant current circuit IS is also reduced.

  Next, in order to transition BLK from the sleep state to the active state, when req is transitioned from the “L” level to the “H” level, the MN7 is turned off, and the MP12 is also kept off according to the “L” level output of the SCH1. . Then, the constant current circuit IS starts the operation as described in FIGS. That is, IBIAS and T-CPS are activated at high speed, and a relatively large current I associated with the precharge circuits PC1 and PC2 is output to VSWGT at the initial stage. As a result, the large gate capacities of PSW1 to PSWn are rapidly charged, and PSW1 to PSWn are in a state of exceeding the threshold value in a short time. That is, the time T10 can be shortened as described with reference to FIG. Thereafter, a stable constant current I is output as PC1 and PC2 are stopped, and the charge of VSSM is discharged toward VSS while suppressing the inrush current in PSW1 to PSWn.

  After the discharge of the VSSM charge, when the potential of VSWGT rises and the potential of VSWMO exceeds the threshold value of SCH1, the output of ND2 transitions to the 'L' level, which is higher than the output transistor in the constant current circuit IS. MP12 with a sufficiently large driving capability is turned on. As a result, VSWGT is driven to substantially the VCC level, and PSW1 to PSWn are turned on strongly. When VSWGT (VSWMO) is substantially at the VCC level, CMP1 outputs the 'H' level, and ACK is asserted, so that BLK becomes active. Then, the output of AD1 becomes ‘L’ level, the IBIAS and T-CPS in IS are stopped by the switch circuits SW1 and SW2, and the output transistors MP1 and MP2 are driven off. Thus, even when the active state is entered, the power consumption can be further reduced by stopping the IS operation.

  Further, when the transition from the sleep state to the active state is made, since the variation of the constant current circuit IS is small as described above, the transition to the active state can be stably performed in a short time. That is, with reference to FIG. 14 described above, the variation between the solid line and the broken line can be reduced, and the peak value of the inrush current can always be kept at a constant level, and the wake-up time can always be made a constant short time.

  As described above, by using the semiconductor integrated circuit device according to the second embodiment, it is possible to restore the power supply of the circuit block whose internal power supply is cut off in a short time while suppressing the inrush current. In addition to the circuit block, power consumption in the constant current circuit can be reduced when the internal power supply is shut off. Furthermore, even after the circuit block is completely restored, the power consumption in the constant current circuit can be reduced. For this reason, the power consumption of the semiconductor integrated circuit device can be reduced.

(Embodiment 3)
In the third embodiment, a case where the constant current circuit IS described in the first embodiment is applied to control of an I / O circuit will be described. FIG. 9 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The semiconductor integrated circuit device according to the third embodiment includes an I / O circuit IO1 suitable for generating a small amplitude signal as shown in FIG. 9, and includes a PMOS transistor MP22, an NMOS transistor MN22, and a current mirror circuit MLp. , MLn and constant current circuits IS1, IS2 and the like.

  The current mirror circuit MLp is composed of two PMOS transistors MP20 and MP21 having a source connected to the power supply voltage VCC and a gate connected in common, and copies the current of the constant current circuit IS2 connected to the drain of MP20. To the source of MP22. The current mirror circuit MLn includes two NMOS transistors MN20 and MN21 having a source connected to the power supply voltage VSS and a gate connected in common, and copies the current of the constant current circuit IS1 connected to the drain of the MN20. To the source of MN22.

  MP22 has a source connected to MLp, a gate connected to an input signal (signal input node) Vin, MN22 has a source connected to MLn, a gate connected to Vin, and a drain of MP22 and MN22 is commonly connected as a signal output node. Yes. The constant current circuits IS1, IS2 are circuits as shown in FIGS. As for IS2, for example, the output current I from the PMOS transistors MP1 and MP2 in FIGS. 1 and 3 is copied and applied by a current mirror circuit composed of NMOS transistors.

  In such a configuration, when an “H” level signal is input to Vin, the current I based on IS1 flows to the load resistor R20, and when an “L” level signal is input, the current I based on IS2 is It flows to the load resistance R20. As a result, a signal having an amplitude “I × R20” is transmitted to the load resistor R20 with “VCC / 2” as a reference.

  FIG. 10 is a circuit diagram showing an example of another configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The semiconductor integrated circuit device according to the third embodiment includes an I / O circuit IO2 having a slew rate control function as shown in FIG. 10, and includes PMOS transistors MP23 and MP24, NMOS transistors MN23 and MN24, and a constant current circuit. It is constituted by IS1, IS2, capacitors C1, C2, and the like. MP23 has a source connected to power supply voltage VCC, a gate connected to input signal (signal input node) Vin1, and a drain connected to the gates of constant current circuits IS2 and MP24. The MN23 has a source connected to the ground voltage VSS, a gate connected to the input signal (signal input node) Vin2, and a drain connected to the gates of the constant current circuits IS1 and MN24.

  MP24 has a source connected to VCC, a gate connected to IS2 and the like, MN24 has a source connected to VSS and a gate connected to IS1 and the like, and the drains of MP24 and MN24 are commonly connected to signal output node Vout. The capacitor C1 is connected between the gate and drain of the MP24, and the capacitor C2 is connected between the gate and drain of the MN24. The constant current circuits IS1, IS2 are circuits as shown in FIGS. As for IS2, for example, the output current I from the PMOS transistors MP1 and MP2 in FIGS. 1 and 3 is copied and applied by a current mirror circuit composed of NMOS transistors.

  In such a configuration, when an “H” level signal is input to Vin1 and Vin2, the gate charge of MP24 is discharged with a delay time (T = C1 × R) due to the output resistance R of IS2 and the capacitor C1. , The gate charge of MN24 is discharged by MN23. Therefore, the 'H' level signal whose slew rate is controlled by the delay time (T = C1 × R) is output to Vout via the MP24. On the other hand, when an 'L' level signal is input to Vin1 and Vin2, the gate charge of MP24 is charged by MP23, and the gate charge of MN24 is delayed by the output resistance R and capacitance C2 of IS1 (T = C2 × R ) Is charged. Therefore, the ‘L’ level signal whose slew rate is controlled by the delay time (T = C2 × R) is output to Vout via the MN24.

  FIG. 11 is a schematic diagram showing a layout configuration example of a semiconductor integrated circuit device including the I / O circuit of FIG. 9 or FIG. In the semiconductor integrated circuit device (semiconductor chip CP) shown in FIG. 11, for example, a plurality of I / O circuits IO1 and IO2 as described in FIG. 9 or FIG. However, the constant current circuits IS1 and IS2 can be used in common by a plurality of I / O circuits. In the example of FIG. 11, a plurality of constant current circuits IS are arranged in a certain region. A current is supplied to the I / O circuit IO. As a result, the circuit area can be reduced.

  As described above, by using the semiconductor integrated circuit device according to the third embodiment, a high-precision I / O circuit, an I / O circuit capable of reducing power consumption, or an I / O circuit capable of high-speed startup is realized. It becomes possible. That is, constant current circuits IS1 and IS2 with small variations are required in order to perform amplitude control and slew rate control of the output signal as described in FIGS. 9 and 11 with high accuracy. For example, in order to reduce power consumption in the sleep state, it is effective to stop the operation of the constant current circuits IS1 and IS2. Further, in order to return the I / O circuit from the sleep state to the active state in a short time (ie, to start up at high speed), the constant current circuits IS1 and IS2 are started up at a high speed, and the element size is relatively large. It is effective to perform initial charging of the final stage transistors (corresponding to MLp and MLn in FIG. 9 and MP24 and MN24 in FIG. 10) with a large load capacity at high speed. Such a matter can be satisfied by using the constant current circuit IS as described in FIGS. 1 and 3 as can be understood from the above description.

(Embodiment 4)
In the fourth embodiment, a case where the constant current circuit IS described in the first embodiment is applied to control of a regulator circuit will be described. FIG. 12 is a schematic diagram showing an example of the configuration of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 12 includes a regulator circuit VREG, a constant current circuit IS as shown in FIGS. 1 and 3, and a circuit block BLK having a predetermined function such as a CPU.

  VREG includes a PMOS transistor MP30, an amplifier circuit AMP, a phase compensation capacitor C3, and the like. MP30 has a source connected to power supply voltage VCC, a drain connected to BLK and C3, and a gate connected to the output of AMP. One input of the AMP is a reference voltage Vref generated according to the output current from the constant current circuit IS, and the other input is a feedback signal from the drain of the MP30.

  In such a semiconductor integrated circuit device, the magnitude of the power supply voltage supplied to the BLK via the MP30 is determined based on the magnitude of the reference voltage Vref. Therefore, in order to supply a stable power supply voltage to BLK, it is necessary to reduce the variation of the constant current circuit IS. Further, when the circuit block BLK is in the sleep state, the power consumption can be further reduced by stopping the operations of VREG and IS. Furthermore, when returning from the sleep state to the active state, it is necessary to stabilize Vref early and stabilize the power supply voltage supplied from VREG to BLK in a short time.

  Such a matter can be satisfied by using a constant current circuit IS as shown in FIGS. 1 and 3 as can be understood from the above description. That is, for example, in the sleep state, the operation of the current bias circuit IBIAS and the temperature correction circuit T-CPS is stopped by the switch circuit SW, and Vref becomes the ground voltage VSS level. Then, as the output of AMP approaches VCC, MP30 is turned off and VREG is stopped. On the other hand, when returning to the active state, the IS is activated in a short time, and Vref is overdriven for a predetermined time at the initial stage, and the gate of the MP30 having a relatively large capacity is rapidly precharged. As a result, the output of VREG can be stabilized in a short time.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, here, an example in which the constant current circuit is applied to a power switch, an I / O circuit, and a power circuit has been described. However, the present invention is not limited to these, and various types of devices that require high-speed startup and low power consumption are described. It can be used effectively in applications.

  The semiconductor integrated circuit device according to the present invention is a technique that is particularly useful when applied to a semiconductor integrated circuit device having a low power consumption function using a power switch. However, the present invention is not limited thereto, and is not limited to a semiconductor integrated circuit device including a constant current circuit. On the other hand, it is widely applicable.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a conceptual diagram which shows the basic concept of the current bias circuit and temperature correction circuit in FIG. FIG. 2 is a circuit diagram showing an example of a detailed configuration of the semiconductor integrated circuit device of FIG. 1. In the semiconductor integrated circuit device of FIG. 3, a part of the circuit is extracted, (a) is a circuit diagram around the current bias circuit, and (b) is a circuit diagram around the temperature correction circuit. FIG. 4 is a waveform diagram illustrating an operation example related to the startup circuit of FIG. 3. FIG. 5 is a block diagram showing an example of the configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 7 is a schematic diagram illustrating an example of a layout configuration of the semiconductor integrated circuit device of FIG. 6. FIG. 7 is a circuit diagram showing a configuration example of the power switch controller in the semiconductor integrated circuit device of FIG. 6. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 10 is a circuit diagram showing an example of another configuration in the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 11 is a schematic diagram illustrating a layout configuration example of a semiconductor integrated circuit device including the I / O circuit of FIG. 9 or 10. FIG. 10 is a schematic diagram showing an example of the configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. 1 is a circuit diagram showing an example of a configuration outline of a semiconductor integrated circuit device studied as a premise of the present invention. It is a wave form diagram which shows the operation example of the circuit of FIG.

Explanation of symbols

IS constant current circuit IS_ref PMOS drive element ST-UP startup circuit IBIAS current bias circuit T-CPS temperature correction circuit SW switch circuit PC precharge circuit MP PMOS transistor MN NMOS transistor PG 1 shot pulse generation circuit IV inverter circuit R resistance BLK circuit block PSW power switch VSWC power switch controller SYSC system controller CP semiconductor chip ND NAND circuit SCH Schmitt trigger circuit CMP comparator circuit ML current mirror circuit IO I / O circuit C capacity AMP amplifier circuit VREG regulator circuit

Claims (9)

A pulse generation circuit that outputs a second signal having a first pulse width when the first signal is activated;
A first transistor driven by a first node and outputting a first current to an output node;
A second transistor driven by a second node and outputting a second current to the output node;
A first circuit that drives the first node such that the first current increases or decreases with increasing temperature;
A second circuit that drives the second node such that the second current decreases or increases with increasing temperature;
A first switch circuit connected to the power supply path of the first circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A second switch circuit connected to the power supply path of the second circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A first precharge circuit connected to the first node and receiving the second signal and overdriving the first transistor in a period of the first pulse width;
Connected to said second node, receiving said second signal have a second precharge circuit for overdriving the second transistor in the period of the first pulse width,
The first circuit includes:
A first PMIS transistor whose source is connected to the supply voltage;
A second PMIS transistor having a source connected to the power supply voltage and a gate commonly connected to a drain and a gate of the first PMIS transistor;
A first NMIS transistor having a source connected to a third node via a first resistor and a drain connected to the drain of the second PMIS transistor;
A second NMIS transistor having a source connected to the third node, a gate connected in common to the drain and the gate of the first NMIS transistor, and a drain connected to the drain of the first PMIS transistor;
A third PMIS transistor connected between a drain of the first PMIS transistor and the second NMIS transistor and the power supply voltage and having the gate input with the second signal;
The drains of the second PMIS transistor and the first NMIS transistor are the first node,
The semiconductor integrated circuit device, wherein the first switch circuit is a third NMIS transistor connected between the third node and a ground voltage . A pulse generation circuit that outputs a second signal having a first pulse width when the first signal is activated;
A first transistor driven by a first node and outputting a first current to an output node;
A second transistor driven by a second node and outputting a second current to the output node;
A first circuit that drives the first node such that the first current increases or decreases with increasing temperature;
A second circuit that drives the second node such that the second current decreases or increases with increasing temperature;
A first switch circuit connected to the power supply path of the first circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A second switch circuit connected to the power supply path of the second circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A first precharge circuit connected to the first node and receiving the second signal and overdriving the first transistor in a period of the first pulse width;
Connected to said second node, receiving said second signal have a second precharge circuit for overdriving the second transistor in the period of the first pulse width,
The second circuit includes:
A plurality of PMIS transistors connected in series between a power supply voltage and the second node, each diode-connected;
A second resistor connected between the second node and the fourth node;
The semiconductor integrated circuit device, wherein the second switch circuit is an NMIS transistor connected between the fourth node and a ground voltage . A pulse generation circuit that outputs a second signal having a first pulse width when the first signal is activated;
A first transistor driven by a first node and outputting a first current to an output node;
A second transistor driven by a second node and outputting a second current to the output node;
A first circuit that drives the first node such that the first current increases or decreases with increasing temperature;
A second circuit that drives the second node such that the second current decreases or increases with increasing temperature;
A first switch circuit connected to the power supply path of the first circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A second switch circuit connected to the power supply path of the second circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A first precharge circuit connected to the first node and receiving the second signal and overdriving the first transistor in a period of the first pulse width;
Connected to said second node, receiving said second signal have a second precharge circuit for overdriving the second transistor in the period of the first pulse width,
The first circuit includes:
A first PMIS transistor whose source is connected to the supply voltage;
A second PMIS transistor having a source connected to the power supply voltage and a gate commonly connected to a drain and a gate of the first PMIS transistor;
A first NMIS transistor having a source connected to a third node via a first resistor and a drain connected to the drain of the second PMIS transistor;
A second NMIS transistor having a source connected to the third node, a gate connected in common to the drain and the gate of the first NMIS transistor, and a drain connected to the drain of the first PMIS transistor;
The drains of the second PMIS transistor and the first NMIS transistor are the first node,
The first switch circuit is a third NMIS transistor connected between the third node and a ground voltage;
The second circuit includes:
A plurality of PMIS transistors connected in series between a power supply voltage and the second node, each diode-connected;
A second resistor connected between the second node and the fourth node;
The semiconductor integrated circuit device, wherein the second switch circuit is a fourth NMIS transistor connected between the fourth node and the ground voltage . The semiconductor integrated circuit device according to any one of claims 1 to 3 ,
The first transistor and the second transistor are PMIS transistors whose sources are connected to a power supply voltage,
The semiconductor integrated circuit device, wherein the first precharge circuit and the second precharge circuit are NMIS transistors whose sources are connected to a ground voltage. The semiconductor integrated circuit device according to any one of claims 1 to 3 , further comprising:
A circuit block having a predetermined function;
A semiconductor integrated circuit device comprising: a power switch driven by the output node and having a power cutoff function of the circuit block. A circuit block having a predetermined function;
A constant current circuit for outputting a third current to the output node by the activation of the first signal;
A third transistor that outputs a fourth current to the output node by activation of a third signal;
A power switch connected to the power path of the circuit block and driven by the output node;
A first detection circuit that monitors the potential of the output node and activates the third signal when the first potential is reached;
A second detection circuit that monitors the potential of the output node and activates a fourth signal when the second potential is reached;
A control circuit that deactivates the first signal when the fourth signal is activated;
The constant current circuit is:
A pulse generation circuit that outputs a second signal having a first pulse width when the first signal is activated;
A first transistor driven by a first node and outputting a first current that is part of the third current to the output node;
A second transistor driven by a second node and outputting a second current that is another part of the third current to the output node;
A first circuit that drives the first node such that the first current increases or decreases with increasing temperature;
A second circuit that drives the second node such that the second current decreases or increases with increasing temperature;
A first switch circuit connected to the power supply path of the first circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A second switch circuit connected to the power supply path of the second circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A first precharge circuit connected to the first node and receiving the second signal and overdriving the first transistor in a period of the first pulse width;
Connected to said second node, receiving said second signal have a second precharge circuit for overdriving the second transistor in the period of the first pulse width,
The first circuit includes:
A first PMIS transistor whose source is connected to the supply voltage;
A second PMIS transistor having a source connected to the power supply voltage and a gate commonly connected to a drain and a gate of the first PMIS transistor;
A first NMIS transistor having a source connected to a third node via a first resistor and a drain connected to the drain of the second PMIS transistor;
A second NMIS transistor having a source connected to the third node, a gate connected in common to the drain and the gate of the first NMIS transistor, and a drain connected to the drain of the first PMIS transistor;
A third PMIS transistor connected between a drain of the first PMIS transistor and the second NMIS transistor and the power supply voltage and having the gate input with the second signal;
The drains of the second PMIS transistor and the first NMIS transistor are the first node,
The semiconductor integrated circuit device, wherein the first switch circuit is a third NMIS transistor connected between the third node and a ground voltage . A circuit block having a predetermined function;
A constant current circuit for outputting a third current to the output node by the activation of the first signal;
A third transistor that outputs a fourth current to the output node by activation of a third signal;
A power switch connected to the power path of the circuit block and driven by the output node;
A first detection circuit that monitors the potential of the output node and activates the third signal when the first potential is reached;
A second detection circuit that monitors the potential of the output node and activates a fourth signal when the second potential is reached;
A control circuit that deactivates the first signal when the fourth signal is activated;
The constant current circuit is:
A pulse generation circuit that outputs a second signal having a first pulse width when the first signal is activated;
A first transistor driven by a first node and outputting a first current that is part of the third current to the output node;
A second transistor driven by a second node and outputting a second current that is another part of the third current to the output node;
A first circuit that drives the first node such that the first current increases or decreases with increasing temperature;
A second circuit that drives the second node such that the second current decreases or increases with increasing temperature;
A first switch circuit connected to the power supply path of the first circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A second switch circuit connected to the power supply path of the second circuit, turned on when the first signal is activated, and turned off when the first signal is deactivated;
A first precharge circuit connected to the first node and receiving the second signal and overdriving the first transistor in a period of the first pulse width;
Connected to said second node, receiving said second signal have a second precharge circuit for overdriving the second transistor in the period of the first pulse width,
The second circuit includes:
A plurality of PMIS transistors connected in series between a power supply voltage and the second node, each diode-connected;
A second resistor connected between the second node and the fourth node;
The semiconductor integrated circuit device, wherein the second switch circuit is an NMIS transistor connected between the fourth node and a ground voltage . The semiconductor integrated circuit device according to claim 6 or 7 ,
The semiconductor integrated circuit device, wherein the power switch is an NMIS transistor having a source connected to a ground voltage. The semiconductor integrated circuit device according to claim 8 .
The first transistor and the second transistor are PMIS transistors whose sources are connected to a power supply voltage,
2. The semiconductor integrated circuit device according to claim 1, wherein each of the first precharge circuit and the second precharge circuit is an NMIS transistor having a source connected to the ground voltage.

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