JP4924761B1 - Capacitive load drive circuit and fluid ejection device - Google Patents

Abstract

A capacitive load is efficiently driven even with a duty ratio near an upper limit or a lower limit.
A drive waveform signal is pulse-modulated to generate a modulation signal, and after power amplification, a drive signal generated by passing through a smoothing filter is applied to a capacitive load. Under the condition that the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period, the carrier is set so that the absolute value of the maximum value and the minimum value of the current within the one modulation period is equal to or greater than a predetermined threshold value. Change the frequency. If the absolute value of the maximum value and the minimum value of the current flowing through the smoothing filter within one modulation period falls below a predetermined threshold, a large loss occurs during power amplification. Therefore, if the carrier frequency is changed so as not to fall below the predetermined threshold, it is possible to efficiently amplify the power and drive the capacitive load.
[Selection] Figure 15

Description

  The present invention relates to a technique for driving by applying a drive signal to a capacitive load such as a piezoelectric element.

There are many actuators configured by capacitive loads such as piezoelectric elements, such as an ejection head mounted on an inkjet printer. In order to drive such an actuator (that is, a capacitive load), a drive signal having a certain amount of power is required. Therefore, the drive signal is generated by power amplification of the drive waveform signal that is the source of the drive signal. Here, if the analog drive waveform signal is amplified in an analog manner and the analog drive signal is directly generated, a large power loss occurs and power efficiency is lowered. Therefore, power amplification is performed using a so-called class D amplifier. Technology has been proposed (Patent Document 1).
Patent Document 2).

The class D amplifier performs power amplification as follows. First, a modulation signal is generated by pulse-modulating an analog driving waveform signal. Several systems are known for pulse modulation, but a system called pulse width modulation is generally used. A method called pulse width modulation is a period in which the voltage of the drive waveform signal is higher than the voltage of the triangular waveform when the drive waveform signal to be modulated is compared with a triangular waveform that is repeated at a constant period (modulation period). O
In this modulation system, N is output and, conversely, OFF is output during a period when the voltage of the drive waveform signal is lower, thereby generating a modulation signal that repeats ON and OFF. In the modulation signal thus obtained, the ratio of the ON period within one modulation cycle (on duty ratio or duty ratio, referred to as duty ratio in this specification) increases as the voltage of the drive waveform signal increases. Get higher.

In the class D amplifier, after the power of the digital modulation signal obtained by pulse modulation is amplified,
A power-amplified drive signal is generated by converting the analog signal through a smoothing filter. By amplifying the power of the digital modulation signal in this way, the power loss can be greatly reduced compared to the case where the analog drive waveform signal is amplified with the analog power. Loss can be greatly reduced.

JP-A-11-204850 JP 2007-96364 A

However, when driving a capacitive load using a class D amplifier, if the duty ratio of the modulation signal is near the upper limit value or near the lower limit value, a large power loss may occur during amplification. As a result, the capacitive load There is a problem that the power efficiency when driving the battery may decrease.

The present invention has been made to solve at least a part of the above-described problems of the prior art, and can always drive a capacitive load efficiently under any conditions regardless of the duty ratio. The aim is to provide possible technology.

In order to solve at least a part of the problems described above, the capacitive load driving circuit of the present invention employs the following configuration. That is,
A capacitive load drive circuit that drives a capacitive load by applying a drive signal to the capacitive load having a capacitive component,
A drive waveform signal generating circuit for generating a drive waveform signal which is a reference of the drive signal;
A modulation circuit that generates a modulation signal by pulse-modulating the drive waveform signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates the drive signal by smoothing the power amplification modulation signal;
Under a reversing condition in which the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal, the absolute value of the maximum value and the minimum value of the current within the one modulation period is predetermined. The gist of the invention is that it comprises carrier frequency changing means for changing a carrier frequency when the modulation circuit performs pulse modulation so as to be equal to or higher than a threshold value.

In such a capacitive load drive circuit of the present invention, a modulation signal is generated by pulse-modulating a drive waveform signal which is a reference of a drive signal to be applied to the capacitive load, and the obtained modulation signal is power amplified. A drive signal is generated by smoothing later. Also, under the condition that the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal (reversal condition), by changing the carrier frequency, The absolute value of the maximum value and the minimum value of the current is kept above a predetermined threshold value.

Although the detailed mechanism will be described later, under the condition that the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal (reverse condition),
When the duty ratio of the modulation signal is near the upper limit value or near the lower limit value, the absolute values of the maximum value and the minimum value of the current within one modulation period cannot be maintained above a predetermined threshold value. And when the absolute value of the maximum value and the minimum value of the current within one modulation period falls below a predetermined threshold,
It has been found that a large power loss occurs during amplification with a digital power amplifier. Furthermore,
It has also been found that the absolute value of the maximum value and the minimum value of the current within one modulation period can be changed by changing the carrier frequency when the modulation circuit performs pulse modulation. Therefore, under the reverse condition where the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period, the absolute value of the maximum value and the minimum value of the current within the one modulation period is equal to or greater than a predetermined threshold value. By changing the carrier frequency in this manner, it is possible to avoid the occurrence of a large power loss during amplification by the digital power amplifier and to drive the capacitive load efficiently.

Further, the capacitive load driving circuit of the present invention may be configured as follows. First, in a digital power amplifier, a power amplification modulation signal is generated by switching ON / OFF of two switch elements that are push-pull connected between a predetermined voltage generated by a power supply and the ground. In addition, the predetermined voltage generated by the power source of the digital power amplifier is V, the dead time, which is the time to turn off both switch elements when switching the ON / OFF of the two switch elements, is T, When the parasitic capacitance is C, V
The carrier frequency may be changed so that the absolute value of the maximum value and the minimum value of the current within one modulation period does not fall below the threshold value obtained by the calculation formula C / T.

As will be described in detail later, a large power loss occurs during amplification by the digital power amplifier because the maximum and minimum values of current within one modulation period fall below a predetermined threshold value under the above-described inversion conditions. This threshold value is V when the predetermined voltage generated by the power source of the digital power amplifier is V, the dead time is T, and the parasitic capacitance of the two switch elements is C.
-It was found that it can be obtained by the calculation formula C / T. Therefore, if the maximum and minimum values of current within one modulation period are kept below this threshold even under reverse conditions, it is possible to avoid a large power loss during amplification by the digital power amplifier. Is possible.

In the capacitive load drive circuit of the present invention described above, the capacitance Cd of the junction capacitance of the diode is used instead of the capacitance C of the parasitic capacitance of the two switch elements, and is obtained by the calculation formula V · Cd / T The carrier frequency may be changed so that the absolute value of the maximum value and the minimum value of the current within one modulation period does not fall below the threshold value.

Even if the carrier frequency is changed so that the absolute value of the maximum and minimum values of current within one modulation period does not fall below such a threshold, a large power loss occurs during amplification by the digital power amplifier. It becomes possible to avoid doing.

Alternatively, in the above-described capacitive load driving circuit of the present invention, a capacitor is connected in parallel to at least one of the two switch elements, and the capacitance of the combined capacity of the capacitor and the parasitic capacitance of the two switch elements is Cs. Then, the carrier frequency may be changed so that the absolute value of the maximum value and the minimum value of the current within one modulation period does not fall below the threshold value obtained by the calculation formula V · Cs / T.

Even if the carrier frequency is changed so that the absolute value of the maximum and minimum values of current within one modulation period does not fall below such a threshold, a large power loss occurs during amplification by the digital power amplifier. Can be avoided.

In the capacitive load driving circuit of the present invention described above, load information related to the magnitude of the capacitive component of the capacitive load may be acquired, and the carrier frequency may be changed according to this load information.

When the drive signal applied to the capacitive load is not a constant voltage, the absolute value of the maximum value and the minimum value within one modulation period of the current flowing from the digital power amplifier to the smoothing filter is kept above a predetermined threshold value. The carrier frequency to be changed varies depending on the size of the capacitive component of the capacitive load. Therefore, if information (load information) regarding the magnitude of the capacitive component of the capacitive load is acquired and the carrier frequency is changed in consideration of this information, the carrier frequency can be changed appropriately. For example, the capacity component size is classified into multiple stages and set as load information, and the carrier frequency is changed according to the classification indicated in the load information, or the carrier frequency to be changed is corrected. By doing so, it becomes possible to change to a more appropriate carrier frequency.

Further, the capacitive load driving circuit of the present invention can be configured as follows. That is,
A capacitive load drive circuit that drives a capacitive load by applying a drive signal to the capacitive load having a capacitive component,
A drive waveform signal generating circuit for generating a drive waveform signal which is a reference of the drive signal;
A phase lead compensation circuit that performs phase lead compensation on the drive signal and outputs the signal after the phase lead compensation as a feedback signal;
An arithmetic circuit that outputs an error signal by subtracting the feedback signal from the drive waveform signal;
A modulation circuit that generates a modulation signal by pulse-modulating the error signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates the drive signal by smoothing the pulse-wave-shaped power amplification modulation signal;
Under a reversing condition in which the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal, the absolute value of the maximum value and the minimum value of the current within the one modulation period is predetermined. You may make it provide the carrier frequency change means which changes the carrier frequency at the time of the said modulation circuit performing pulse modulation so that it may become more than a threshold value.

In this way, the drive signal applied to the capacitive load is negatively fed back with respect to the drive waveform signal serving as a reference for the drive signal, so that the drive signal is prevented from being distorted due to the resonance of the smoothing filter. Can do. Also, when the drive signal is negatively fed back, it is compensated for phase advance compensation (phase advance compensation) and then negatively fed back. Therefore, the drive signal whose phase is delayed by a smoothing filter is driven negatively. The signal output does not become unstable.

In addition, any of the capacitive load driving circuits of the present invention described above can efficiently drive power and drive a capacitive load. Therefore, the above-described capacitive load driving circuit of the present invention includes the following fluid ejecting apparatus, that is, a supply pump that supplies liquid, a fluid chamber into which the liquid supplied from the supply pump flows, and a capacitive load. And a pulsation generator having an ejection nozzle that ejects the liquid that has flowed into the fluid chamber. By applying a drive signal to the actuator, the liquid that has flowed into the fluid chamber is discharged from the ejection nozzle. The fluid ejecting apparatus ejecting in a pulse form can be suitably applied as a drive circuit that generates a drive signal.

It is explanatory drawing which showed the structure of the fluid injection apparatus carrying the capacitive load drive circuit of 1st Example. It is explanatory drawing which showed the circuit structure of the capacitive load drive circuit of 1st Example. It is explanatory drawing which showed a mode that the power consumption in the digital power amplifier at the time of a fixed voltage output increases according to a duty ratio. It is the circuit diagram which showed the detailed structure of the digital power amplifier. It is explanatory drawing which showed the reason which electric power loss generate | occur | produces at the time of the electric power amplification in a digital power amplifier. It is explanatory drawing which showed a mode that the electric current which flows into the coil of a smoothing filter at the time of the output of a fixed voltage changes substantially linearly. It is explanatory drawing which showed the reason for which the electric current which flows into the coil of a smoothing filter at the time of the output of a fixed voltage changes substantially linearly. It is explanatory drawing which showed a mode that the amplitude of the electric current which flows into the coil of a smoothing filter at the time of the output of a fixed voltage changes according to a duty ratio. It is explanatory drawing which showed the reason that the power loss at the time of power amplification falls on the conditions where a big electric current flows into the coil of a smoothing filter at the time of the output of a fixed voltage. It is explanatory drawing which showed the reason that the power loss at the time of power amplification falls on the conditions where a big electric current flows into the coil of a smoothing filter at the time of the output of a fixed voltage. It is explanatory drawing which showed operation | movement of the digital power amplifier at the time of the output of a fixed voltage according to the magnitude | size of the electric current which flows into the coil of a smoothing filter. It is explanatory drawing which showed the conditions which a power loss does not generate | occur | produce with a digital power amplifier at the time of the output of a fixed voltage. It is explanatory drawing which showed a part of capacitive load drive circuit of 1st Example. It is explanatory drawing which showed a mode that the flag was set to the drive waveform signal in 1st Example. It is explanatory drawing which showed operation | movement of the capacitive load drive circuit of 1st Example. It is a flowchart of the process which sets a flag to drive waveform signal information in 1st Example. It is explanatory drawing which showed the other aspect by which the flag was set to the drive waveform signal information in 1st Example. It is explanatory drawing which showed a part of capacitive load drive circuit of the modification of 1st Example. It is explanatory drawing which showed operation | movement of the capacitive load drive circuit of 2nd Example. It is explanatory drawing which showed operation | movement of the capacitive load drive circuit of the modification of 2nd Example. It is a flowchart of the process which the capacitive load drive circuit of the modification of 2nd Example performs in order to switch carrier frequency. It is explanatory drawing about the capacitive load drive circuit of 3rd Example. It is explanatory drawing which showed the circuit structure of the capacitive load drive circuit of 3rd Example. It is explanatory drawing which illustrated the aspect in which the capacitive load drive circuit of 3rd Example acquires load information. It is explanatory drawing which illustrated the other aspect from which the capacitive load drive circuit of 3rd Example acquires load information. 10 is an explanatory diagram of a capacitive load drive circuit according to Modification 1. FIG. 10 is an explanatory diagram of a capacitive load drive circuit according to Modification 2. FIG.

Hereinafter, in order to clarify the contents of the present invention described above, examples will be described in the following order.
A. First embodiment:
A-1. Device configuration:
A-2. Circuit configuration of capacitive load drive circuit:
A-3. Mechanism of power loss in digital power amplifier:
A-4. Mechanisms to avoid power loss in digital power amplifiers:
A-5. How to avoid an increase in power loss in the first embodiment:
A-6. Modification of the first embodiment:
B. Second embodiment:
B-1. How to avoid an increase in power loss in the second embodiment:
B-2. Modification of the second embodiment:
C. Third embodiment:
D. Modification 1:
E. Modification 2:

A. First Example:
A-1. Device configuration :
FIG. 1 is an explanatory diagram showing a configuration of a fluid ejecting apparatus 100 equipped with a capacitive load driving circuit 200 of the first embodiment. As shown in the drawing, the fluid ejection device 100 is roughly divided into:
A pulsation generating unit 110 for ejecting liquid, a fluid supply unit 120 for supplying fluid toward the pulsation generation unit 110, a control unit 130 for controlling operations of the pulsation generation unit 110 and the fluid supply unit 120, and the like. ing. The fluid ejecting apparatus 100 is an example of a water jet knife as a surgical tool used for excising or incising a living tissue by ejecting a pulsed liquid from a pulsation generating unit 110.

The pulsation generating unit 110 is provided on the second case 113 made of metal and the first case 114 made of metal.
A circular pipe-shaped fluid ejection pipe 112 is erected on the front surface of the second case 113, and a nozzle 111 is inserted at the tip of the fluid ejection pipe 112. Second case 11
3 and the first case 114 are formed with a thin disk-shaped fluid chamber 115, and the fluid chamber 115 is connected to the nozzle 111 via the fluid ejection pipe 112. A laminated piezoelectric element 116 is provided inside the first case 114. Pulsation generator 11
0 and the control unit 130 are connected by a wiring cable 150, and a drive signal is transmitted from the capacitive load driving circuit 200 in the control unit 130 via the wiring cable 150 to the piezoelectric element 116.
To be supplied. Further, the wiring cable 150 is attached to the pulsation generator 110 by a connector. For this reason, the distribution cable 150 can be replaced with various distribution cables 150 having different lengths and characteristics. The piezoelectric element 116 corresponds to the “capacitive load” in the present invention.

The fluid supply means 120 sucks up the liquid from the fluid container 123 containing the liquid to be ejected (water, physiological saline, chemical liquid, etc.) through the first connection tube 121, and then moves the second connection tube 122 through. And supplied to the fluid chamber 115 of the pulsation generator 110. For this reason, the fluid chamber 115 is in a state filled with the liquid.

When a drive signal is applied from the control unit 130 to the piezoelectric element 116, the piezoelectric element 116 expands and the fluid chamber 115 is compressed, and as a result, the liquid filled in the fluid chamber 115 is pulsed from the nozzle 111. Is injected into the shape. The expansion amount of the piezoelectric element 116 depends on the voltage applied as the drive signal. Therefore, in order to eject a pulsed liquid with desired characteristics,
It is necessary to apply an accurate drive signal to the piezoelectric element 116. Therefore, in order to generate such a drive signal, the control unit 130 includes a capacitive load drive circuit 2 as described below.
00 is installed.

A-2. Capacitive load drive circuit configuration:
FIG. 2 is an explanatory diagram showing a circuit configuration of the capacitive load driving circuit 200 mounted on the control unit 130. As shown in the figure, the capacitive load drive circuit 200 includes a drive waveform signal generation circuit 210 that outputs a drive waveform signal (hereinafter referred to as WCOM) serving as a reference for the drive signal, and the WCOM received from the drive waveform signal generation circuit 210. An arithmetic circuit 220 that outputs an error signal (hereinafter referred to as dWCOM) based on a feedback signal (hereinafter referred to as dCOM), which will be described later, and a modulation that performs pulse modulation on the dWCOM from the arithmetic circuit 220 and converts it into a modulated signal (hereinafter referred to as MCOM). Circuit 230;
The MCOM from the modulation circuit 230 is digitally power amplified to obtain a power amplified modulation signal (hereinafter referred to as A).
COM) and a digital power amplifier 240 to ACO
After receiving M and removing the modulation component, the pulsation generator 1 as a drive signal (hereinafter referred to as COM)
A smoothing filter 250 to be supplied to the ten piezoelectric elements 116, and a phase lead compensation circuit 260 that generates dCOM (feedback signal) by adding compensation (phase lead compensation) that advances the phase to COM output from the smoothing filter 250. And carrier frequency changing means 270 for changing the carrier frequency when the modulation circuit 230 performs pulse modulation. In the capacitive load driving circuit 200 of the first embodiment, dCOM obtained by adding phase advance compensation to COM is negatively fed back. However, a configuration in which negative feedback is not provided is also possible. In this case, the arithmetic circuit 220
In addition, the phase lead compensation circuit 260 becomes unnecessary. As a result, the modulation circuit 230 performs pulse modulation on WCOM, not dWCOM.

Of these, the drive waveform signal generation circuit 210 includes a waveform memory that stores WCOM data (drive waveform signal information to be described later) and a D / A converter, and D / A converts the data read from the waveform memory. A WCOM (drive waveform signal) is generated by converting the signal into an analog signal. The arithmetic circuit 220 outputs a signal obtained by subtracting dCOM from the WCOM thus output as dWCOM (error signal). Not only the analog signal but also the drive waveform signal generation circuit 210 reads WCOM (drive waveform signal) as digital data from the waveform memory storing the WCOM data, and converts dCOM into digital data by the A / D converter. The signal processing circuit may be used to generate dWCOM (error signal) as digital data by subtracting dCOM from WCOM by digital operation in the arithmetic circuit 220. In that case, the modulation circuit 230 is configured by a digital circuit using a signal processing circuit, and dWC
OM is handled as digital data.

The modulation circuit 230 generates (pulse modulation) a pulse wave-like MCOM (modulation signal) by comparing dWCOM with a triangular wave having a constant period (modulation period). Here, the base frequency (carrier frequency) of the triangular wave used for pulse modulation can be changed by the carrier frequency changing means 270 based on information from the drive waveform signal generating circuit 210.

The MCOM obtained by the modulation circuit 230 is input to the digital power amplifier 240. The digital power amplifier 240 includes two switch elements (MOS) connected in a push-pull manner.
FET, etc.), a power source, and a gate driver for driving these switch elements. When the output of MCOM is ON, the high-side switch element is turned ON, the low-side switch element is turned OFF, and the power supply voltage Vdd is output as ACOM. MC
When the output of OM is OFF, the high-side switch element is turned OFF, the low-side switch element is turned ON, and the ground voltage is output as ACOM. As a result, the modulation circuit 2
The MCOM that changes in a pulse waveform between the operating voltage of 30 and the ground is the voltage Vdd of the power supply.
The power is amplified to ACOM that changes in a pulse waveform between the ground and the ground. In this amplification, since only the ON / OFF of the two switch elements connected in a push-pull manner is switched, it is possible to suppress power loss as compared with the case of amplifying an analog waveform.

The power-amplified ACOM (power amplification modulation signal) is converted into COM (drive signal) by passing through a smoothing filter 250 constituted by an LC circuit, and the piezoelectric element 1
16 is applied. Further, COM is negatively fed back to the arithmetic circuit 220, but the smoothing filter 2
By passing 50, COM is out of phase with WCOM. So C
Rather than simply negatively feeding back OM, compensation (phase lead compensation) is performed to advance the phase through a phase lead compensation circuit 260 constituted by a capacitor and a resistor, and the obtained signal is negatively input to the arithmetic circuit 220 as dCOM. It is supposed to return.

A-3. Mechanism of power loss in digital power amplifier:
As described above, the digital power amplifier 240 can generate the ACOM by power-amplifying the modulation signal (MCOM) without a large power loss. However, even in the digital power amplifier 240, if a certain condition is satisfied, a large power loss may occur during power amplification.

FIG. 3 is an explanatory diagram showing how power loss occurs in the digital power amplifier 240.
As shown in the figure, for example, when a constant voltage is output to the load, the power loss increases abruptly when the duty ratio of the modulation signal becomes smaller than a certain value. Even when the duty ratio of the modulation signal is large, if the value exceeds a certain value, the power loss increases rapidly. If such a phenomenon occurs, the effect of amplifying the WCOM after it is modulated and converted to MCOM is lost, so a countermeasure is required. To that end, the mechanism by which this phenomenon occurs must be clarified.

FIG. 4 is a circuit diagram showing the internal configuration of the digital power amplifier 240. As illustrated, the digital power amplifier 240 includes two MOSFETs that are push-pull connected, a power supply Vdd, and a gate driver that drives these MOSFETs. Each MOSFET has a parasitic capacitance between the drain terminal, the gate terminal, and the source terminal. In the figure, Cds represents a parasitic capacitance generated between the drain terminal and the source terminal, Cgd represents a parasitic capacitance generated between the drain terminal and the gate terminal, and Cgs represents between the gate terminal and the source terminal. Parasitic capacitance is shown. Here, Cds is actually MOSFE.
This is the junction capacitance of the parasitic diode of T. For convenience, in this embodiment, the parasitic diode and Cds
And are shown separately. The inventors of the present application have found that when a constant voltage (or almost constant voltage) is output to the load, for example, power loss occurs due to these parasitic capacitances.

FIG. 5 is an explanatory diagram showing the operation of the digital power amplifier 240 for power amplification. In the digital power amplifier 240, two MOSFETs are push-pull connected,
In FIG. 5, these MOSFETs are simplified by switches. Each MOSFET has three types of parasitic capacitances as shown in FIG. 4. In FIG. 5, these parasitic capacitances are collectively displayed as one. In the following description, of the two MOSFETs that are push-pull connected, the high-side MOSFET is referred to as “MOSFET (H)”, and the low-side MOSFET is referred to as “MOSFET (L)”. FIG. 5 (a)
FIG. 5D corresponds to a state in which the MOSFET (H) is turned on and the MOSFET (L) is turned off. At the time of power amplification, these two states are switched alternately. Also, MOSFET (H) is OFF and M
The state in which the OSFET (L) is ON is simply referred to as “the output state is the L state”.
When ET (H) is ON and MOSFET (L) is OFF, simply “Output state is H”
Shall be referred to as

When both MOSFETs are turned on, a large inrush current flows from the power supply Vdd to the ground, thereby damaging the element. Therefore, to avoid this, 2
When switching between the two states, both MOSFET (H) and MOSFET (L) are O
Switching is performed via a period of FF (dead time period). FIG.
) Shows the state of the dead time period when the output state switches from the L state to the H state, and FIG. 5E shows the state when the output state switches from the H state to the L state. The state of the dead time period is shown.

Here, paying attention to the state shown in FIG. 5A (the output state is L state), in this state, one terminal of the parasitic capacitance of the MOSFET (H) is connected to the voltage Vdd, and the other terminal is Connected to ground. Therefore, charge is accumulated (charged) in the parasitic capacitance of the MOSFET (H).
Is done. In addition, as for the parasitic capacitance of the MOSFET (L), no charge is accumulated because any terminal is connected to the ground. When the dead time period is reached from this state, the MOSFET (L) is turned off as shown in FIG.

When the dead time period elapses, the MOSFET (H) is turned on this time. Here, a terminal from which an ACOM (power amplification modulation signal) is output is Vs. MOSFET (H)
When the MOSFET (H) is turned on, the terminal on the side connected to the power supply Vdd of the parasitic capacity of the MOSFET (H) and the terminal connected to Vs are short-circuited. The charge of the parasitic capacitance of the MOSFET (H) stored in the state of FIG. 5A flows as a current as indicated by the dashed line arrow in FIG. Also, MOSFET (
Focusing on the parasitic capacitance of L), at the moment when the MOSFET (H) is turned on, the MOSFET (
The terminal on the side connected to Vs of the parasitic capacitance L) is at the voltage Vdd, and the terminal on the side connected to the ground is kept at the ground potential, so that the broken line in FIG. A current as shown by an arrow flows, and the parasitic capacitance of the MOSFET (L) is charged. However, FIG.
The dashed-dotted line and broken line currents indicated by> cause resistance loss in the MOSFET (H).

When the parasitic capacitance of the MOSFET (L) is charged in this way, finally, FIG.
(The output state is H). In this state, the terminal connected to the parasitic capacitance Vs of the MOSFET (L) is connected to the power supply Vdd, and the terminal on the opposite side is connected to the ground, so that charges are accumulated (charged). In addition, since the terminals of the parasitic capacitance of the MOSFET (H) are all connected to the power supply Vdd, no charge is accumulated.

In the above, the case where the state of FIG. 5A (the output state is L state) is switched to the state of FIG. 5D (the output state is H state) has been described. A case will be described in which the state d) (the output state is H) is switched to the state shown in FIG. 5A (the output state is L). When the dead time period is reached from the state of FIG. 5D, the MOSFET (H) is turned off as shown in FIG. In this state, the parasitic capacitance of the MOSFET (L) is charged to the voltage Vdd. When the dead time period elapses, MOSFET (
L) is turned ON. Then, the terminal connected to the parasitic capacitance Vs of the MOSFET (L) and the terminal connected to the ground are short-circuited, and the MOSFET (L) stored in the state of FIG. ) Of the parasitic capacitance flows as a current as indicated by a dashed line arrow in FIG.

Further, the terminal connected to the power source Vdd of the parasitic capacitance of the MOSFET (H) is the power source V
Since the terminal on the side connected to dd and connected to Vs is connected to the ground, FIG.
) Flows as indicated by the broken arrow, and the parasitic capacitance of the MOSFET (H) is charged.
However, the dashed-dotted line and broken line current shown in FIG. 5 (f) cause resistance loss in the MOSFET (L). Therefore, when the parasitic capacitance of the MOSFET (H) is charged in this manner, the state finally shown in FIG.

The above description has been made assuming that the smoothing filter 250 is not connected to the digital power amplifier 240. However, since the smoothing filter 250 is connected to the digital power amplifier 240 as shown in FIG. 2, it is necessary to consider the influence of this.

FIG. 6 shows a current flowing through a coil of a general smoothing filter when a voltage that switches between a voltage E and a voltage 0 at a constant period T is applied to a general smoothing filter composed of a coil and a capacitor. ing. Since the output of the digital power amplifier 240 of the first embodiment repeats the voltage Vdd and the ground, it can be applied to the smoothing filter 250 of the present embodiment by replacing the voltage E in FIG. 6 with the voltage Vdd.

If the time the application of the voltage E (corresponding to the voltage Vdd) in a constant period T and t _on,
The duty ratio D _is (in the case of percentage _{100 × t on / T) t} on / T becomes. This state corresponds to the case where the voltage Vout (= D × E) is output from the smoothing filter 250. At this time, during the period in which the voltage E is applied to the coil, the current increases almost linearly from minus (in a state of flowing backward to the power supply side) to plus (in a state of flowing toward the ground). In a period in which the applied voltage is zero, a sawtooth current that flows almost linearly from plus and turns to minus flows. In addition, since the voltage output from the smoothing filter 250 is maintained at the voltage Vout (= D × E), the charges entering and exiting the capacitor during one cycle are equal, so the maximum amplitude to the plus side The value and the maximum value of the amplitude to the minus side are equal.

FIG. 7 shows a calculation formula for the current I flowing through the coil of the smoothing filter 250. FIG. 7A shows a period in which the voltage E (corresponding to the voltage Vdd) is applied, and FIG. 7B shows a period in which the applied voltage is dropped to the ground. is there. A current I flowing through the coil during the period of applying the voltage E is shown in a circuit diagram in FIG. The inductance of the coil constituting the smoothing filter 250 is L, the capacitance of the capacitor is C, the initial current flowing through the coil (current that flows when the voltage E is applied) is I ₀ , and the initial voltage of the capacitor (the capacitor when the voltage E is applied) If the voltage between terminals of E) is E ₀ , the differential equation shown in the equation (1) is established between the voltage E and the current I. When this equation is solved, the current I is obtained by the equation (2). It is done. Here, ω ₀ is the resonance frequency (= 1 / √ (LC)) of the smoothing filter 250. And, since the time _{t on} the voltage E is applied sufficiently short compared to the resonance period of the low pass filter 250, cos .omega ₀ t can is considered almost 1, sin .omega ₀ t be regarded as substantially omega ₀ t Can do. Then, equation (2) becomes (
It can be approximated by equation (3), and it can be seen that the current I increases linearly with the passage of time t.

The same applies to the period during which the voltage applied to the smoothing filter 250 is dropped to the ground. That is, the current I flowing through the coil during the period when the applied voltage is dropped to the ground.
Can be shown by the circuit diagram in FIG. 7B, and the applied voltage is 0, so the current I is (
The differential equation shown in equation 4) holds. When this equation is solved, the current I flowing during the period in which the applied voltage is ground is obtained by the equation (5). In addition, the sinω ₀ t ω ₀ t
Assuming that cosω ₀ t is 1, the current I can be approximated by equation (6).
Therefore, it can be seen that the current I decreases linearly with the passage of time t during the period in which the applied voltage is dropped to the ground.

Further, as shown in FIG. 6, at the instant (t = 0) when the voltage E is applied, the current I = −IA, so that I ₀ = −IA in the equation (3). The initial voltage E ₀ is equal to the voltage Vo in FIG.
It is equal to ut (= D × E). Further, at a time t = t _on immediately before switching from a period in which the voltage E is applied to a period in which the voltage is dropped to the ground, I (t _on ) =
IA. When these are substituted into the equation (3) and arranged, the amplitude IA of the current flowing through the coil is represented by the equation (7) shown in FIG. However, the reciprocal of the period T shown in FIG.
fc (carrier frequency) is used, and t _on = D / fc is substituted for t in equation (3). As shown in the equation (7), the magnitude IA of the current amplitude is a quadratic function of the duty ratio D, and is shown in FIG.
As shown in b), the maximum value is obtained when D = 0.5 (duty ratio D is 50%).

From the above, the following can be understood. When the output of the digital power amplifier 240 is smoothed by the smoothing filter 250 and a constant voltage is applied to the load (when the duty ratio is constant), the coil of the smoothing filter 250 has a saw blade shape as shown in FIG. Current flows. The current amplitude is maximized on the plus side at the moment when the output of the digital power amplifier 240 falls to the ground (the moment when the output state is switched from H to L), and is maximized on the minus side. This is the moment when the output of the digital power amplifier 240 rises from the ground (the moment when the output state switches from L to H). The absolute value | IA | of the current is maximized when the duty ratio D is 50%, and decreases as the duty ratio D decreases from 50% or increases from 50%.

When the smoothing filter 250 is connected to the digital power amplifier 240, the smoothing filter 25
The operation of the digital power amplifier 240 in a state where the smoothing filter 250 is connected will be described based on the fact that the current I flowing through the zero coil behaves in this manner.

FIG. 9 shows the state shown in FIG. 5A from the state where the output of the digital power amplifier 240 is L. FIG.
It is explanatory drawing which showed the phenomenon which generate | occur | produces during the dead time period at the time of switching to the state of (d) (output is a H state). As shown in FIG. 9A, in the state where the output of the digital power amplifier 240 is L (the MOSFET (H) is OFF and the MOSFET (L) is ON), M
Charges are stored in the parasitic capacitance of the OSFET (H). Further, as described above with reference to FIG. 6, immediately before the output of the digital power amplifier 240 switches from the L state to the H state, a current having a magnitude IA from the coil of the smoothing filter 250 toward the digital power amplifier 240 is generated. Flowing. In FIG. 9A, a state in which a current from the coil flows is represented by a dashed arrow.

In order to switch the output state of the digital power amplifier 240 from this state, both MOSFETs are turned off during the dead time period. Then, smoothing filter 2
In the 50 coils, an electromotive force is generated in a direction in which a current continues to flow due to a self-induction phenomenon. The broken-line arrows shown in FIG. 9B represent the current that flows due to the electromotive force described above. Since MOSFET (L) is switched off, it cannot flow here. On the other hand, since no electric charge is stored in the parasitic capacitance of the MOSFET (L), a current flows through the parasitic capacitance due to the counter electromotive force of the coil and is charged. M
As for the parasitic capacitance of the OSFET (H), the back electromotive force of the coil is generated, and as a result, the terminal voltage on the side connected to Vs of the parasitic capacitance rises. The voltage between the terminals decreases, and current flows. As a result, the charge stored in the parasitic capacitance of the MOSFET (H) is regenerated to the power supply Vdd.

Then, as shown in FIG. 9C, all charges stored in the parasitic capacitance of the MOSFET (H) are regenerated, and the terminal voltage on the side connected to Vs of the parasitic capacitance of the MOSFET (L) is a voltage. After charge is stored in the parasitic capacitance until Vdd is reached, the MOSFET (H) is turned on. In this way, as described above with reference to FIG. 5, when the output of the digital power amplifier 240 is switched from the L state to the H state, the discharge of the charge remaining in the parasitic capacitance of the MOSFET (H) and the MOSFET (L) There is no power loss due to charging of the parasitic capacitance. That is, if the state of FIG. 9A can be brought to the state of FIG. 9C during the dead time period, the occurrence of power loss can be suppressed. The same applies when switching the output of the digital power amplifier 240 from H to L state.

FIG. 10 is generated during a dead time period when the state of FIG. 5D (the output of the digital power amplifier 240 is H) is switched to the state of FIG. 5A (the output is L). It is explanatory drawing which showed the phenomenon to do. As shown in FIG. 10A, when the output of the digital power amplifier 240 is in the H state (MOSFET (H) is ON and MOSFET (L) is OFF), the parasitic capacitance of the MOSFET (L) is charged. Is stored. Further, as described above with reference to FIG. 6, immediately before the output of the digital power amplifier 240 switches from the H state to the L state, a current having a magnitude IA from the digital power amplifier 240 toward the coil of the smoothing filter 250. Is flowing. In FIG. 10A, a state in which a current flows from the power source Vdd of the digital power amplifier 240 toward the coil is represented by a dashed arrow.

From this state, in order to switch the output state of the digital power amplifier 240 from H to L,
In the dead time period, the two MOSFETs are both turned off. Then, an electromotive force is generated in a direction in which a current is continuously applied to the coil of the smoothing filter 250 due to a self-induction phenomenon. The broken-line arrows shown in FIG. 10B represent the current that flows due to the electromotive force described above. Since the MOSFET (H) is switched off, the power supply V
The current from dd cannot flow here. On the other hand, since no charge is stored in the parasitic capacitance of the MOSFET (H), a current flows through the parasitic capacitance due to the counter electromotive force of the coil and is charged. As for the parasitic capacitance of the MOSFET (L), the voltage at the terminal connected to Vs of the parasitic capacitance decreases as a result of the back electromotive force of the coil, so the terminal connected to the ground. The voltage between the terminals becomes smaller and current flows. As a result, the charge stored in the parasitic capacitance of the MOSFET (L) is regenerated in the capacitor of the smoothing filter 250.

Then, as shown in FIG. 10C, all the charges stored in the parasitic capacitance of the MOSFET (L) are regenerated, and the charges are stored in the parasitic capacitance until the voltage between the terminals of the MOSFET (H) reaches the voltage Vdd. After that, the MOSFET (L) is turned on. In this way, when the output of the digital power amplifier 240 is switched from H to L as described above with reference to FIG.
There is no power loss due to the discharge of the charge remaining in the parasitic capacitance of the SFET (L) and the charging of the parasitic capacitance of the MOSFET (H). That is, if the state of FIG. 10A can be brought to the state of FIG. 10C during the dead time period, the occurrence of power loss can be suppressed.

Thus, if a large back electromotive force can be generated by the coil of the smoothing filter 250 when the output state of the digital power amplifier 240 is switched, the digital power amplifier 2
Therefore, it is possible to greatly suppress the power loss generated at 40. However, as shown in FIG. 8 (a), when the duty ratio is small or large, the value of the current flowing through the coil is small, and the coil cannot generate a sufficiently large back electromotive force. , FIG.
It is considered that a large power loss as shown in Fig. 1 occurred.

A-4. Mechanism to avoid power loss in digital power amplifier:
FIG. 11 shows the operation of the digital power amplifier 240 when the coil can generate a sufficiently large counter electromotive force and when the coil cannot generate a sufficiently large counter electromotive force. The state of switching is shown. FIG. 11A shows a case where a sufficiently large back electromotive force is generated, FIG. 11B shows a case where a back electromotive force having a sufficient amount is not generated, and FIG. The case where the magnitude | size of electromotive force is insufficient is shown.

First, the case of FIG. 11B, which is the simplest case, will be described. Immediately before the output state of the digital power amplifier 240 switches from the L state to the dead time period, the coil current I flows in the negative direction (in the reverse direction) as shown in FIG. Also,
The output voltage of the digital power amplifier 240 is zero. This state is referred to as state [A]. Subsequently, when the MOSFET (L) is switched to OFF and shifted to the dead time period, as described above with reference to FIG. 9B, the charge of the parasitic capacitance of the MOSFET (L) is charged by the counter electromotive force of the coil. When the charge is regenerated in the parasitic capacitance of the MOSFET (H), the output voltage of the digital power amplifier 240 rises accordingly, and the voltage Vdd is just reached when the dead time period ends. A state in which the output voltage of the digital power amplifier 240 is increased by the back electromotive force of the coil is referred to as a state [B].

When the dead time period ends and the output state of the digital power amplifier 240 is in the H state, as described above with reference to FIG. ) Is flowing, but the direction of the current is reversed in the middle, and the current flows in the plus direction (the direction from the digital power amplifier 240 toward the coil). A state where the output voltage of the digital power amplifier 240 is the voltage Vdd and a negative current flows in the coil is referred to as a state [C], and a positive current flows when the coil current is reversed. Will be referred to as state [D].

After that, when the output state of the digital power amplifier 240 is switched from the H state to the MOSFET (H) being turned OFF to shift to the dead time period, as described above with reference to FIG. The charge of the parasitic capacitance of the MOSFET (L) is regenerated, and the MOS
Charge is charged in the parasitic capacitance of the FET (H), and the output voltage of the digital power amplifier 240 is lowered accordingly. When the dead time period ends, the voltage drops to zero.
A state in which the output voltage of the digital power amplifier 240 is lowered by the counter electromotive force of the coil,
It will be referred to as state [E].

When the dead time period ends and the output state of the digital power amplifier 240 becomes the L state, as described above with reference to FIG. The direction of the current is reversed, and the current flows in the negative direction. A state where the output voltage of the digital power amplifier 240 is 0 and a positive current flows through the coil.
It will be referred to as state [F]. In addition, the state where a negative current flows through the coil
It is the state [A] described above.

As described above, the state in which the operation of the digital power amplifier 240 is switched when the counter electromotive force having a magnitude that is not excessive or insufficient is generated in the coil when the dead time period is entered. On the other hand, when a sufficiently large back electromotive force is generated in the coil, the operation of the digital power amplifier 240 is switched as shown in FIG.

First, when the output state of the digital power amplifier 240 is in the L state, the state [A] is described above. When switching to the dead time period, the state [B], that is, the MOSFET ( The parasitic capacitance of L) is charged, and the charge of the parasitic capacitance of the MOSFET (H) is regenerated, so that the output voltage of the digital power amplifier 240 increases.
If a sufficiently large back electromotive force is generated in the coil, the parasitic capacitance of the MOSFET (H) is charged and the parasitic capacitance of the MOSFET (H) is charged before the dead time period ends. The charge regeneration is completed (ie, the output voltage of the digital power amplifier 240 reaches Vdd), and thereafter, the charge passes through the parasitic diode of the MOSFET (H), and the charge is supplied to the power supply Vdd.
It will be in the state of flowing backward. Such a state is referred to as a state [G]. In the state [G], the output voltage of the digital power amplifier 240 becomes higher than the voltage Vdd by the voltage drop of the parasitic diode of the MOSFET (H).

Thereafter, when the output state of the digital power amplifier 240 is H, the state [C] (
From the state in which the output voltage is Vdd and the coil current is negative), the state [D] (
The output voltage is Vdd and the coil current is positive. When the dead time period is reached, the state [E] described above (the MOSFET (L
) Is regenerated, and the parasitic capacitance of the MOSFET (H) is charged to reduce the output voltage. In this case, too, when a back electromotive force having a sufficient magnitude is generated in the coil, before the dead time period ends, charge regeneration from the parasitic capacitance of the MOSFET (L), and the MOSFET The charging of the parasitic capacitance of (H) is completed (that is, the output voltage of the digital power amplifier 240 is reduced to 0), and thereafter, the MOSFET
The charge is absorbed from the ground side via the parasitic diode (L). Such a state is referred to as a state [H]. In the state [H], the output voltage of the digital power amplifier 240 is
The voltage is lower than 0 by the voltage drop of the parasitic diode of the MOSFET (L).

On the other hand, when the back electromotive force generated in the coil is insufficient, the operation of the digital power amplifier 240 is switched as shown in FIG. The operation from when the output state of the digital power amplifier 240 is switched from the L state to the dead time period until the dead time period ends is the same as the operation described above with reference to FIG. 11A or FIG. It is.
That is, the state [A] is switched to the state [B].

However, if the magnitude of the counter electromotive force generated in the coil is insufficient, the output voltage of the digital power amplifier 240 does not reach Vdd even when the dead time period (state [B]) ends, and the MOSFET Charging the parasitic capacitance (L) is not completed. Further, the regeneration of charge from the parasitic capacitance of the MOSFET (H) is not completed. In this state, after the dead time period ends and the output state of the digital power amplifier 240 switches to the H state, a current flows through the MOSFET (H), charging the parasitic capacitance of the MOSFET (L), and The output voltage rises to the voltage Vdd until the discharge of the charge remaining in the parasitic capacitance of the MOSFET (H) is completed. Such a state is referred to as a state [I]. During the period of the state [I], power loss due to resistance occurs in the MOSFET (H) as in the case of switching from the state of FIG. 5A to the state of FIG. 5D.

If the back electromotive force generated in the coil is insufficient, the digital power amplifier 24
A similar phenomenon occurs when the output state of 0 is switched from H to L, that is, when the state [D] is switched to the state [E]. In this case, even when the dead time period (state [E]) ends, the output voltage of the digital power amplifier 240 does not drop to 0, and the MOSFET (L)
Regeneration of charge from the parasitic capacitance of the battery is not completed Similarly, charging of the parasitic capacitance of the MOSFET (H) is not completed. In this state, the dead time period ends, and after the output state of the digital power amplifier 240 is switched to the L state, a current flows through the MOSFET (L), and the MOS
The output voltage decreases to 0 until the charging of the parasitic capacitance of the FET (H) and the discharging of the charge remaining in the parasitic capacitance of the MOSFET (L) are completed. Such a state is referred to as a state [J]. During the period of the state [J], a power loss due to resistance occurs in the MOSFET (L) as in the case of switching from the state of FIG. 5D to the state of FIG.

As described above, power loss occurs when the digital power amplifier 240 enters the state [I] or the state [J]. And these states indicate the carrier frequency fc of pulse modulation.
As a result, a very large power loss is generated. Therefore, in order to avoid such a power loss in the digital power amplifier 240, it is only necessary to prevent the state [I] and the state [J] from occurring. Therefore, conditions for preventing these states from occurring will be examined.

FIG. 12A is a diagram for explaining conditions under which the state [I] and the state [J] do not occur.
State [I] is digital power amplifier 2 when the dead time period in state [B] has elapsed.
This occurs when the output voltage of 40 has not reached the voltage Vdd. In other words, the condition for preventing the state [I] from occurring is that the output voltage of the digital power amplifier 240 rises from the voltage 0 to the voltage Vdd or more within the dead time period. Here, the capacitances of the parasitic capacitances of the MOSFET (H) and the MOSFET (L) are expressed as Coss (H) and Cos, respectively.
Assuming that ss (L), the increase in the output voltage V in the state [B] is shown in FIG.
) Expression. However, Coss is an output capacity, and generally Coss = Cds + Cgd
It is represented by In addition, when the ratio of the capacitance of Coss is dominant by Cds, it may be considered that Coss≈Cds. Note that IA in the equation (8) is the magnitude of the current flowing in the coil at the moment of switching to the dead time period. Therefore, if the dead time period when the output state of the digital power amplifier 240 is switched from L to H is Td1, the condition for preventing the state [I] from being generated is the expression (10) in FIG. The indicated conditions will be satisfied.

Similarly, state [J] occurs when the output voltage of digital power amplifier 240 has not dropped from voltage Vdd to voltage 0 when the dead time period in state [E] has elapsed.
The decrease in the output voltage V in the state [E] is displayed by the equation (9) shown in FIG. Therefore, if the dead time period when the output state of the digital power amplifier 240 switches from H to L is Td2, the condition for preventing the state [J] from occurring is (11) in FIG.
The condition expressed by the equation is satisfied.

Here, in the equations (10) and (11), Coss (H) and Coss (L) are M
Since it is a value determined by the specification of OSFET, it is difficult to change. Also, Td1 and Td2 need to be designed in as short a time as possible in order to perform high-speed switching. If the minimum time width of the output pulse of the digital power amplifier 240 is determined, It cannot be designed and is difficult to change. Further, as shown by the equation (7) in FIG. 8A, the equation IA includes the voltage E,
That is, since Vdd is included, the conditions shown in the equations (10) and (11) cannot be satisfied by changing Vdd. On the other hand, IA can be changed by the carrier frequency fc at the time of pulse modulation, as shown by the equation (7). By the way, (7)
In the equation, L is the inductance of the coil of the smoothing filter 250, and the smoothing filter 2
This value cannot be changed significantly if 50 required properties are to be secured. Further, since the duty ratio D corresponds to the voltage value to be output from the smoothing filter 250, this value cannot be changed.

Therefore, in order to satisfy the expressions (10) and (11), the only parameter that can be changed relatively easily is the carrier frequency fc. In other words, if the carrier frequency fc at the time of pulse modulation is changed so as to satisfy the expressions (10) and (11), even if the duty ratio becomes a value near the upper limit value or near the lower limit value, Power amplifier 240
It is possible not to increase the power loss at the time. Based on such a principle, the capacitive load driving circuit 200 of the first embodiment changes the carrier frequency fc during pulse modulation so that the power loss in the digital power amplifier 240 does not increase. Hereinafter, a method for avoiding an increase in power loss when the load is driven at a constant voltage near the upper limit or near the lower limit of the duty ratio in the capacitive load driving circuit 200 of the first embodiment will be specifically described.

A-5. How to avoid an increase in power loss in the first embodiment:
FIG. 13 is an explanatory diagram showing a method for avoiding an increase in power loss in the digital power amplifier 240 in the capacitive load driving circuit 200 of the first embodiment. As described above with reference to FIG. 2, the drive waveform signal generation circuit 210 of the first embodiment outputs WCOM (drive waveform signal) that is the source of COM (drive signal), and information (drive waveform) for that purpose. Signal information) is stored in the built-in waveform memory.

FIG. 13B is an explanatory diagram showing drive waveform signal information stored in the drive waveform signal generation circuit 210 of the first embodiment. As shown in the figure, the drive waveform signal information includes an elapsed time from the start of WCOM output, a voltage output at that time, and a flag set value (hereinafter referred to as f).
stored as “lag”). If the amplitude of the triangular wave used in the modulation circuit 230 is determined, the WCOM voltage value and the duty ratio D have a one-to-one relationship.

FIG. 14 is an explanatory diagram illustrating drive waveform signal information stored in the drive waveform signal generation circuit 210. The shaded area in the figure indicates that the WCOM voltage (and hence the duty ratio D) is near the upper limit (in the example shown, the duty ratio D is 80% or more), or near the lower limit (in the example shown, the duty ratio D). Is a region that takes a value of 20% or less. If the slope of WCOM is 0 (or very small) in these areas, the flag is “1”.
", Otherwise flag is set to" 0 ". Such fl
The process for setting ag will be described later.

As shown in FIG. 13A, the drive waveform signal generation circuit 210 of the first embodiment reads the drive waveform signal information stored in the waveform memory, outputs WCOM to the arithmetic circuit 220, and sets the flag as the carrier. Output to the frequency changing means 270. Also, the carrier frequency changing means 270 stores the correspondence between the flag and the carrier frequency fc as shown in FIG. Then, the carrier frequency fc corresponding to the flag received from the drive waveform signal generation circuit 210 is selected and set in the modulation circuit 230. By doing this,
When the load is driven by a phenomenon as shown in FIG. 3, that is, a constant voltage (or a voltage close to a constant) near the upper limit or the lower limit of the duty ratio, the digital power amplifier 240 is driven.
It is possible to avoid a phenomenon in which the power loss at the terminal increases rapidly.

FIG. 15 is an explanatory diagram showing the reason why an increase in power loss can be avoided in the digital power amplifier 240 of the first embodiment. In the following, it is assumed that the load is driven at a constant voltage (and therefore a constant duty ratio) unless otherwise specified. Assuming that the carrier frequency is fixed to fc0 regardless of the duty ratio, the amplitude IA of the current flowing through the coil of the smoothing filter 250 is given by the equation (7) in FIG. 8, and the amplitude is increased as the duty ratio is further away from 50%. IA becomes smaller. As a result, the amplitude IA is equal to the expression (10) shown in FIG.
11), the phenomenon shown in FIG. 11C occurs, and the digital power amplifier 2
At 40, a large power loss is generated.

Therefore, an amplitude IA that satisfies the equal signs of the equations (10) and (11) in FIG. 12 or a larger amplitude with a little margin than this amplitude IA is set as the threshold amplitude Ith. When the duty ratio is such that the amplitude IA given by the equation (7) in FIG. 8 is equal to or smaller than the threshold amplitude Ith, the carrier frequency is lowered from fc0 to fc1, as shown in FIG. In FIG. 15, when the duty ratio is 20% or less or the duty ratio is 80% or more, it is assumed to be lower than the threshold amplitude Ith. Also, the carrier frequency fc to be lowered
1 is the amplitude IA obtained by the expression (7) in FIG. 8 even with the lower limit duty ratio (here, duty ratio D = 5%) and the upper limit duty ratio (here, duty ratio D = 95%).
Is set to a frequency that does not fall below the threshold amplitude Ith (or equal to the amplitude Ith).

In this way, as indicated by a thick broken line in FIG. 15A, the amplitude IA of the current flowing through the coil of the smoothing filter 250 can be kept at or above the threshold amplitude Ith at all duty ratios. . As a result, the state [I] and the state [J] shown in FIG. 11C can be prevented from occurring, and therefore, as shown by a thick broken line in FIG. 15B, the lower limit of the duty ratio. It is possible to avoid a phenomenon in which power loss increases near (low duty) or near the upper limit (high duty).

Finally, a flag setting process for setting a flag for WCOM of the drive waveform signal information will be described. FIG. 16 is a flowchart showing processing for setting a flag of drive waveform signal information. When the flag setting process is started, first, X (X−1) + (2L · I
th / Vdd) · fc0 = 0 is calculated (step S100). Where L
Is the inductance of the coil of the smoothing filter 250, Ith is the threshold amplitude Ith of the current flowing through the coil, and Vdd is the voltage of the power supply of the digital power amplifier 240. Therefore, the obtained X indicates a duty ratio such that the amplitude IA of the current flowing through the coil of the smoothing filter 250 becomes the threshold amplitude Ith.

Subsequently, a period in which the gradient of the voltage value with respect to time is 0 (that is, the voltage value is constant) is extracted from WCOM. In addition, the number m of extracted locations is stored (step S102). And after setting the variable n to "1" (step S104), the duty ratio D of the nth location extracted is calculated (step S106). The duty ratio D can be calculated by dividing the voltage value indicated by WCOM by the triangular wave amplitude voltage used by the modulation circuit 230 during pulse modulation.

Then, whether or not the obtained duty ratio D is smaller than the previously calculated X,
Or it is judged whether it is larger than 1-X (step S108). X as mentioned above
Since the duty ratio is such that the amplitude IA of the current flowing through the coil of the smoothing filter 250 becomes the threshold amplitude Ith, the amplitude IA of the current flowing through the coil is eventually determined in step S108.
Therefore, it is determined whether or not the duty ratio D is smaller than the threshold amplitude Ith.

As a result, when the calculated duty ratio D is smaller than X or larger than 1-X (step S108: yes), it can be determined that it is necessary to switch the carrier frequency, so that period (nth) Is set to “1” (step S110). On the other hand, when the calculated duty ratio D is larger than X and smaller than 1-X (step S108: no), it can be determined that there is no need to switch the carrier frequency, so that period (n The flag of the (th extraction period) is set to “0” (step S112).

Thus, when flag is set for the nth extraction period, the extraction period is m
It is determined whether it is the second (step S114). As a result, if it is not the m-th extraction period (step S114: no), an extraction period for which no flag has been set still remains, so that “1” is added to n (step S118). ), The process after step S106 is performed for the new n. On the other hand, when the extraction period for which the flag is set is the mth extraction period (step S114: yes), the flag is set for all the extracted periods. Therefore, “0” is set in the flag of the period not extracted.
”Is set to“ 0 ”for all periods in which the flag is not set to“ 1 ”(step S116), the flag setting process in FIG.

If the flag is set in this way, the flag can be set appropriately for various WCOMs. For example, as shown in FIG. 17A, when there is a period in which the voltage gradient is 0 and the duty ratio is high in the middle of WCOM, the flag of this period is set to “
1 "can be set. Further, as shown in FIG. 17B, when the duty ratio takes an intermediate value even when a period in which the voltage gradient is 0 exists, the flag in this period remains “0”. Can be set. As described above, according to the flag setting process of FIG. 16, the carrier frequency can be switched by appropriately setting the flag of the drive waveform signal information. As a result, it is possible to suppress power loss in the digital power amplifier 240 even during a period when the duty is high.

A-6. Modification of the first embodiment:
In the first embodiment described above, the flag for switching the carrier frequency fc is:
The drive waveform signal generation circuit 210 has been described as being incorporated in advance in the drive waveform signal information storing WCOM. In this case, the carrier frequency changing unit 270 may change the carrier frequency fc in accordance with the flag output from the drive waveform signal generation circuit 210. However, as described above with reference to FIG. 16, since the flag can be set based on the voltage value of WCOM, the flag is generated inside the carrier frequency changing means 270, and the carrier frequency is generated based on the obtained flag. fc may be switched.

FIG. 18 shows that the carrier frequency changing means 270 of the modified example of the first embodiment
It is explanatory drawing which showed a mode that c was switched. The drive waveform signal information stored in the drive waveform signal generation circuit 210 of the modified example stores the time and the voltage value of WCOM.
ag is not stored. Then, the drive waveform signal generation circuit 210 outputs WCOM to the arithmetic circuit 220 and the carrier frequency changing unit 270. In the carrier frequency changing unit 270 according to the modified example, the flag generation circuit generates a flag based on the WCOM received from the drive waveform signal generation circuit 210. Then, based on the generated flag, the carrier frequency fc
To change. In this case, the digital power amplifier 240 is used regardless of the duty ratio.
It becomes possible to suppress the power loss at.

B. Second embodiment:
In the first embodiment described above, the carrier frequency fc is switched between two stages of the frequency fc0 and the frequency fc1. That is, when the amplitude of the current flowing through the coil of the smoothing filter 250 becomes smaller than the threshold amplitude Ith, the carrier frequency fc is changed from fc0 to f.
It was supposed to be pulled down to c1 at once. On the other hand, more types of carrier frequencies fc may be prepared and the carrier frequencies fc may be switched gradually. Hereinafter, such a second embodiment will be described. In the second embodiment, only the configuration different from the first embodiment will be described, and the description of the same configuration will be omitted.

B-1. How to avoid an increase in power loss in the second embodiment:
FIG. 19 is an explanatory diagram showing how to avoid an increase in power loss in the digital power amplifier 240 in the second embodiment. In the first embodiment described above, the duty ratio is used in the range of 5% to 95%, and when the duty ratio is 20% or less or 80% or more, the carrier frequency fc is lowered from fc0 to fc1. Here, the duty ratio of 20% or 80% is a duty ratio at which the amplitude IA of the current flowing through the coil of the smoothing filter 250 reaches the threshold amplitude Ith when the carrier frequency fc is fc0.

On the other hand, in the second embodiment, between 5% and 20% of the duty ratio, for example, 9%
A plurality of duty ratios such as 13% and 17% are set. Duty ratio is 5% ~ 9
The carrier frequency is fc1, the carrier frequency is fc2 when the duty ratio is between 9% and 13%, the carrier frequency is fc3 when the duty ratio is between 13% and 17%, and the duty ratio is between 17% and 20%. In the meantime, the carrier frequency fc is switched in multiple stages such as fc4. Similarly, when the duty ratio is between 80% and 95%, a plurality of duty ratios such as 84%, 88%, and 92% are set. When the duty ratio is between 80% and 84%, the carrier frequency is fc4 and the duty ratio is 84.
The carrier frequency is fc3 between% and 88%, the carrier frequency is fc2 when the duty ratio is between 88% and 92%, and the carrier frequency is f when the duty ratio is between 92% and 95%.
The carrier frequency fc is switched in multiple steps, such as c1.

Here, the number by which the duty ratio is divided between 5% and 20% and the duty ratio to be divided can be set as appropriate. Also, the carrier frequency fcn set in each period
Can be set by the calculation formula shown in FIG. Here, _Xn represents a duty ratio that divides the duty ratio between 5% and 20%. The frequency fcn obtained by calculation formula FIG. 19 (c) between the duty ratio from X _n of X _{n + 1,} it is the upper limit of the frequency at which the amplitude IA of the current flowing through the coil is not less than the amplitude Ith threshold . Therefore, if the carrier frequency fc in each period is switched based on such a calculation formula, the amplitude IA of the current flowing through the coil does not fall below the threshold amplitude Ith regardless of the duty ratio. Thus, the power loss in the digital power amplifier 240 can be suppressed.

Here, since the smoothing filter 250 is a low-pass filter, the amount of amplitude attenuation of the carrier frequency component in the smoothing filter 250 decreases as the value of the carrier frequency fc decreases. When the amplitude attenuation amount of the carrier frequency component decreases, the amplitude of the carrier ripple superimposed on the COM (drive signal) increases. As described above, in the first embodiment, the carrier frequency fc is rapidly reduced from fc0 to fc1 within a duty ratio range of 20% or less or 80% or more. Therefore, for the reasons described above, in the range of duty ratios of 20% or less or 80% or more, COM
The amplitude of the carrier ripple superimposed on the (drive signal) increases uniformly.

Further, as described above, in the second embodiment, when the duty ratio is between 17% and 20%, f
c4 (fc1 <fc4), the carrier frequency is f when the duty ratio is between 13% and 17%.
c3 (fc1 <fc3), the carrier frequency is fc when the duty ratio is between 9% and 13%.
2 (fc1 <fc2) is gradually reduced. Therefore, the duty ratio is 9
In the period of 20% to 20%, the second embodiment can suppress the carrier ripple from being superimposed on the output as compared with the first embodiment.

B-2. Modification of the second embodiment:
In the second embodiment described above, the carrier frequency fc is switched in multiple stages according to the duty ratio. On the other hand, the carrier frequency fc depends on the duty ratio.
May be switched continuously.

FIG. 20 shows a state in which the carrier frequency fc is continuously switched between fc1 and fc0 according to the duty ratio. If the carrier frequency fc is continuously switched in this way, even when the duty ratio is 20% or less, or 80% or more,
The amplitude IA of the current flowing through the coil of the smoothing filter 250 can be held at the threshold amplitude Ith. As a result, power loss in the digital power amplifier 240 can be suppressed.

FIG. 21 is a flowchart of the carrier frequency switching process performed to continuously switch the carrier frequency fc according to the duty ratio. This process is a process executed by the carrier frequency changing unit 270 when the drive waveform signal generation circuit 210 starts outputting WCOM. In the modification of the second embodiment, it is assumed that the drive waveform signal information with flag as shown in FIG. 13B is stored in the waveform memory of the drive waveform signal generation circuit 210.

In the carrier frequency switching process, first, the carrier frequency fc is changed to the standard frequency fc0.
(Step S200). Then, the drive waveform signal generation circuit 210 outputs WCO.
When the output of M (drive waveform signal) is started, drive waveform signal information (WCOM voltage and flag) is acquired from the drive waveform signal generation circuit 210 (step S202).

Then, it is determined whether or not the acquired flag is “1” (step S204). flag
Is set by the flag setting process described above with reference to FIG. 16, and the flag is “1”.
If so, the carrier frequency fc needs to be changed from the standard frequency fc0. Therefore, when the flag is “1” (step S204: yes), the duty ratio D is calculated from the voltage value of WCOM received as the drive waveform signal information (step S206). As described above, the duty ratio D can be calculated by dividing the voltage value indicated by WCOM by the triangular wave amplitude voltage used by the modulation circuit 230 during pulse modulation. Subsequently, the carrier frequency fc is calculated from the calculated duty ratio D according to the following equation:
Is calculated (step S203).
fc = D · (1-D) · Vdd / (2L · Ith)
Here, L is the inductance of the coil of the smoothing filter 250, and Ith is the threshold amplitude of the current flowing through the coil. Vdd is a voltage generated by a power source used in the digital power amplifier 240. Further, as apparent from the equation (7) shown in FIG. 8, the carrier frequency fc obtained by this calculation equation is given when a certain duty ratio D is given.
The carrier frequency fc is such that the amplitude IA of the current flowing through the coil becomes the threshold amplitude Ith. Then, the carrier frequency of the triangular wave used for pulse modulation in the modulation circuit 230 is
The carrier frequency fc thus calculated is changed (step S210).

In the above, when the flag acquired as the drive waveform signal information is set to “1” (
The processing in the case where “yes” is determined in step S204) has been described. However, when the flag setting is not “1” (step S204: no), the carrier frequency fc is
What is necessary is just to set to the standard frequency fc0 (step S212).

Subsequently, the drive waveform signal generation circuit 210 determines whether or not to end the output of the WCOM (step S214). When the output of the WCOM is continued (step S214: no), the process returns to the step S202, and a new one is generated. After acquiring drive waveform signal information, a series of subsequent processes are performed.
On the other hand, when the output of WCOM is terminated (step S214: yes), the carrier frequency switching process shown in FIG. 21 is terminated as it is.

In the modification of the second embodiment described above, the amplitude IA of the current flowing in the coil of the smoothing filter 250 is equal to the threshold value even when the duty ratio of the MCOM output from the modulation circuit 230 is near the upper limit or the lower limit. The carrier frequency fc so that the amplitude Ith is maintained.
Can be switched. For this reason, it is possible to suppress the carrier ripple from being superimposed on the output from the smoothing filter 250 while avoiding an increase in power loss in the digital power amplifier 240 regardless of the duty ratio.

C. Third embodiment:
In the first embodiment and the second embodiment described above, the case where the output voltage (that is, COM) of the smoothing filter 250 is a constant voltage has been described. However, the output voltage of the smoothing filter 250 is not necessarily a completely constant voltage. For example, if the output voltage changes slowly, the above description holds true. Further, if the output voltage does not change abruptly, there is a possibility that the same explanation is valid only for a short time. In the following, a third embodiment extended when the output voltage from the smoothing filter 250 changes will be described. In the third embodiment, only the configuration different from the first embodiment or the second embodiment will be described, and the description of the same configuration will be omitted.

FIG. 22 is an explanatory diagram showing the current I flowing through the coil of the smoothing filter 250 when COM (drive signal) is not constant. Since the piezoelectric element 116 to be driven is a capacitive load, the current flows from the smoothing filter 250 toward the piezoelectric element 116, so that the COM voltage rises and the current flows backward from the piezoelectric element 116 toward the smoothing filter 250. As a result, the COM voltage decreases. Therefore, a current I whose phase is advanced by a half cycle with respect to COM (drive signal) flows through the coil of the smoothing filter 250.

The coil of the smoothing filter 250 has a voltage Vdd from the digital power amplifier 240.
The pulse waveform is output. For this reason, as represented by the equations (3) and (6) shown in FIG.
A current I having a waveform in which a small pulsation corresponding to a modulation period of 0 is superimposed flows.

Therefore, for example, as shown by the broken line in FIG. 22A, when trying to output COM having a large voltage amplitude, the current I flowing through the coil of the smoothing filter 250 is the current of the waveform shown by the solid line in the figure. Become. During the period in which the drive signal rises from 0 toward the maximum value, the current I
Always flows from the digital power amplifier 240 toward the coil side. In this case, A-
As described in 3 above, the charge regeneration of the parasitic capacitance of the MOSFET (H) and the charging of the parasitic capacitance of the MOSFET (L) during the dead time period are not performed. Therefore, it is difficult to suppress the increase in power loss in the digital power amplifier 240 at the time of low duty or high duty as described above. In the period in which the drive signal is decreasing from the maximum value toward 0, the current I
Always flows from the coil toward the digital power amplifier 240. Similarly, charge regeneration of the parasitic capacitance of the MOSFET (L) during the dead time period described in A-3, and MOSFE
The parasitic capacitance of T (H) is not charged. Therefore, it is difficult to suppress the power loss in the digital power amplifier 240 at the time of low duty or high duty as described above.

On the other hand, as shown by the broken line in FIG. 22B, when COM with a small voltage amplitude is output, the current I has a direction within one modulation period as shown by the solid line in the figure. It becomes a form to switch. That is, as described in A-3, charge regeneration of the parasitic capacitance of the MOSFET (H or L) and charging of the parasitic capacitance of the MOSFET (L or H) are performed during the dead time period. Accordingly, as described above, an increase in power loss in the digital power amplifier 240 can be suppressed. In other words, if the absolute value of the amplitude IA of the current I flowing in the coil immediately before entering the dead time period does not fall below the absolute value of the threshold amplitude Ith, the power in the digital power amplifier 240 can be reduced. Loss can be suppressed.

Therefore, attention is paid to the upper limit value IA (+) and the lower limit value IA (−) of the current I that increase or decrease within the modulation period. As shown in FIG. 22C, the upper limit value IA (+) is obtained by adding the component Id (+) accompanying pulse modulation to the component Iload resulting from the application of COM. Further, the lower limit value IA (−) is obtained by adding a component Id accompanying pulse modulation to a component Iload caused by applying COM.
(+) Is added.

Here, as shown in FIG. 22C, the component Iload resulting from COM is a current obtained by multiplying the time differentiation of the COM voltage value VCOM by the combined capacitance of the capacitor and the piezoelectric element 116 constituting the smoothing filter 250. Value. In FIG. 22C, Clpf represents the capacitance of the capacitor constituting the smoothing filter 250, and Cload represents the capacitance of the piezoelectric element 116. Therefore, Iload is determined by COM. On the other hand, the components Id (+) and Id (−) accompanying pulse modulation can be changed by the carrier frequency fc at the time of pulse modulation. From this, the upper limit IA (
If the carrier frequency fc is changed so that the absolute value of +) and the absolute value of the lower limit value IA (−) do not fall below the threshold amplitude Ith, the COM is slowly increased as shown in FIG. Even in the case of a change, power loss in the digital power amplifier 240 can be suppressed.

As an aspect of changing the carrier frequency fc, the upper limit value IA (+) and the lower limit value IA (−) that change every moment with respect to the voltage value of COM are expressed by the calculation formula shown in FIG. The carrier frequency fc can be changed so that the upper limit value IA (+) and the lower limit value IA (−) do not fall below the threshold amplitude Ith. Or COM
The carrier frequency fc is not changed every time according to the voltage value of, but the minimum value IA (+ min) of the upper limit value IA (+) and the maximum value IA (−max) of the lower limit value IA (−) are previously set. The carrier frequency fc may be changed so that any absolute value does not fall below the threshold amplitude Ith.

Further, as shown in FIG. 22A, even when the COM (drive signal) changes greatly in a short time, when the current I of the coil constituting the smoothing filter 250 crosses the current 0, it is a short time. However, the description described above with reference to FIGS. 9 and 10 may be valid. The coil current I becomes zero when COM (driving signal) is an extreme value (maximum value or minimum value), so that the duty ratio D is near the upper limit or the lower limit, and COM is the extreme value. When the value is reached, the carrier frequency fc may be lowered to a predetermined frequency fc1. Even in this case, power loss in the digital power amplifier 240 can be suppressed.

The component Iload caused by COM in the current I flowing through the coil of the smoothing filter 250
Changes depending on the capacitance Cload of the piezoelectric element 116, as shown in FIG. Therefore, when the pulsation generator 110 of the fluid ejecting apparatus 100 is replaced, information (load information) regarding the capacitance Cload of the new piezoelectric element 116 may be acquired.

FIG. 23 is an explanatory diagram showing a circuit configuration of a modified example in which load information can be acquired in the third embodiment. In the illustrated modification, load information acquisition means 280 for acquiring the load information of the replaced pulsation generator 110 (here, information related to the capacitance Cload of the piezoelectric element 116) is provided, and the carrier frequency changing means 270 includes: It is possible to acquire load information from the load information acquisition unit 280.

FIG. 24 is an explanatory diagram showing an example of acquiring load information. In the illustrated example, an ID tag 284 indicating the capacitance Cload of the piezoelectric element 116 is provided on the piezoelectric element 116 side (pulsation generating unit 110). Then, the operator of the fluid ejection device 100 reads the load information described in the ID tag 284 and switches 282 provided in the load information acquisition unit 280.
By setting ON / OFF, load information can be input to the carrier frequency changing means 270. As a result, even when the pulsation generator 110 is replaced and the capacitance Cload of the piezoelectric element 116 is changed, it is possible to appropriately change the carrier frequency fc and prevent the digital power amplifier 240 from increasing the power loss. It becomes.

Alternatively, as shown in FIG. 25, a ROM 286 storing load information is built in the piezoelectric element 116 side (pulsation generating unit 110), and the load information is obtained from the load information acquisition unit 280.
The load information may be acquired by reading the data with a ROM data read circuit 288 provided in the above. Even in this case, when the pulsation generating unit 110 is replaced, information on the capacitance Cload of the new piezoelectric element 116 is transmitted to the carrier frequency changing unit 270, and the carrier frequency fc can be appropriately changed. The amplifier 240 can avoid an increase in power loss.

D. Modification 1
Here, in the various embodiments described above, as shown in FIG. 4, the digital power amplifier 240 is composed of two switch elements connected in a push-pull manner, and a MOSFET is given as an example of the switch elements. I have explained. Further, the MOSFET has been described in which a body diode is parasitically formed in the structure, and the junction capacitance of the body diode exists as Cds which is one of the parasitic capacitances of the switch element. However, depending on the type of the switch element, there is a structure in which the body diode is not formed parasitically (for example, IGBT: insulated gate bipolar transistor). In this case, as described above, an electromotive force is generated in the coil during the dead time.
A reflux diode may be provided in parallel with the switch element. FIG. 26 shows a configuration example of the digital power amplifier 240 in the case where a return diode is provided in parallel with the switch element. FIG. 26 shows an example in which an IGBT is used for the switch element, but the present invention is not limited to this. In the case of providing a free wheeling diode as shown in FIG.
By replacing the Cds of the OSFET, it is possible to avoid an increase in power loss in the digital power amplifier 240.

E. Modification 2
Further, in the digital power amplifier 240, a transient spike-like high voltage may be generated by the switching operation. In order to absorb this, the digital power amplifier 240 is absorbed.
May be provided with a protection circuit. FIG. 27 shows a configuration example in which a snubber circuit is provided as a protection circuit at the output of the digital power amplifier 240. In the case of FIG. 27, the capacitor Cc of the snubber circuit is connected in parallel to the parasitic capacitance Cds of the MOSFET (L).
By considering the OSFET (L) as a combined capacitance obtained by adding Cc to the capacitance of Cds, Cc + Cds, it is possible to avoid an increase in power loss in the digital power amplifier 240.

Also, as described above, when a free-wheeling diode is provided in parallel with the MOSFET, the MOS
For FET (L), the combined capacitance of the junction capacitance of the body diode and the junction capacitance of the free-wheeling diode may be Cds. In addition, when a free-wheeling diode is provided in parallel with the MOSFET and a snubber circuit is provided as a protection circuit, it is possible to suppress power loss in the digital power amplifier 240 by using Cc + Cds as a combined capacitance, Cc + Cds. Become.

Although the capacitive load drive circuits of various embodiments have been described above, the present invention is not limited to all the embodiments described above, and can be implemented in various modes without departing from the scope of the invention. For example, by applying the capacitive load driving circuit of this embodiment to various electronic devices including medical devices such as a fluid ejection device used for forming a microcapsule containing a medicine or a nutrient, power efficiency is improved. A miniaturized electronic device can be provided. Also,
The present invention can also be suitably applied to a capacitive load drive circuit that is mounted on an ink jet printer and drives an ejection nozzle that ejects ink.

DESCRIPTION OF SYMBOLS 100 ... Fluid injection apparatus, 110 ... Pulsation generation | occurrence | production part, 111 ... Nozzle,
112 ... Fluid ejection pipe, 113 ... Second case, 114 ... First case,
115 ... Fluid chamber, 116 ... Piezoelectric element, 120 ... Fluid supply means,
121 ... 1st connection tube, 122 ... 2nd connection tube, 123 ... Fluid container,
130 ... Control unit, 150 ... Wiring cable,
200: capacitive load driving circuit, 210: driving waveform signal generating circuit, 220: arithmetic circuit,
230: modulation circuit, 240: digital power amplifier, 250: smoothing filter,
260 ... compensation circuit, 270 ... carrier frequency changing means,
280 ... Load information acquisition means, 282 ... Switch, 286 ... ROM,
288 ... ROM data read circuit

Claims (7)

A capacitive load drive circuit that drives a capacitive load by applying a drive signal to the capacitive load having a capacitive component,
A drive waveform signal generating circuit for generating a drive waveform signal which is a reference of the drive signal;
A modulation circuit that generates a modulation signal by pulse-modulating the drive waveform signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates the drive signal by smoothing the power amplification modulation signal;
Under a reversing condition in which the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal, the absolute value of the maximum value and the minimum value of the current within the one modulation period is predetermined. A capacitive load drive circuit comprising: carrier frequency changing means for changing a carrier frequency when the modulation circuit performs pulse modulation so as to be equal to or greater than a threshold value. The capacitive load drive circuit according to claim 1,
The digital power amplifier generates the power amplification modulation signal by switching ON / OFF of two switch elements that are push-pull connected between a predetermined voltage generated by a power source and a ground.
The predetermined threshold is:
The predetermined voltage generated by the power source is V,
When switching the ON / OFF of the two switch elements, a dead time which is a time for turning off both of the two switch elements is T,
When the capacitance of the parasitic capacitance of the two switch elements is C,
A capacitive load driving circuit which is a threshold value obtained by a calculation formula of V · C / T. The capacitive load drive circuit according to claim 1,
The digital power amplifier generates the power amplification modulation signal by switching ON / OFF of two switch elements that are push-pull connected between a predetermined voltage generated by a power supply and the ground, and A diode is connected in parallel to the switch element,
The predetermined threshold is:
The predetermined voltage generated by the power source is V,
When switching the ON / OFF of the two switch elements, a dead time which is a time for turning off both of the two switch elements is T,
When the capacitance of the junction capacitance of the diode is Cd,
A capacitive load driving circuit which is a threshold value obtained by a calculation formula V · Cd / T. The capacitive load drive circuit according to claim 1,
The digital power amplifier generates the power amplification modulation signal by switching ON / OFF of two switch elements that are push-pull connected between a predetermined voltage generated by a power supply and the ground, and A capacitor is connected in parallel to at least one of the two switch elements,
The predetermined threshold is:
The predetermined voltage generated by the power source is V,
When switching the ON / OFF of the two switch elements, a dead time which is a time for turning off both of the two switch elements is T,
When the capacitance of the combined capacitance of the capacitor and the parasitic capacitance of the two switch elements is Cs,
A capacitive load driving circuit which is a threshold value obtained by a calculation formula of V · Cs / T. A capacitive load driving circuit according to any one of claims 1 to 4,
Load information acquisition means for acquiring load information related to the magnitude of the capacitive component of the capacitive load;
The capacitive load driving circuit, wherein the carrier frequency changing means is means for changing the carrier frequency according to the load information. A capacitive load drive circuit that drives a capacitive load by applying a drive signal to the capacitive load having a capacitive component,
A drive waveform signal generating circuit for generating a drive waveform signal which is a reference of the drive signal;
A phase lead compensation circuit that performs phase lead compensation on the drive signal and outputs the signal after the phase lead compensation as a feedback signal;
An arithmetic circuit that outputs an error signal by subtracting the feedback signal from the drive waveform signal;
A modulation circuit that generates a modulation signal by pulse-modulating the error signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates the drive signal by smoothing the pulse-wave-shaped power amplification modulation signal;
Under a reversing condition in which the direction of the current flowing from the digital power amplifier to the smoothing filter is reversed within one modulation period of the modulation signal, the absolute value of the maximum value and the minimum value of the current within the one modulation period is predetermined. A capacitive load drive circuit comprising: carrier frequency changing means for changing a carrier frequency when the modulation circuit performs pulse modulation so as to be equal to or greater than a threshold value. A capacitive load driving circuit according to any one of claims 1 to 6,
A supply pump for supplying liquid;
A fluid chamber into which the liquid supplied from the supply pump flows, an actuator that is the capacitive load, and a pulsation generator having an ejection nozzle that ejects the liquid that has flowed into the fluid chamber,
A fluid ejecting apparatus in which the liquid that has flowed into the fluid chamber is ejected in pulses from the ejecting nozzle by applying the drive signal to the actuator.

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