JP4994437B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a system IC (Integrated Circuit) having a nonvolatile memory element and a capacitor element or a resistance element.

  As a semiconductor integrated circuit device, for example, a non-volatile memory device called a flash memory or an EEPROM (Electrically Erasable Programmable Lead Only Memory) is known. In this flash memory, a one-transistor type memory cell in which a memory cell is constituted by one nonvolatile memory element, or one nonvolatile memory element and one selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) are connected in series. A connected two-transistor type memory cell is known. In the nonvolatile memory element, a floating gate type (floating gate type) for storing information in a floating gate electrode (floating gate electrode) between the semiconductor substrate and the control gate electrode, and between the semiconductor substrate and the gate electrode. MNOS (Metal Nitride Oxide Semiconductor) type that uses NO (nitride film / oxide film: Nitride / Oxide) film as the gate insulating film, and stores information in this gate insulating film, the gate between the semiconductor substrate and the gate electrode A MONOS (Metal Oxide Nitride Oxide Semiconductor) type is known in which an ONO (oxide film / nitride film / oxide film) film is used as the insulating film, and information is stored in the gate insulating film. In the floating gate type, an ONO film is used as an interlayer insulating film between the floating gate electrode and the control gate electrode.

  On the other hand, in a semiconductor integrated circuit device, not only active elements such as MISFETs but also generally passive elements such as resistance elements and capacitive elements exist. For example, they are used in delay circuits, load elements, oscillation circuits, power supply stabilization bypass capacitors (bypass capacitors), and the like. There are various known resistance elements and capacitive elements. For example, as a resistance element, a diffusion resistance element formed by introducing impurities into a semiconductor substrate, a polysilicon resistance element formed of a polycrystalline silicon film, and the like are known. As a capacitor element, a semiconductor region (impurity diffusion region) formed by introducing impurities into a semiconductor substrate is used as a lower electrode, and a conductive film provided on the lower electrode with a dielectric film interposed therebetween is used as an upper electrode. Capacitor elements, etc. Capacitor elements having a conductive film provided on the element isolation region on the main surface of the semiconductor substrate as a lower electrode and a conductive film provided on the lower electrode with a dielectric film interposed therebetween as an upper electrode It has been known. As a capacitive element, a capacitive element using the above-described ONO film as a dielectric film is also known.

  In addition, as a well-known document relevant to this invention, there exist the following patent document 1 (Unexamined-Japanese-Patent No. 2000-269449) and patent document 2 (Unexamined-Japanese-Patent No. 2000-164835). Patent Document 1 discloses a manufacturing technique of a semiconductor integrated circuit device having a nonvolatile memory having a floating gate structure and a capacitor. Patent Document 2 discloses a technique for manufacturing an integrated circuit having a nonvolatile memory having a floating gate structure, a high breakdown voltage transistor, and a low breakdown voltage transistor.

JP 2000-269449 A JP 2000-164835 A

  In recent years, in the state-of-the-art technology fields such as multimedia and information communication, data is realized by realizing a system-on-chip structure in which microcomputers, DRAMs, ASICs (Application Specific Integrated Circuits), flash memories, etc. are mixedly mounted in one chip. There are active moves to increase transfer speed, save space (improve packaging density), and reduce power consumption.

  In the case of a system-on-chip that incorporates a logical operation circuit such as a flash memory array and a microcomputer, for example, a plurality of MISFETs that are driven by an external power supply voltage of 3.3 V using an external power supply of 3.3 V, In order to increase the speed, a first internal power supply voltage of 1.8 V is generated by a step-down circuit, and a plurality of MISFETs driven by the first internal power supply voltage are required. Further, a second internal power supply voltage of 10 V to 12 V is generated by the booster circuit, and the second internal power supply voltage (10 to 12 V) is used to drive for writing to the selected memory cell in the flash memory array. Multiple MISFETs are required. Hereinafter, the former MISFET driven at 3.3 V or 1.8 V is referred to as a low breakdown voltage MISFET, and the latter MISFET driven at 10 to 12 V is referred to as a high breakdown voltage MISFET. Each of the low breakdown voltage MISFET and the high breakdown voltage MISFET is built in a CMOS configuration (a pair of a p-type MISFET and an n-type MISFET) in one semiconductor substrate (semiconductor chip).

  On the other hand, a system LSI mounted on a portable card includes a regulator, a central processing unit (CPU), an input / output circuit (I / O), a system controller, a watchdog timer, a random number generator, a ROM (Lead The memory includes a random memory (RAM), a random access memory (RAM), and an EEPROM. In the regulator, I / O, and EEPROM, a plurality of high voltage MISFETs are used. In addition, a plurality of resistance elements are used in the watchdog timer and the timer in the EEPROM. In order to stabilize the power supply voltage, a plurality of bypass capacitors are used.

As a result of studying the system LSI, the present inventor has found the following problems.
In the case where the lower electrode of the capacitive element is formed with the first-layer polycrystalline silicon film and the upper electrode of the capacitive element and the gate electrode of the low breakdown voltage and high breakdown voltage MISFET are formed with the second-layer polycrystalline silicon film, After the lower electrode is formed on the element isolation region of the main surface, heat treatment is performed to form a gate insulating film made of a silicon oxide film. When the gate insulating film is formed, a bird's beak made of a silicon oxide film is formed from the side surface of the lower electrode along the interface between the lower electrode and the element isolation region. The element isolation region on the main surface of the substrate is usually formed of a silicon oxide film. Oxidizing agents such as O ₂ and H ₂ O pass through the silicon oxide film during the heat treatment. Accordingly, when the gate insulating film is formed, a bird's beak of the silicon oxide film extending from the side surface of the lower electrode along the interface between the lower electrode and the element isolation region is formed.

  By forming the bird's beak, the peripheral edge of the lower electrode is lifted, and a warp in which the lower surface of the lower electrode becomes convex occurs in the lower electrode, so that the lower electrode is easily peeled off from the element isolation region. Such a problem becomes conspicuous as the capacity element is miniaturized as the system LSI is highly integrated and multifunctional, and it is difficult to downsize the capacity element. In addition, the yield of the system LSI and the reliability may be reduced.

  Even in the case where the resistance element is formed of the first-layer polycrystalline silicon film on the element isolation region of the substrate and the low-breakdown-voltage and high-breakdown-voltage MISFET gate electrodes are formed of the second-layer polycrystalline silicon film, The bird's beak is formed. Due to the formation of the bird's beak, the resistance value of the resistance element varies. The variation in resistance value due to the bird's beak becomes conspicuous with the miniaturization of the resistance element, so that it is difficult to form a high resistance resistance element by narrowing the width.

  The channel length of the MISFET becomes shorter with miniaturization due to higher integration. When the channel length is shortened, a depletion layer from the source region and the drain region protrudes under the gate electrode, and the potential barrier of the channel formation region is lowered. As a result, the threshold voltage (Vth) decreases, and the drain current (Ids) increases only by slightly increasing the voltage (Vds) between the source region and the drain region, and a constant current region cannot be obtained. Further, when the voltage Vds is increased, a punch-through state in which the depletion layers from the drain region and the source region are brought into contact with each other, and the drain current Ids increases rapidly. That is, the breakdown voltage between the drain region / source region is lowered. Further, since the drain current (subthreshold current) that flows when the gate voltage (Vg) is lower than the threshold voltage Vth increases, the leakage current in the “OFF” state increases.

  Such a deterioration in breakdown voltage between the drain region and the source region and an increase in leakage current in the “OFF state” are suppressed by increasing the impurity concentration of the well region where the MISFET is formed, that is, the impurity concentration of the channel formation region. be able to. Accordingly, the surface impurity concentration of the low-voltage well region where the low breakdown voltage MISFET is formed is set higher than the surface impurity concentration of the high-voltage well region where the high breakdown voltage MISFET is formed.

  The well region is usually formed before the step of forming the gate insulating film. On the other hand, in the gate insulating film of the ONO type nonvolatile memory element, lower and upper oxide films are generally formed by thermal oxidation. Therefore, when the low-pressure well region is formed before the step of forming the gate insulating film of the ONO type nonvolatile memory element, the number of times the low-pressure well region is heat-treated increases. Since the surface impurity concentration in the low-pressure well region is higher than the surface impurity concentration in the high-pressure well region, if the number of heat treatments is increased, the surface impurity concentration in the low-pressure well region decreases, and the characteristics of the low-voltage MISFET change. End up.

  An object of the present invention is to provide a technique capable of realizing a capacitive element having a small occupied area and a large capacitance.

  An object of the present invention is to provide a technology capable of realizing a high-resistance resistance element.

  An object of the present invention is to provide a technique capable of forming a high voltage MISFET without affecting the characteristics of the low voltage MISFET.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor integrated circuit device having a capacitive element in which a lower electrode is provided on an element isolation region on a main surface of a semiconductor substrate, and an upper electrode is provided on the lower electrode with a dielectric film interposed therebetween. ,
An oxidation resistant film (for example, a silicon nitride film) is provided between the element isolation region on the main surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

(2) a MISFET in which a gate electrode is provided on an element formation region on a main surface of a semiconductor substrate with a gate insulating film interposed therebetween; a lower electrode is provided on an element isolation region on the main surface of the semiconductor substrate; A method of manufacturing a semiconductor integrated circuit device having a capacitive element having an upper electrode provided with a dielectric film on an electrode,
The lower electrode is provided on an element isolation region on the main surface of the semiconductor substrate with a first oxidation-resistant film (for example, a silicon nitride film) interposed therebetween, and the upper surface of the lower electrode is a second oxidation-resistant film ( A step of forming the gate insulating film made of a silicon oxide film in an element formation region of the main surface of the semiconductor substrate by performing a heat treatment in a state of being covered with, for example, a silicon nitride film.

(3) A nonvolatile memory element formed in the first region of the main surface of the semiconductor substrate, a MISFET formed in the second region of the main surface of the semiconductor substrate, and element isolation of the main surface of the semiconductor substrate A method for manufacturing a semiconductor integrated circuit device having a capacitive element formed on a region,
(A) performing a heat treatment to form a silicon oxide film in the first region of the main surface of the semiconductor substrate;
After the step (a), a step (b) of forming a first silicon nitride film so as to cover the silicon oxide film and an element isolation region on the main surface of the semiconductor substrate;
After the step (b), a first silicon film is formed on the first silicon nitride film so as to cover the first region of the main surface of the semiconductor substrate and the element isolation region of the main surface of the semiconductor substrate. (C) step of forming
After the step (c), a step (d) of forming a second silicon nitride film on the first silicon film so as to cover the element isolation region on the main surface of the semiconductor substrate;
After the step (d), the second silicon nitride film and the first silicon film are patterned, and the gate electrode of the nonvolatile memory element is formed on the first region of the main surface of the semiconductor substrate. And forming a lower electrode of the capacitive element whose upper surface is covered with the second silicon nitride film on the first silicon nitride film on the element isolation region of the main surface of the semiconductor substrate. e) a process;
(F) After the step (e), heat treatment is performed to form a gate insulating film made of a silicon oxide film in the second region of the main surface of the semiconductor substrate;
After the step (f), a step (g) of forming a second silicon film so as to cover the gate insulating film and the second silicon nitride film on the lower electrode;
After the step (g), the second silicon film is patterned to form a gate electrode of the MISFET on the gate insulating film, and on the second silicon nitride film on the lower electrode. (H) forming an upper electrode of the capacitive element.

(4) A semiconductor integrated circuit device having a resistance element provided on an element isolation region on a main surface of a semiconductor substrate,
An oxidation resistant film (for example, a silicon nitride film) is provided between the element isolation region on the main surface of the semiconductor substrate and the resistance element and on the resistance element.

(5) A semiconductor integrated circuit having a MISFET provided with a gate electrode on an element formation region on the main surface of the semiconductor substrate with a gate insulating film interposed therebetween, and a resistance element provided on an element isolation region on the main surface of the semiconductor substrate. A circuit device manufacturing method comprising:
The resistance element is provided on an element isolation region on the main surface of the semiconductor substrate with a first oxidation-resistant film (for example, a silicon nitride film) interposed therebetween, and the upper surface of the resistance element is a second oxidation-resistant film ( A step of forming the gate insulating film made of a silicon oxide film in an element formation region of the main surface of the semiconductor substrate by performing a heat treatment in a state of being covered with, for example, a silicon nitride film.

(6) A nonvolatile memory element formed in the first region of the main surface of the semiconductor substrate, a MISFET formed in the second region of the main surface of the semiconductor substrate, and element isolation of the main surface of the semiconductor substrate A method of manufacturing a semiconductor integrated circuit device having a resistance element formed on a region,
(A) performing a heat treatment to form a silicon oxide film in the first region of the main surface of the semiconductor substrate;
After the step (a), a step (b) of forming a first silicon nitride film so as to cover the silicon oxide film and an element isolation region on the main surface of the semiconductor substrate;
After the step (b), a first silicon film is formed on the first silicon nitride film so as to cover the first region of the main surface of the semiconductor substrate and the element isolation region of the main surface of the semiconductor substrate. (C) step of forming
After the step (c), a step (d) of forming a second silicon nitride film on the first silicon film so as to cover the element isolation region on the main surface of the semiconductor substrate;
After the step (d), the second silicon nitride film and the first silicon film are patterned, and the gate electrode of the nonvolatile memory element is formed on the first region of the main surface of the semiconductor substrate. And (e) a step of forming the resistance element whose upper surface is covered with the second silicon nitride film on the first silicon nitride film on the element isolation region of the main surface of the semiconductor substrate. When,
(F) After the step (e), heat treatment is performed to form a gate insulating film made of a silicon oxide film in the second region of the main surface of the semiconductor substrate;
(G) a step of forming a second silicon film so as to cover the gate insulating film after the step (f);
(H) After the step (g), the second silicon film is patterned to form a gate electrode of the MISFET on the gate insulating film.

(7) a MISFET in which a gate electrode is provided on an element formation region of a main surface of a semiconductor substrate with a gate insulating film interposed therebetween;
A capacitive element in which a lower electrode is provided on an element isolation region of a main surface of a semiconductor substrate, and an upper electrode is provided on the lower electrode with a dielectric film interposed therebetween;
A method of manufacturing a semiconductor integrated circuit device having a resistance element provided on an element isolation region of a main surface of the semiconductor substrate,
The lower electrode and the resistance element are provided on the element isolation region on the main surface of the semiconductor substrate with a first oxidation resistance film (for example, a silicon nitride film) interposed therebetween, and the upper surface of the lower electrode and the upper surface of the resistance element Forming a gate insulating film made of a silicon oxide film in an element forming region on the main surface of the semiconductor substrate by performing a heat treatment in a state where the gate insulating film is covered with a second oxidation resistant film (for example, a silicon nitride film). Have.

(8) a nonvolatile memory element formed in the first region of the main surface of the semiconductor substrate;
A MISFET formed in a second region of the main surface of the semiconductor substrate;
A capacitive element formed on the first element isolation region of the main surface of the semiconductor substrate;
A method of manufacturing a semiconductor integrated circuit device having a resistance element formed on a second element isolation region on a main surface of the semiconductor substrate,
(A) performing a heat treatment to form a silicon oxide film in the first region of the main surface of the semiconductor substrate;
(B) a step of forming a first silicon nitride film so as to cover the silicon oxide film and the first and second element isolation regions of the main surface of the semiconductor substrate after the step (a);
After the step (b), on the first silicon nitride film so as to cover the first region of the main surface of the semiconductor substrate and the first and second element isolation regions of the main surface of the semiconductor substrate. Forming a first silicon film in (c),
After the step (c), a second silicon nitride film is formed on the first silicon film so as to cover the first and second element isolation regions on the main surface of the semiconductor substrate (d). When,
After the step (d), the second silicon nitride film and the first silicon film are patterned, and the gate electrode of the nonvolatile memory element is formed on the first region of the main surface of the semiconductor substrate. A lower electrode of the capacitive element having an upper surface covered with the second silicon nitride film on the first silicon nitride film on the first element isolation region of the main surface of the semiconductor substrate; and the semiconductor Forming the resistive element having an upper surface covered with the second silicon nitride film on the first silicon nitride film on the second element isolation region of the main surface of the substrate;
(F) After the step (e), heat treatment is performed to form a gate insulating film made of a silicon oxide film in the second region of the main surface of the semiconductor substrate;
After the step (f), a step (g) of forming a second silicon film so as to cover the second silicon nitride film on the lower electrode and the resistance element, and the gate insulating film;
After the step (g), the second silicon film is patterned, and the capacitive element is formed on the gate insulating film on the gate electrode of the MISFET and on the second silicon nitride film on the lower electrode. (H) forming an upper electrode.

(9) a nonvolatile memory element in the first region of the main surface of the semiconductor substrate;
A first MISFET provided in a second region of the main surface of the semiconductor substrate;
A method for manufacturing a semiconductor integrated circuit device, comprising: a second MISFET having an operating voltage lower than that of the first MISFET, and a second MISFET provided in a third region of the main surface of the semiconductor substrate. And
Forming a gate insulating film including a thermal oxide film in a first region of the main surface of the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a first well region in a second region of the main surface of the semiconductor substrate;
Forming a second well region in a third region of the main surface of the semiconductor substrate,
The step of forming the second well region is performed after the gate electrode is formed.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, it is possible to realize a capacitive element having a small occupation area and a large capacitance.
According to the present invention, a high-resistance resistance element can be realized.
According to the present invention, a high voltage MISFET can be formed without affecting the characteristics of the low voltage MISFET.
According to the present invention, it is possible to improve the manufacturing yield of the semiconductor integrated circuit device.

1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view in which a part (memory cell portion) of FIG. 1 is enlarged. FIG. 2 is an enlarged schematic cross-sectional view of a part of FIG. 1 (a high breakdown voltage pMIS portion and a resistance element portion). FIG. 2 is an enlarged schematic cross-sectional view of a part of FIG. 1 (low breakdown voltage p-type MIS portion and capacitive element portion). It is a circuit block diagram comprised in the semiconductor integrated circuit device which is one Embodiment of this invention. FIG. 6 is a circuit diagram showing a schematic configuration of the EEPROM of FIG. 5. It is a schematic explanatory drawing of the bypass capacitor in FIG. FIG. 6 is a diagram showing a leakage current characteristic when a positive voltage is applied to the upper electrode in the capacitive element of one embodiment of the present invention. FIG. 6 is a diagram showing leakage current characteristics when a negative voltage is applied to the upper electrode in the capacitive element according to the embodiment of the present invention. It is a figure which shows the upper electrode voltage dependence of the capacitive element of one Embodiment of this invention. It is a figure which shows the polycrystalline silicon width dependence of resistance value in the resistive element of one Embodiment of this invention. It is typical sectional drawing in the manufacturing process of the semiconductor integrated circuit device which is one Embodiment of this invention. FIG. 13 is a schematic cross-sectional view during the manufacturing process of the semiconductor integrated circuit device, following FIG. 12; FIG. 14 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13; FIG. 15 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14; FIG. 16 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15; FIG. 17 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16; FIG. 18 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17; FIG. 19 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18; FIG. 20 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19; FIG. 21 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 20; FIG. 22 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 21; FIG. 23 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22; FIG. 24 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 23; FIG. 25 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 24; FIG. 26 is a schematic cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 25; FIG. 27 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 26; FIG. 28 is a schematic cross sectional view showing the semiconductor integrated circuit device during a manufacturing step following that of FIG. 27;

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted. Further, in the cross-sectional view, in order to make the drawing easy to see, some hatching that shows the cross-section may be omitted.
In the present embodiment, an example in which the present invention is applied to a system LSI used as a semiconductor integrated circuit device, for example, incorporated in an IC card will be described.
FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a system LSI of the present embodiment.
FIG. 2 is an enlarged schematic cross-sectional view of a part (memory cell portion) of FIG.
FIG. 3 is an enlarged schematic cross-sectional view of a part of FIG. 1 (high breakdown voltage pMIS portion and resistance element portion).
FIG. 4 is an enlarged schematic cross-sectional view of a part of FIG. 1 (low breakdown voltage p-type MIS portion and capacitive element portion).
FIG. 5 is a circuit block diagram showing a schematic configuration of the system LSI of the present embodiment.
FIG. 6 is a circuit diagram showing a schematic configuration of the EEPROM of FIG.
FIG. 7 is a block diagram illustrating an example of a usage pattern of the capacitive element of FIG.

  As shown in FIG. 5, the system LSI of this embodiment includes a regulator, a central processing unit (CPU), an input / output circuit (I / O), a system controller, a watchdog timer, a random number generator, a ROM, a RAM, An EEPROM or the like is mounted on the semiconductor chip 1A.

  The EEPROM constituting the system LSI is used as a data memory of an IC card, for example, and a high voltage (−Vpp) for rewriting (erasing and writing) is provided through a booster circuit as shown in FIG. 6 mounted on the semiconductor chip 1A. It comes to be supplied. The booster circuit boosts an external power supply voltage of 1.8-5V to 1.5V, which is stepped down by a regulator for low-voltage logic other than EEPROM, and generates -10.5V. At that time, a high voltage is supplied to the output node by a multi-stage charge pump circuit using a capacitive element of several tens of pF.

  In addition, in the semiconductor chip 1A, as shown in FIG. 7, between the internal power supply Vdd and Vss (0V) which regulates the external power supply Vcc, it is called a bypass capacitor (bypass capacitor) for stabilizing the internal power supply voltage. A large number of capacitive elements C are connected. The capacitive element C is often arranged under the wiring in the wiring channel region between the circuit blocks (modules).

  The system LSI basically has a CMIS device configuration in which an n channel conductivity type MISFET and a p channel conductivity type MISFET are combined. This CMIS device is usually called CMOS.

  In addition, a relatively low voltage-driven MISFET such as a MISFET driven at 1.8 V or a MISFET driven at 3.3 V has a smaller device structure for higher speed. Therefore, such a MISFET has a low gate breakdown voltage. Hereinafter, such a MISFET is referred to as a low breakdown voltage MISFET.

  Further, a relatively high voltage-driven MISFET such as a MISFET driven at 12 V has a high gate breakdown voltage. Hereinafter, such a MISFET is referred to as a high breakdown voltage MISFET.

  Next, a specific structure of the system LSI will be described with reference to FIGS. FIG. 1 shows a memory cell Me, a low breakdown voltage p-type MISFET-QLp, a resistance element 10b, a high breakdown voltage p-type MISFET-QHp, and a capacitive element C. The memory cell Me is used in the memory cell array of the EEPROM, the low breakdown voltage p-type MISFET-QLp is used in the central processing unit and the like, and the resistance element 10b is used in the watchdog timer and the like. The high-breakdown-voltage p-type MISFET-QHp is used in regulators, input / output circuits, EEPROM peripheral circuits, and the like, and the capacitive element C is used as the aforementioned bypass capacitor.

  As shown in FIGS. 1 to 4, the system LSI is mainly composed of a semiconductor substrate 1 (hereinafter simply referred to as a substrate) from p-type single crystal silicon as a semiconductor substrate. On the main surface of the substrate 1, a plurality of element formation regions partitioned by the element isolation regions 5 are provided. The element formation region includes a memory cell formation region, a low breakdown voltage MIS formation region, a high breakdown voltage MIS formation region, and the like. The element isolation region 5 is formed by, for example, a well-known STI (Shallow Trench Isolation) technique. In the element isolation region 5 by the STI technique, a shallow groove (for example, a groove having a depth of about 300 [nm]) is formed on the main surface of the substrate 1, and then an insulating film made of, for example, a silicon oxide film is formed on the main surface of the substrate 1. The film is formed by a CVD (Chemical Vapor Deposition) method and then planarized by a CMP (Chemical Mechanical Polishing) method so that the insulating film remains selectively in the shallow groove. .

  As shown in FIGS. 1 and 2, an n-type well region 2 is formed in the memory cell formation region on the main surface of the substrate 1, and a high-voltage p-type well region 4 is formed in the n-type well region 2. Has been. In the memory cell formation region on the main surface of the substrate 1, memory cells Me are formed. The memory cell Me is composed of one nonvolatile memory element Qm and one selection MISFET-Qs connected in series to the nonvolatile memory element Qm.

  As shown in FIGS. 1 and 3, an n-type well region 2 is formed in a low-pressure pMIS formation region on the main surface of the substrate 1, and a low-pressure n-type well region 14 is formed in the n-type well region 2. Is formed. Further, a low breakdown voltage p-type MISFET-QLp is formed in the low-voltage pMIS formation region of the main surface of the substrate 1.

  As shown in FIGS. 1 and 3, a resistance element 10b is formed on the element isolation region 5 on the main surface of the substrate 1, and a low-voltage system p is formed below the element isolation region 5 where the resistance element 10b is formed. A mold well region 15 is formed. Hereinafter, the element isolation region 5 in which the resistance element 10b is formed is referred to as a first element isolation region.

  As shown in FIGS. 1 and 4, an n-type well region 2 is formed in a high-pressure pMIS formation region on the main surface of the substrate 1, and a high-voltage n-type well region 3 is formed in the n-type well region 2. Is formed. Further, a high breakdown voltage p-type MISFET-QHp is formed in the high voltage pMIS formation region of the substrate 1.

  As shown in FIGS. 1 and 4, a capacitive element C is formed on the element isolation region 5 on the main surface of the substrate 1, and a high-voltage system is provided below the element isolation region 5 where the capacitive element C is formed. A p-type well region 4 is formed. Hereinafter, the element isolation region 5 in which the capacitive element C is formed is referred to as a second element isolation region.

  In order to prevent parasitic channels, n-type is interposed between the high-voltage p-type well region 4 and the low-voltage n-type well region 14, between the high-voltage n-type well region 3 and the high-voltage p-type well region 4, and the like. Well region 3a is formed.

  As shown in FIG. 2, the nonvolatile memory element Qm mainly includes a channel formation region, a gate insulating film 16, a gate electrode (memory gate electrode) 10a, a source region, and a drain region. The gate insulating film 16 is provided on the main surface of the substrate 1, the gate electrode 10a is provided on the main surface of the substrate 1 with the gate insulating film 16 interposed therebetween, and the channel formation region is a surface layer portion of the substrate immediately below the gate electrode 10a. Specifically, it is provided in the surface layer portion of the high-pressure p-type well region 4. The source region and the drain region are provided so as to sandwich the channel formation region on both sides in the channel length direction of the channel formation region.

  The source region and the drain region of the nonvolatile memory element Qm are configured to have a pair of n-type semiconductor regions 21 that are extension regions and a pair of n-type semiconductor regions 25 that are contact regions. The n-type semiconductor region 21 is formed in alignment with the gate electrode 10a. The n-type semiconductor region 25 is formed in alignment with the sidewall spacer 24 provided on the side wall of the gate electrode 10 a and has a higher impurity concentration than the n-type semiconductor region 21.

  The nonvolatile memory element Qm uses an ONO (oxide / nitride / oxide) film as the gate insulating film 16 between the high-voltage p-type well region 4 (substrate) and the gate electrode 10a. The gate insulating film 16 is of a MONOS (Metal Oxide Nitride Oxide Semiconductor) type. In the nonvolatile memory element Qm of this embodiment, an ONO film made of silicon oxide film / silicon nitride film / silicon oxide film is used for the gate insulating film 16.

  As shown in FIG. 2, the selection MISFET-Qs mainly includes a channel formation region, a gate insulating film 17, a gate electrode 19a, a source region, and a drain region. The gate insulating film 17 is provided on the main surface of the substrate 1, the gate electrode 19a is provided on the main surface of the substrate 1 with the gate insulating film 17 interposed therebetween, and the channel formation region is a surface layer portion of the substrate immediately below the gate electrode 19a. Specifically, it is provided in the surface layer portion of the high-pressure p-type well region 4. The source region and the drain region are provided so as to sandwich the channel formation region on both sides in the channel length direction of the channel formation region.

  The source region and the drain region of the selection MISFET-Qs are configured to have a pair of n-type semiconductor regions 21 that are extension regions and a pair of n-type semiconductor regions 25 that are contact regions. The n-type semiconductor region 21 is formed in alignment with the gate electrode 19a. The n-type semiconductor region 25 is formed in alignment with the sidewall spacer 24 provided on the side wall of the gate electrode 19a.

  The threshold voltage of the non-volatile memory element Qm becomes high if many electrons are trapped in the trap in the silicon nitride film of the gate insulating film 16, and the potential of the word line formed integrally with the gate electrode 10a becomes high. However, the transistor is not “ON”. When no electrons are present in the trap in the silicon nitride film of the gate insulating film 16, the threshold voltage is lowered and turned “ON”. In order to inject (write) electrons into the silicon nitride film of the gate insulating film 16, a positive voltage (for example, 1.5V) is applied to the gate electrode 10a, and a negative high voltage ( For example, −10.5 V) is applied, and the silicon oxide film of the gate insulating film 16 is tunneled from the channel formation region (the high-voltage p-type well region 4). On the contrary, when erasing, a negative high voltage (for example, −8.5 V) is applied to the gate electrode 10a, and a positive voltage (for example, 1.5 V) is applied to the high-voltage p-type well region 4, Electrons in the silicon nitride film of the insulating film 16 are emitted to the channel formation region (high breakdown voltage p-type well region 4) by the tunnel effect, and holes are tunnel-injected from the channel formation region into the silicon nitride film. Is called.

  As shown in FIG. 3, the low breakdown voltage p-type MISFET-QLp mainly has a channel formation region, a gate insulating film 18, a gate electrode 19b, a source region, and a drain region. The gate insulating film 18 is provided on the main surface of the substrate 1, the gate electrode 19b is provided on the main surface of the substrate 1 with the gate insulating film 18 interposed therebetween, and the channel formation region is a surface layer portion of the substrate immediately below the gate electrode 19b. Specifically, it is provided in the surface layer portion of the low-pressure n-type well region 14. The source region and the drain region are provided so as to sandwich the channel formation region on both sides in the channel length direction of the channel formation region.

  The source region and the drain region of the low breakdown voltage p-type MISFET-QLp are configured to have a pair of p-type semiconductor regions 23 that are extension regions and a pair of p-type semiconductor regions 26 that are contact regions. The p-type semiconductor region 23 is formed in alignment with the gate electrode 19b. The p-type semiconductor region 26 is formed in alignment with the sidewall spacer 24 provided on the side wall of the gate electrode 19 b and has a higher impurity concentration than the p-type semiconductor region 23.

  As shown in FIG. 3, the resistance element 10b is provided with a contact region for connecting an upper layer wiring at one end and the other end located on the opposite sides. The resistance element 10b is mainly composed of, for example, a polycrystalline silicon film.

  As shown in FIG. 4, the high breakdown voltage p-type MISFET-QHp mainly has a channel formation region, a gate insulating film 17, a gate electrode 19d, a source region, and a drain region. The gate insulating film 17 is provided on the main surface of the substrate 1, the gate electrode 19b is provided on the main surface of the substrate 1 with the gate insulating film 17 interposed therebetween, and the channel formation region is a surface layer portion of the substrate immediately below the gate electrode 19d. Specifically, it is provided in the surface layer portion of the high-pressure n-type well region 3. The source region and the drain region are provided so as to sandwich the channel formation region on both sides in the channel length direction of the channel formation region.

  The source region and drain region of the high breakdown voltage p-type MISFET-QHp have a pair of p-type semiconductor regions 22 that are extension regions and a pair of p-type semiconductor regions 26 that are contact regions. The p-type semiconductor region 22 is formed in alignment with the gate electrode 19d. The p-type semiconductor region 26 is formed in alignment with the sidewall spacer 24 provided on the side wall of the gate electrode 19 d and has a higher impurity concentration than the p-type semiconductor region 22.

  As shown in FIG. 4, the capacitive element C is provided with a lower electrode 10c provided on the second element isolation region of the main surface of the substrate 1, and a dielectric film interposed on the lower electrode 10c. The upper electrode 19c is included. In the capacitive element C of the present embodiment, an ONO film composed of the silicon oxide film 11 / the silicon nitride film 12 / the silicon oxide film 13 is used as the dielectric film. The high-voltage p-type well region 4 under the second element isolation region is fixed at a constant potential (for example, 0 V) so as not to affect the capacitive element C.

  The gate electrode 10a of the nonvolatile memory element Qm, the resistor element 10b, and the lower electrode 10c of the capacitor element C are mainly formed of, for example, a first-layer polycrystalline silicon film. The gate electrode 19a of the selection MISFET-Qs, the gate electrode 19b of the low breakdown voltage p-type MISFET-QLp, the upper electrode 19c of the capacitive element C, and the gate electrode 19d of the high breakdown voltage p-type MISFET-QHp are, for example, a second layer. It is formed mainly of a crystalline silicon film. Impurities for reducing the resistance value are introduced into the polycrystalline silicon films of the first layer and the second layer.

  In the gate insulating film 16 of the nonvolatile memory element Qm, the lower silicon oxide film has a thickness of about 1.8 [nm], the silicon nitride film has a thickness of about 15 [nm], and the upper silicon oxide film has a thickness of about 15 [nm], for example. For example, the thickness is about 3 [nm]. These upper and lower silicon oxide films are formed by, for example, a thermal oxidation method.

  The gate insulating film 17 of the selection MISFET-Qs and the high breakdown voltage p-type MISFET-QHp is formed with a thickness of, for example, about 18 [nm], and the gate insulating film 17 of the low breakdown voltage p-type MISFET-QLp is, for example, 3.7. It is formed with a thickness of about [nm]. These gate insulating films 16 and 17 are formed by, for example, a thermal oxidation method.

  The gate length of the nonvolatile memory element Qm is, for example, about 500 [nm], the gate length of the selection MISFET-Qs is, for example, about 400 [nm], and the gate length of the low breakdown voltage p-type MISFET-QLp is, for example, about 160 [nm]. The gate length of the high breakdown voltage p-type MISFET-QHp is, for example, about 900 [nm].

  As shown in FIGS. 2, 3 and 4, in the nonvolatile memory element Qm, the selection MISFET-Qs, the low breakdown voltage p-type MISFET-QLp, the high breakdown voltage p-type MISFET-QHp, the capacitive element C, and the resistance element 10b, The gate electrode (10a, 19a, 19b, 19d), the surface of the semiconductor region (25, 26), the surface of the upper electrode 19c, the surface of the contact region of the lower electrode 10c, and the opposite side of the resistance element 10b. A silicide layer 28 that is a metal / semiconductor reaction layer is formed on the surfaces of the two contact regions in order to reduce the resistance. These silicide layers 28 are formed in alignment with the sidewall spacers 24 by, for example, a salicide (Self Aligned Silicide) technique.

  On the main surface of the substrate 1, an interlayer insulating film 29 made of, for example, a silicon oxide film is provided so as to cover the above-described active elements and passive elements. Source / drain contact holes that reach the silicide layer 28 from the surface of the interlayer insulating film 29 are provided on the semiconductor regions 25 and 26, and conductive plugs 30 are embedded in the source / drain contact holes. ing. The semiconductor regions 25 and 26 are electrically connected to the wiring 31 extending on the interlayer insulating film 29 with the silicide layer 28 and the conductive plug 30 interposed therebetween.

  Although not shown, a gate contact hole that reaches the silicide layer 28 from the surface of the interlayer insulating film 29 is provided on the gate electrodes 19a, 19b, and 19d, and a conductive plug is provided inside the gate contact hole. 30 is embedded. The gate electrodes 19a, 19b, and 19d are electrically connected to the wiring 31 extending on the interlayer insulating film 29 with the silicide layer 28 and the conductive plug 30 interposed therebetween.

  An upper electrode contact hole that reaches the silicide layer 28 from the surface of the interlayer insulating film 29 is provided on the upper electrode 19c, and a conductive plug 30 is embedded in the upper electrode contact hole. The upper electrode 19 c is electrically connected to the wiring 31 extending on the interlayer insulating film 29 with the silicide layer 28 and the conductive plug 30 interposed therebetween.

  A lower electrode contact hole reaching the silicide layer 28 from the surface of the interlayer insulating film 29 is provided on the contact region of the lower electrode 10c, and a conductive plug 30 is embedded in the lower electrode contact hole. Yes. The lower electrode 10 c is electrically connected to the wiring 31 extending on the interlayer insulating film 29 with the silicide layer 28 and the conductive plug 30 interposed therebetween.

  Resistive contact holes that reach the silicide layer 28 from the surface of the interlayer insulating film 29 are respectively provided on one and the other contact regions of the resistive element 10b, and a conductive plug 30 is provided inside the resistive contact hole. Embedded. One and the other contact regions of the resistive element 10b are electrically connected to the wiring 31 extending on the interlayer insulating film 29 with the silicide layer 28 and the conductive plug 30 interposed therebetween.

  As shown in FIG. 4, between the lower electrode 10c of the capacitive element C and the second element isolation region (element isolation insulating film) on the main surface of the substrate 1, for example, a silicon nitride film 8 is used as an oxidation resistant film. For example, a silicon oxide film 9 is provided between the silicon nitride film 8 and the lower electrode 10c. That is, the lower electrode 10 c of the capacitive element C is provided on the second element isolation region on the main surface of the substrate 1 with an oxidation resistant film made of the silicon nitride film 8 interposed therebetween. In the present embodiment, the silicon nitride film 8 is formed in the same process as the silicon nitride film of the gate insulating film 16 of the nonvolatile memory element Qm, and the silicon oxide film 9 is an upper layer of the gate insulating film 16 of the nonvolatile memory element Qm. The silicon oxide film is formed in the same process.

  In the capacitive element C, as shown in FIG. 4, the lower electrode 10c is formed in a larger planar size than the upper electrode 19c. This is to make it easy to connect the upper layer wiring to the lower electrode 10c. Therefore, the lower electrode 10c is provided with a contact region for connecting an upper layer wiring. Further, the area occupied by the capacitive element C is determined by the planar size of the lower electrode 10c.

  As described above, the dielectric film of the capacitive element C is formed of the ONO film composed of the silicon oxide film 11 / the silicon nitride film 12 / the silicon oxide film 13. Therefore, an oxidation resistant film made of the silicon nitride film 12 is provided between the lower electrode 10c and the upper electrode 19c.

The silicon nitride film 8 is about 15 [nm] thick, the silicon oxide film 9 is about 3 [nm] thick, the silicon oxide film 11 is about 6 [nm] thick, and the silicon nitride film 12 is For example, the thickness is about 26 [nm], and the silicon oxide film 13 is about 1 [nm], for example. In this case, the capacitance per unit area is about 1.9 [fF / μm ² ], and 19 [pF] at 100 [μm] square.

It is desirable that the leakage current flowing through the dielectric film of the capacitive element C is sufficiently small. FIG. 8 is a diagram showing leakage current characteristics when a positive voltage is applied to the upper electrode in the capacitive element C in which the area of the dielectric film between the upper electrode and the lower electrode is 18000 [μm ² ]. The film thickness of the silicon nitride film 12 is used as a parameter. As shown in FIG. 8, the leakage current decreases as the thickness of the silicon nitride film 12 increases, but the leakage current becomes remarkable from about 10 [V].

  FIG. 9 is a diagram showing a leakage current characteristic when a negative voltage is applied to the upper electrode in the capacitive element C having the same area as FIG. The silicon nitride film 12 is used as a parameter. As shown in FIG. 9, when the thickness of the silicon nitride film 12 is 26 [nm], almost no leakage current flows until −14 [V]. Since the absolute voltage of the high voltage in the EEPROM of FIGS. 5 and 6 is 12 [V], it is desirable to use the upper electrode as a negative voltage. When used as a bypass capacitor for stabilizing the power supply voltage, the polarity does not matter. The reason why the leakage current has polarity dependency is that the thickness of the silicon oxide film 11 is 6 [nm] and the thickness of the silicon oxide film 13 is 1 [nm].

  FIG. 10 is a diagram illustrating the upper electrode voltage dependency of the capacitive element C. In FIG. As shown in FIG. 10, the capacitance value decreases on the negative voltage side because the lower electrode is depleted. The reason why the capacitance value decreases more on the negative voltage side as the silicon nitride film 12 is thinner is that the lower electrode is more easily depleted. It is characterized in that the dependency on applied voltage is extremely small as compared with a MOS type capacitor element in which a semiconductor region formed on a substrate is a lower electrode.

  As shown in FIG. 3, for example, a silicon nitride film 8 is provided as an oxidation resistant film between the resistance element 10 b and the first element isolation region on the main surface of the substrate 1. For example, a silicon oxide film 9 is provided between the resistance element 10b. That is, the resistance element 10 b is provided on the first element isolation region of the main surface of the substrate 1 with an oxidation resistant film made of the silicon nitride film 8 interposed therebetween. In the present embodiment, the silicon nitride film 8 is formed in the same process as the silicon nitride film of the gate insulating film 16 of the nonvolatile memory element Qm, and the silicon oxide film 9 is an upper layer of the gate insulating film 16 of the nonvolatile memory element Qm. The silicon oxide film is formed in the same process.

  As shown in FIGS. 1 to 4, the low-pressure n-type well region 14 is formed shallower than the high-pressure n-type well region 3, and the surface concentration of the low-pressure n-type well region 14 is high-pressure n-type. The surface concentration of the well region 3 is higher (darker). The low-pressure p-type well region 15 is formed shallower than the high-pressure p-type well region 4, and the surface concentration of the low-pressure p-type well region 15 is higher than the surface concentration of the high-pressure p-type well region 4 ( It is dark).

  Next, the manufacture of the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS. 12 to 28 are schematic cross-sectional views during the manufacturing process of the semiconductor integrated circuit device.

  First, a substrate 1 made of single crystal silicon having a specific resistance of 10 [Ωcm] is prepared, and thereafter, an element isolation region 5 for partitioning an element formation region is formed on the main surface of the substrate 1 as shown in FIG. The element isolation region 5 is formed using, for example, a well-known STI technique. Specifically, in the element isolation region 5, a shallow groove (for example, a groove having a depth of about 300 [nm]) is formed on the main surface of the substrate 1, and then, for example, a silicon oxide film is formed on the main surface of the substrate 1. The insulating film to be formed is formed by the CVD method, and then the insulating film is formed by planarizing by the CMP method so that the insulating film is selectively left inside the shallow groove. In this step, a buffer insulating film 6 made of, for example, a silicon oxide film is formed in the element formation region on the main surface of the substrate 1.

  Next, an impurity for forming a well region is selectively ion-implanted into the main surface of the substrate 1, and then a heat treatment for activating the impurity is performed, so that an n-type well region 2 is formed as shown in FIG. Then, a high-voltage n-type well region 3, an n-type well region 3a for preventing a parasitic channel, and a high-voltage p-type well region 4 are formed.

For example, phosphorus (P) is used as an impurity for forming the n-type well region 2. This phosphorus is ion-implanted under the conditions of an acceleration energy of 2 MeV and a dose of 5.0 × 10 ¹² [atoms / cm ² ].
For example, phosphorus (P) and boron difluoride (BF ₂ ) are used as impurities for forming the high-pressure n-type well region 3.
This phosphorus ion implantation is
Acceleration energy is 1 MeV, dose is 8.0 × 10 ¹² [atoms / cm ² ],
Acceleration energy is 460 KeV, dose amount is 5.0 × 10 ¹¹ [atoms / cm ² ],
The acceleration energy is 180 KeV and the dose is 1.0 × 10 ¹² [atoms / cm ² ].
The ion implantation of boron difluoride is performed under the conditions of an energy of 100 KeV and a dose of 1.5 × 10 ¹² [atoms / cm ² ].

For example, boron (B) and boron difluoride (BF ₂ ) are used as impurities for forming the high-pressure p-type well region 4.
This boron ion implantation is
Acceleration energy is 500 KeV, dose amount is 8.0 × 10 ¹² [atoms / cm ² ],
Acceleration energy is 150 KeV, dose amount is 1.8 × 10 ¹² [atoms / cm ² ],
The acceleration energy is 50 KeV and the dose is 1.2 × 10 ¹² [atoms / cm ² ].
The ion implantation of boron difluoride is performed under the conditions of an acceleration energy of 100 KeV and a dose of 2.5 × 10 ¹² [atoms / cm ² ].
Boron difluoride for forming the high-breakdown-voltage n-type and p-type well regions is implanted for adjusting the threshold voltage.

  In this step, the n-type well region 2 and the high-voltage p-type well region 4 are formed in the memory cell formation region on the main surface of the substrate 1. An n-type well region 2 is formed under the low breakdown voltage pMIS formation region on the main surface of the substrate 1 and the first element isolation region. In addition, an n-type well region 2 and a high-voltage n-type well region 3 are formed in the high breakdown voltage pMIS formation region on the main surface of the substrate 1. In addition, an n-type well region 2 and a high breakdown voltage p-type well region 4 are formed under the second element isolation region on the main surface of the substrate 1. Further, an n-type well region 3 a for preventing parasitic channels is formed on the main surface of the substrate 1.

  Next, a part of the buffer insulating film 6 (region where the nonvolatile memory element is formed) in the memory cell formation region on the main surface of the substrate 1 is selectively removed by etching, and then in an oxygen atmosphere diluted with nitrogen As shown in FIG. 14, the substrate is subjected to a heat treatment in the non-volatile memory element formation region from which a part of the buffer insulating film 6 is removed, for example, a very thin oxide having a thickness of about 1.8 [nm]. A silicon film 7 is formed.

  Next, as shown in FIG. 15, silicon nitride having a thickness of, for example, about 18 [nm] is formed on the entire surface of the main surface of the substrate 1 including the silicon oxide film 7 and the first and second element isolation regions. A film 8 is formed by a CVD method, and then the substrate 1 is subjected to heat treatment in a steam atmosphere. As shown in FIG. 15, a silicon oxide film having a thickness of, for example, about 3 nm is formed on the surface of the silicon nitride film 8. A film 9 is formed. In this step, the thickness of the silicon nitride film 8 is reduced from 18 [nm] to about 15 [nm]. In this step, an ONO (silicon oxide film 7 / silicon nitride film 8 / silicon oxide film 9) film is formed as a gate insulating film of the nonvolatile memory element Qm on the high-voltage p-type well region 4 in the memory cell formation region. Is formed.

  Next, as shown in FIG. 16, a first layer having a thickness of, for example, about 200 nm is formed on the entire surface of the silicon oxide film 9 including the memory cell formation region and the first and second element isolation regions. The polycrystalline silicon film 10 is formed by the CVD method, and then an impurity (for example, phosphorus (P)) for reducing the resistance value is ion-implanted into the polycrystalline silicon film 10, and then heat treatment for activating the impurity is performed. Apply.

  Next, as shown in FIG. 17, the silicon oxide film 11, the silicon nitride film 12, and the like are formed on the entire surface of the polycrystalline silicon film 10 including the first and second element isolation regions from the surface of the polycrystalline silicon film 10. A silicon oxide film 13 is sequentially formed by a CVD method. The silicon oxide film 11 is formed with a film thickness of about 6 [nm], the silicon nitride film 12 is formed with a film thickness of about 26 [nm], and the silicon oxide film 13 is formed with a film thickness of about 70 [nm], for example.

  Next, the silicon oxide film 13, the silicon nitride film 12, the silicon oxide film 11, and the polycrystalline silicon film 10 are sequentially patterned, and as shown in FIG. 18, the gate electrode of the nonvolatile memory element Qm is formed in the memory cell formation region. 10a, a resistive element 10b is formed on the first element isolation region, and a lower electrode 10c of the capacitive element C is formed on the second element isolation region. Patterning of the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 11 is performed sequentially using a mask made of, for example, a photoresist film on the silicon oxide film 13. The patterning of the polycrystalline silicon film 10 is performed using an ONO film composed of the silicon oxide film 13, the silicon nitride film 12, and the silicon oxide film 11 as a mask.

  In this step, the non-volatile memory element Qm is interposed on the memory cell formation region on the main surface of the substrate 1 with a gate insulating film 16 made of ONO (silicon oxide film 7 / silicon nitride film 8 / silicon oxide film 9) interposed therebetween. Gate electrode 10a is formed.

  Further, a resistance element 10b having an oxidation resistance film made of a silicon nitride film 8 interposed on the first element isolation region of the main surface of the substrate 1 and an upper surface covered with an oxidation resistance film made of a silicon nitride film 12. Is formed.

  Further, a capacitive element C in which an oxidation resistant film made of the silicon nitride film 8 is interposed on the second element isolation region of the main surface of the substrate 1 and the upper surface is covered with an oxidation resistant film made of the silicon nitride film 12. The lower electrode 10c is formed.

  Further, an ONO (silicon oxide film 11 / silicon nitride film 12 / silicon oxide film 13) film used as a dielectric film of the capacitive element C is formed on the lower electrode 10c.

  Further, in this step, the silicon oxide film 13 on the resistance element 10b and the lower electrode 10c and the silicon oxide film around the resistance element 10b and the lower electrode 10c are formed by overetching at the time of patterning the polycrystalline silicon film 10. The film thickness of 9 becomes thin.

  Next, as shown in FIG. 19, the silicon nitride film 8 around the gate electrode 10 a, the resistance element 10 b, and the lower electrode 10 c is removed, and then a low-pressure well region is formed on the main surface of the substrate 1. As shown in FIG. 20, a low-voltage n-type well region 14 and a first element isolation region are formed in the low breakdown voltage pMIS formation region. A low-pressure p-type well region 15 is formed below.

As an impurity for forming the low-pressure n-type well region 14, for example, phosphorus (P) is used.
This phosphorus ion implantation is
Acceleration energy is 360 KeV, dose amount is 2.0 × 10 ¹³ [atoms / cm ² ],
Acceleration energy is 100 KeV, dose amount is 1.5 × 10 ¹² [atoms / cm ² ],
The acceleration energy is 40 KeV and the dose is 8.0 × 10 ¹² [atoms / cm ² ].
For example, boron (B) and boron difluoride (BF ₂ ) are used as impurities for forming the low-pressure p-type well region 15.
This boron ion implantation is
Acceleration energy is 200 KeV, dose is 1.5 × 10 ¹³ [atoms / cm ² ],
Acceleration energy is 120 KeV, dose amount is 5.0 × 10 ¹² [atoms / cm ² ],
The acceleration energy is 50 KeV and the dose is 1.5 × 10 ¹² [atoms / cm ² ].
The ion implantation of boron difluoride is performed under the conditions of an acceleration energy of 60 KeV and a dose of 2.0 × 10 ¹³ [atoms / cm ² ].
Boron difluoride for forming the low-pressure p-type well region is implanted for adjusting the threshold voltage.

  Here, the low-pressure well region (14, 15) is formed after the gate insulating film of the nonvolatile memory element Qm is formed. Therefore, since the low-pressure well region is not subjected to the heat treatment when the silicon oxide film 7 is formed and the heat treatment when the silicon oxide film 9 is formed, the number of times that the low-pressure well region is heat-treated can be reduced.

  Next, the buffer insulating film 6 on the high-voltage p-type well region 4, the low-pressure n-type well region 14, and the high-voltage n-type well region 3 is removed, and then the substrate 1 is subjected to heat treatment, and FIG. As shown in FIG. 21, a thick silicon oxide film having a thickness of, for example, about 18 [nm] is formed on the high-voltage p-type well region 4, the low-voltage n-type well region 14, and the high-voltage n-type well region 3. A gate insulating film 17 is formed. By removing the buffer insulating film 6, the thickness of the silicon oxide film 13 on the resistance element 10b and the lower electrode 10c is reduced.

  In this step, since an oxidation-resistant film made of the silicon nitride film 8 is provided between the lower electrode 10c and the second element isolation region, oxidation of the lower surface of the lower electrode 10c can be suppressed. . Further, since the upper surface of the lower electrode 10c is covered with an oxidation resistant film made of the silicon nitride film 12 in the dielectric film, the oxidation of the lower electrode 10c can be suppressed.

  Further, in this step, since an oxidation resistant film made of the silicon nitride film 8 is provided between the resistance element 10b and the first element isolation region, oxidation of the lower surface of the resistance element 10b is suppressed. Can do. Further, since the upper surface of the resistance element 10b is covered with the oxidation resistant film made of the silicon nitride film 12, the oxidation of the resistance element 10b can be suppressed.

  Next, the gate insulating film 17 on the low-pressure n-type well region 14 is selectively removed, and then the substrate 1 is subjected to a heat treatment, and as shown in FIG. For example, the gate insulating film 18 made of a thin silicon oxide film having a thickness of about 3.7 [nm] is formed. By this heat treatment, the thickness of the gate insulating film 17 is changed from 18 [nm] to 19 [nm], and the thickness of the silicon oxide film 13 on the resistance element 10b and the lower electrode 10c is set to 1 [nm].

  In this step, since an oxidation-resistant film made of the silicon nitride film 8 is provided between the lower electrode 10c and the second element isolation region, oxidation of the lower surface of the lower electrode 10c can be suppressed. . Further, since the upper surface of the lower electrode 10c is covered with an oxidation resistant film made of the silicon nitride film 12 in the dielectric film, the oxidation of the lower electrode 10c can be suppressed.

  Further, in this step, since an oxidation resistant film made of the silicon nitride film 8 is provided between the resistance element 10b and the first element isolation region, oxidation of the lower surface of the resistance element 10b is suppressed. Can do. Further, since the upper surface of the resistance element 10b is covered with the oxidation resistant film made of the silicon nitride film 12, the oxidation of the resistance element 10b can be suppressed.

  Next, as shown in FIG. 23, the entire surface of the main surface of the substrate 1 including the gate oxide films 17 and 18 and the silicon oxide film 13 on the lower electrode 10c has a thickness of about 250 [nm], for example. A polycrystalline silicon film 19 of the second layer is formed by a CVD method, and then an impurity for reducing the resistance value is ion-implanted into the polycrystalline silicon film 19, and then a heat treatment for activating the impurity is performed. As shown in FIG. 23, a silicon oxide film 20 having a thickness of, eg, about 70 [nm] is formed on the entire surface of the polycrystalline silicon film 19 by a CVD method.

  Next, the silicon oxide film 20 and the polycrystalline silicon film 19 are sequentially patterned. As shown in FIG. 24, the gate electrode 19a of the selection MISFET-Qs is formed on the gate insulating film 17 in the memory cell formation region. The gate electrode 19b of the low breakdown voltage p-type MISFET-QLp is formed on the gate insulating film 18 in the breakdown voltage MIS formation region, the gate electrode 19d of the high breakdown voltage p-type MISFET-QHp is formed on the gate insulation film 17 in the high breakdown voltage pMIS formation region, and the lower electrode. An upper electrode 19c is formed on the ONO film on 10c.

  Next, impurities (for example, phosphorus) are formed in the high-voltage p-type well region 4 in the memory cell formation region, and impurities (for example, boron difluoride and punch-through stoppers are formed in the low-voltage n-type well region 14 in the low breakdown voltage pMIS formation region. Phosphorus), an impurity (for example, boron difluoride) is selectively ion-implanted into the high-voltage n-type well region 3 in the high breakdown voltage pMIS formation region, and as shown in FIG. 25, the high-voltage p-type in the memory cell formation region. In the well region 4, an n-type semiconductor region (extension region) 21 aligned with the gate electrode 10a, an n-type semiconductor region (extension region) 21 aligned with the gate electrode 19a, and a low-voltage n-type well region 14 in the low breakdown voltage pMIS formation region The p-type semiconductor region (extension region) 23 aligned with the gate electrode 19b and the high-voltage n-type well region 3 in the high breakdown voltage pMIS formation region Over preparative matched p-type semiconductor region to the electrode 19d (the extension region) 22 is formed.

  Next, as shown in FIG. 26, sidewall spacers 24 are formed on the sidewalls of the gate electrodes 10a, 19a, 19b, and 19d. For the sidewall spacer 24, an insulating film made of, for example, a silicon oxide film is formed on the entire main surface of the substrate 1 by the CVD method, and thereafter, the insulating film is subjected to anisotropic etching such as RIE (Reactive Ion Etching). Formed by. In this step, the sidewall spacer 24 is formed in alignment with the gate electrode. The sidewall spacer 24 is also formed on the sidewalls of the resistance element 10b, the lower electrode 10c, and the upper electrode 19c.

  Next, impurities (for example, phosphorus and arsenic) are selectively ion-implanted into the high-voltage p-type well region 4 in the memory cell formation region, and as shown in FIG. 27, the high-voltage p-type well region in the memory cell formation region. 4, an n-type semiconductor region (contact region) 25 aligned with the sidewall spacer 24 is formed. Further, impurities (for example, boron difluoride and boron) are selectively ion-implanted into the low-voltage n-type well region 14 in the low breakdown voltage pMIS formation region and the high-voltage n-type well region in the high breakdown voltage pMIS formation region. As shown in FIG. 27, a p-type semiconductor region (contact region) aligned with a sidewall spacer 24 is formed in the low-voltage n-type well region 14 in the low breakdown voltage pMIS formation region and the high-voltage n-type well region in the high breakdown voltage pMIS formation region. ) 26 is formed.

  Next, the natural oxide film or the like is removed, and the surface of the gate electrode (10a, 19a, 19b, 19d), the surface of the contact region of the resistance element 10b, the surface of the contact region of the lower electrode 10c, and the surface of the upper electrode 19c After exposing, for example, a cobalt film 27 is formed as a refractory metal film on the entire main surface of the substrate 1 including these surfaces by a sputtering method, and then silicon (Si) in the semiconductor region (25, 26) is formed. ), Si in the gate electrodes (10a, 19a, 19b, 19d), Si in the contact region of the resistance element 10b, Si in the contact region of the lower electrode 10c, Si in the upper electrode 19c, and Co in the cobalt film 27 As shown in FIG. 28, the surface of the semiconductor region (25, 26), the gate electrodes (10a, 19a, 19b, 19d) are applied. Surface, the surface of the contact region of the resistor element 10b, a surface of the contact region of the lower electrode 10c, and the surface of the upper electrode 19c, forming a silicide (CoSi) layer 28 is a metal-semiconductor reaction layer. The silicide layer 28 is formed in alignment with the sidewall spacer 24.

  Next, the unreacted cobalt film 27 other than the region where the silicide layer 28 is formed is selectively removed, and then heat treatment for activating (CoSi2) the silicide layer 28 is performed.

  By this process, the nonvolatile memory element Qm, the selection MISFET-Qs, the low breakdown voltage p-type MISFET-QLp, the high breakdown voltage p-type MISFET-QHp, the resistance element 10b, and the capacitive element C are almost completed.

  Next, an interlayer insulating film 29 made of, for example, a silicon oxide film is formed on the entire main surface of the substrate 1 including the above-described active elements and passive elements by the CVD method, and then the surface of the interlayer insulating film 29 is subjected to CMP. Flatten by the method.

  Next, source / drain contact holes, gate contact holes, resistance element contact holes, lower electrode contact holes, and upper electrode contact holes reaching the silicide layer 28 from the surface of the interlayer insulating film 29 are formed. Thereafter, a conductive plug 30 is formed by embedding a conductive material such as a metal in these contact holes, and then a wiring 31 is formed on the interlayer insulating film 29, whereby the structure shown in FIGS. It becomes.

  FIG. 11 is a diagram showing the dependency of the resistance value on the polycrystalline silicon width in the resistance element 10b. The film thickness at the time of deposition of the silicon nitride film 12 on the resistance element 10b is used as a parameter. As shown in FIG. 11, as the thickness of the silicon nitride film 12 increases, oxidation from the side surface of the polycrystalline silicon film during the process is suppressed, and the fine line effect is suppressed. In order to reduce the width of the polycrystalline silicon film to 1 [μm] or less, it is desirable that the thickness of the deposited silicon nitride film 12 is 24 [nm] or more.

Thus, according to this embodiment, the following effects can be obtained.
An oxidation resistant film made of the silicon nitride film 8 is provided between the second element portion region on the main surface of the substrate 1 and the lower electrode 10c, and an upper surface of the lower electrode 10c is made of the silicon nitride film 12. By forming a gate insulating film 17 and 18 made of a silicon oxide film on the main surface of the substrate 1 by performing a heat treatment in a state covered with, oxidation of the lower surface and the upper surface of the lower electrode 10c can be suppressed, Furthermore, since the occurrence of bird's beak extending along the interface between the lower electrode 10c and the second element isolation region from the side surface of the lower electrode 10c can be suppressed, warpage of the lower electrode 10c caused by the bird's beak is suppressed. And the problem that the lower electrode 10c is peeled off can be suppressed. As a result, it is possible to realize a capacitive element C that has a small occupation area and a large capacitance.

  In addition, a system LSI on which the capacitor element C having a small occupied area and a large capacity is mounted can be manufactured with a high yield.

  Further, the oxidation resistant film between the second element isolation region and the lower electrode 10c is formed in the same process as the silicon nitride film 8 in the gate insulating film of the nonvolatile memory element Qm, and the acid resistant film on the lower electrode 10c is formed. Since the chemical conversion film is the silicon nitride film 12 in the dielectric film of the capacitive element C, it is possible to realize the capacitive element C having a small occupied area and a large capacity without increasing the number of manufacturing steps. A system LSI equipped with a capacitive element C having a large capacity can be manufactured with a high yield.

  An oxidation resistant film made of the silicon nitride film 8 is provided between the first element region on the main surface of the substrate 1 and the resistance element 10b, and the upper surface of the resistance element 10b is made of the silicon nitride film 12. Since the gate insulating films 17 and 18 made of a silicon oxide film are formed on the main surface of the substrate 1 by performing a heat treatment in the state covered with, oxidation of the lower surface and the upper surface of the resistance element 10b can be suppressed. Even if the resistance element 10b is formed by the polycrystalline silicon film 10 of the first layer, the high resistance resistance element 10b can be stably formed.

  Further, the oxidation resistance film between the first element isolation region and the resistance element 10b is formed in the same process as the silicon nitride film 8 in the gate insulating film of the nonvolatile memory element Qm, and the oxidation resistance film on the resistance element 10b. Since the conductive film is formed in the same process as the silicon nitride film 12 in the dielectric film of the capacitive element C, the high-resistance resistance element 10b can be stably formed without increasing the number of manufacturing steps. .

  Since the low-pressure well region (14, 15) is formed after forming the gate insulating film 16 made of the ONO film of the nonvolatile memory element Qm, the number of times the low-pressure well region is heat-treated can be reduced. A decrease in the surface impurity concentration in the low-pressure well region can be suppressed. As a result, a high voltage MISFET can be formed without affecting the characteristics of a normal low voltage MISFET.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate, 2 ... N-type well region, 3 ... High voltage type n-type well region, 3a ... N-type well region, 4 ... High-voltage type p-type well region, 5 ... Element isolation region, 6 ... Buffer insulating film 7 ... Silicon oxide film, 8 ... Silicon nitride film, 9 ... Silicon oxide film,
DESCRIPTION OF SYMBOLS 10 ... Polycrystalline silicon film, 10a ... Gate electrode, 10b ... Resistance element, 10c ... Lower electrode,
11 ... Silicon oxide film, 12 ... Silicon nitride film, 13 ... Silicon oxide film,
14 ... low-pressure n-type well region, 15 ... low-pressure p-type well region,
16, 17, 18 ... gate insulating film,
19 ... polycrystalline silicon film, 19a, 19b, 19d ... gate electrode, 19c ... upper electrode,
20 ... silicon oxide film, 21, 25 ... n-type semiconductor region, 22, 23, 26 ... p-type semiconductor region, 24 ... sidewall spacer, 27 ... cobalt film, 28 ... silicide layer, 29 ... interlayer insulating film, 30 ... Conductive plug, 31 ... wiring,
QHp: High breakdown voltage p-type MISFET, QLp: Low breakdown voltage p-type MISFET,
Me ... memory cell, Qm ... nonvolatile memory element (MONOS type), Qs ... selection MISFET (high voltage n-type MISFET).

Claims (6)

A nonvolatile memory element formed in a first region of the main surface of the semiconductor substrate, a MISFET formed in a second region of the main surface of the semiconductor substrate, and an element isolation region of the main surface of the semiconductor substrate A method of manufacturing a semiconductor integrated circuit device having a formed resistive element,
(A) performing a heat treatment to form a silicon oxide film in the first region of the main surface of the semiconductor substrate;
After the step (a), a step (b) of forming a first silicon nitride film so as to cover the silicon oxide film and an element isolation region on the main surface of the semiconductor substrate;
After the step (b), a first silicon film is formed on the first silicon nitride film so as to cover the first region of the main surface of the semiconductor substrate and the element isolation region of the main surface of the semiconductor substrate. (C) step of forming
After the step (c), a step (d) of forming a second silicon nitride film on the first silicon film so as to cover the element isolation region on the main surface of the semiconductor substrate;
After the step (d), the second silicon nitride film and the first silicon film are patterned, and the gate electrode of the nonvolatile memory element is formed on the first region of the main surface of the semiconductor substrate. And (e) a step of forming the resistance element whose upper surface is covered with the second silicon nitride film on the first silicon nitride film on the element isolation region of the main surface of the semiconductor substrate. When,
(F) After the step (e), heat treatment is performed to form a gate insulating film made of a silicon oxide film in the second region of the main surface of the semiconductor substrate;
(G) a step of forming a second silicon film so as to cover the gate insulating film after the step (f);
(H) After the step (g), the second silicon film is patterned to form a gate electrode of the MISFET on the gate insulating film (h) step. Manufacturing method. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The method of manufacturing a semiconductor integrated circuit device, further comprising a step of forming a silicon oxide film on the first silicon nitride film after the step (b) and before the step (c). Method. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The step of forming the element isolation region includes
Forming a groove in the semiconductor substrate;
Depositing an insulating film on the semiconductor substrate including in the trench;
And polishing the insulating film to embed the insulating film in the groove. A non-volatile memory element formed in the first region of the main surface of the semiconductor substrate, a MISFET formed in the second region of the main surface of the semiconductor substrate, and an element isolation region of the main surface of the semiconductor substrate. A semiconductor integrated circuit device having a resistive element,
The nonvolatile memory element is
A charge storage film formed on the semiconductor substrate in the first region;
A first gate electrode formed on the charge storage film;
The MISFET is
A gate insulating film formed on the semiconductor substrate in the second region;
A second gate electrode formed on the gate insulating film,
The capacitive element is
A first silicon nitride film formed on the element isolation region;
The resistance element formed on the first silicon nitride film,
The charge storage film of the nonvolatile memory element and the first silicon nitride film of the resistance element are formed of the same layer,
The semiconductor integrated circuit device, wherein the first gate electrode and the resistance element of the nonvolatile memory element are formed of a first silicon film in the same layer. The semiconductor integrated circuit device according to claim 4,
The device isolation region is formed by embedding an insulating film in a groove formed in the semiconductor substrate. The semiconductor integrated circuit device according to any one of claims 4 and 5,
2. A semiconductor integrated circuit device according to claim 1, wherein a data write operation of the nonvolatile memory element is performed by injecting electrons into a trap in the charge storage film.

Images