JP4987745B2 - Time information receiver and radio-controlled clock - Google Patents

Description

  The present invention relates to a time information receiver and a radio-controlled timepiece that receives a radio signal including time information and corrects the time, and determines the period from the timing of the waveform of the JJY (registered trademark) signal of the received time information, Regarding seeking.

  Currently, in Japan and abroad, long-wave standard radio waves with time information including time codes have already been transmitted. Time information receivers or radio wave corrections that receive the standard radio waves and correct the time to display the correct time. Watches are in practical use.

  For example, in Japan, a radio-controlled timepiece receives a long-wave (40 kHz or 60 KHz) standard time radio wave that conveys Japanese standard time with high accuracy, and corrects the time based on the received radio wave to display an accurate time.

  This type of radio-controlled timepiece receives a standard time radio signal and, in the case of an analog type, drives the pointer drive system based on the received signal, and in the case of a digital type, digitally corrects the display time. And a control circuit, and in the time correction mode, the pointer position or the display time is corrected according to the time information (time code signal; TCO signal) of the received radio signal.

The reception signal received by the antenna is AM-modulated with long wave (40 kHz, 60 KHz) standard time radio waves according to the “1” and “0” signals (see FIGS. 7A and 7B).
The format of the long time (40 kHz) standard time radio wave that conveys Japan Standard Time with high accuracy is specifically a signal of 40 kHz for 500 ms (0.5 s) in 1 second (s) in the case of a “1” signal. In the case of a “0” signal, a 40 kHz signal is sent for 800 ms (0.8 s) in 1 second (s), and in the case of a “P” signal (synchronization signal), 1 second (s ), A 40 kHz signal is sent for 200 ms (0.2 s).

FIG. 8 shows an example of time data for one frame. A reference marker M is provided at the start of the frame, and information of 40, 20, 10, 8, 4, 2, and 1 minute is represented by “0” and “1” in each 1 second period from 2 seconds to 9 seconds. A period from 13 seconds to 19 seconds represents time information, a period from 23 seconds to 34 seconds represents a total day, a period from 37 seconds to 39 seconds represents a sign, a period from 41 seconds to 44 seconds represents DUT1, and 10 , 20, 30, 40 and 50 seconds are provided with position markers (Pn) P1 to P5 and P0.
In the example of FIG. 8, each time data is set according to the values of the “H” and “L” levels, and DUT1 = −0.3 at 17:25 on the 114th.

Next, FIGS. 9A to 9D show waveforms of time information when the reception state of the radio-controlled timepiece changes.
FIG. 9A shows an example of a radio wave waveform diagram. Correspondingly, FIG. 9B shows a waveform of time information (TCO signal) when the radio wave reception state is good. The waveform of this time information indicates the pulse waveform of “1”, “0”, and “P” signals.

FIGS. 9C and 9D show TCO signal waveforms when the intensity of the received radio wave is weak or when the reception state is bad due to a lot of noise.
As shown in FIG. 9 (c), when the radio field intensity is very weak, for example, when a “1” signal is indicated, it becomes “H” level for 1 second (or 1 cycle), and the P signal remains at “L” level. Thus, the code cannot be determined. Also in the “P” signal, the “H” level period may change to the “L” level.
As shown in FIG. 9D, when there is a lot of noise, for example, in one second indicating a “1” signal, an arbitrary period having an “H” level period becomes “L” level. As another example, “0” In one second indicating a signal, an arbitrary period having a period of “L” level becomes “H” level. In the “P” signal, for example, an arbitrary period with an “L” level period is “H” level, and an arbitrary period with an “H” level period is “L” level.

  In addition to this, Patent Document 1 discloses that when decoding time information (time code) signal, the received signal has noise by checking the appropriateness of the time information at the edge of the waveform, for example, the rising or falling timing. A technique for appropriately detecting time information even when many components are included is disclosed.

FIG. 10 shows the configuration of a circuit block of a radio-controlled timepiece 300 which is another conventional example.
The radio-controlled timepiece 300 includes an antenna 310, a receiving circuit 320, and a synchronization signal processing circuit 330.
For example, a bar antenna structure is used as the antenna 310 in order to receive a reception signal at 40 KHz, for example. The reception circuit 320 includes a tuning circuit (not shown), an RF amplifier (amplifier circuit), a filter circuit (BPF, etc.), a post-stage amplifier, a detection circuit, a waveform shaping circuit, and the like. With these circuits, the reception circuit 320 amplifies and detects the reception signal received by the antenna 310, further shapes the waveform, and outputs time information (TCO signal).

The synchronization signal processing circuit 330 includes a data acquisition circuit 331, a data storage circuit (buffer circuit) 332, and a second synchronization processing circuit 333.
The TCO signal output from the receiving circuit 320 is supplied to the data acquisition circuit 331, and the 1-second period (one cycle) data of the TCO signal is captured.
For example, as shown in FIGS. 11A to 11C, an “H” level pulse present within a one-second cycle is captured and counted by the data acquisition circuit 331. For example, in each cycle from 1 second to 10 seconds, data is acquired by sequentially performing a count operation and stored in the data storage circuit 332.
The data storage circuit (buffer circuit) 332 is provided, and for example, data for 1 to 8 (or 10 seconds) is stored as second synchronization data.

  These data stored in the data storage circuit 332 are supplied as synchronization data to the second synchronization processing circuit 333, and data processing is performed by, for example, a microcomputer (not shown) and a control program. The start time in each second of the TCO signal is calculated by rearranging the positions of the second-stored data and counting the data in each 1-second cycle, and the appropriate falling edge synchronization signal (start in each 1-second cycle) Position).

The time code signal is stored for a predetermined period, for example, 8 seconds of data in a buffer circuit, and the data is stored in accordance with a predetermined control program using a control device (not shown) such as a microcomputer (also referred to simply as a microcomputer). Rearrangement, the number of “H” (high) levels and the number of “L” (low) levels of the waveform are calculated, and the falling position of the JJY waveform is detected.
JP 2007-139703 A JP 2005-83990 A

By the way, when the above-described current method is used, since only one data acquisition circuit and one data storage circuit (buffer circuit) are provided, the data storage circuit stores, for example, data for 8 seconds. It is necessary to provide capacity. In addition, it is necessary to rearrange the data of each second and to count the number of waveform levels at each timing.
In this method, when the radio wave reception status is poor, the electric field strength is extremely weak, and the noise level is mixed, the noise resistance performance is improved, but on the other hand, the above processing requires a long processing time and more. Program area is required.

  The present invention has been made in view of such circumstances, and a synchronization signal processing circuit is provided in the subsequent stage of the reception circuit of the time information reception device and the radio-controlled timepiece, and the synchronization processing circuit acquires data in parallel and falls. Determine period and save. By performing the second synchronization processing using the stored data, the processing program for synchronization detection is reduced as compared with the conventional one, and the processing time for the synchronization detection is shortened.

In order to achieve the above object, the present invention provides a time information receiving apparatus that receives a standard time radio signal and corrects the time, receives the standard time radio signal, processes the received signal, and derives time information. Receiving circuit, a plurality of data acquisition circuits that sequentially capture the time of successive rising edges or successive falling edges of the waveform with the passage of time of the time information derived from the reception circuit, and the data acquisition circuit A plurality of period determination circuits that are provided in parallel correspondingly and determine the period in parallel from the time data of the edges supplied from the data acquisition circuits, and the period data determined by the plurality of period determination circuits And a synchronization processing circuit for obtaining a synchronization signal from.

The present invention also provides a radio-controlled timepiece that receives a standard time radio signal and corrects the time, receives the standard time radio signal, processes the received signal to derive time information, and A plurality of data acquisition circuits that sequentially capture the time of successive rising edges or successive falling edges of the waveform with the passage of time of the time information derived from the reception circuit, and in parallel corresponding to each of the data acquisition circuits A plurality of period determining circuits that determine the period in parallel from the edge time data supplied from each of the data acquisition circuits, and a synchronization that obtains a synchronization signal from the period data determined by the plurality of period determining circuits. And a processing circuit.

The time information derived from the received acquisition circuitry in each of the data acquisition circuit in a different cycle, determines the period from the time between the falling edges of or rising edge time of the waveform of the time information, a reasonable start of each cycle Find the time (or sync signal).

  The present invention is provided with a plurality of data acquisition circuits and a synchronization data storage circuit (buffer circuit) and takes in waveform data with a time difference of time information, thereby reducing the number of synchronization data storage circuits and determining a synchronization signal. Time can be shortened. Further, the present invention can obtain an accurate synchronization signal even when the start waveform of the TCO signal is unstable due to noise or the like.

FIG. 1 is a front view showing the external appearance of a radio-controlled timepiece 100 according to an embodiment of the present invention.
The radio-controlled timepiece 100 includes a housing 101, a dial plate 102, a second hand (first pointer) 103, a minute hand (second pointer) 104, and an hour hand (second pointer) 105. The dial 102 has a plurality of circular, square, and linear indicators arranged on the circumference centered on the rotation center of the pointer so that the second, minute, or hour is indicated by the rotation position of the pointer. ing.

The radio-controlled timepiece 100 according to the present embodiment receives a standard radio signal including time information, a broadcast radio wave transmitted by a predetermined broadcasting station, or a signal including time information received by wire, and based on the received time information. It has a function to correct the time displayed by the hands (second hand, hour and minute hands).
The radio-controlled timepiece 100 has a pointer drive source that drives the second hand with a first period, for example, one second, in normal hand movement. When the time information is received and the time information is different from the display time, the second hand 103 is driven. A function to control the drive source so that the drive is performed with a second period different from the first period of 1 second, for example, 1.1 seconds, 1.3 seconds, or 0.9 seconds, 0.7 seconds. ing.

FIG. 2 is a block diagram showing the signal processing system circuit 10 of the radio-controlled timepiece 100.
In FIG. 2, numeral 10 is a signal processing system circuit, numeral 11 is a standard radio wave signal receiving system, numeral 12 is a reset / forced reception switch, numeral 13A is a first oscillation circuit, numeral 13B is a second oscillation circuit, numeral 14 Is a control circuit, number 15 is a drive circuit, number 16 is a light emitting element, number 17 is a buffer circuit, numbers 18 and 19 are drive circuits, number 20 is an alarm amplifier, number 21 is a speaker, _VCC is a power supply voltage, C ₁ -C ₅ shows _capacitors, R 1 to R ₆ is a resistance element, respectively. The radio-controlled timepiece 100 includes, for example, a first drive system that drives a second hand (not shown), a second drive system that drives a minute hand and hour hand that are hands, a light-transmitting light detection sensor, and a user directly by hand. A manual correction system for adjusting the time is provided.

  A detection signal of the optical sensor 160 is output to the control circuit 14. Based on the detection signal from the optical sensor 160, the control circuit 14 determines whether the amount of light on the front side of the radio-controlled timepiece 100 is less than a predetermined threshold value.

  The standard radio wave signal receiving system 11 receives a long wave (for example, 40 kHz) including a time code signal transmitted from an antenna 11a and a key station (not shown), for example, and performs predetermined signal processing as a pulse signal S11 (TCO signal). And a long wave receiving circuit 11b that outputs to the control circuit 14.

The reset / forced reception switch 12 is turned on when various states of the control circuit 14 are returned to the initial state.
When the reset / forced reception switch 12 is turned on or when a battery (not shown) is set, the radio-controlled timepiece receives a standard time radio signal forcibly and corrects the time (forced correction mode). )become.

The oscillation circuit 13A includes a ceramic oscillator CRM and capacitors C ₂ and C ₃ , and supplies a basic clock CLKA having a predetermined frequency, for example, 800 kHz, to the control circuit 14.

The oscillation circuit 13B includes a crystal oscillator CRY and capacitors C ₄ and C ₅ , and supplies a basic clock CLKB having a predetermined frequency, for example, 32 kHz, to the control circuit 14.

The control circuit 14 includes a synchronization signal processing circuit that determines a synchronization signal with a period of 1 second when noise or electric field strength is weak, a control unit that controls each functional circuit described later, an alarm generation circuit (not shown), a clock timer, a clock And a signal detection / correction circuit. When the time of the time information signal cycle is set in advance or when the standard time radio signal is forcibly received and the time is corrected, driving power is supplied to the standard radio signal reception system 11.
The reception time can be set, for example, six times each in the morning (AM) and in the afternoon (PM). Note that this time can be arbitrarily selected, and it is not always necessary to receive AM and PM six times each.

Drive circuit 15 is constituted by a pnp transistor _{Q 1} and the resistance element _R 1, _{R 2.}
The base of the transistor Q ₁ is via the resistance element R ₁ is connected to the output line of the drive signal DR ₁ of control circuit 14 is connected to the cathode of the light emitting device 16 comprising a light emitting diode collector through the resistance element R _2, The emitter is connected to the supply line of the power supply voltage _VCC . The cathode of the light emitting element 16 is grounded.
That is, the light emitting element 16 is connected to the drive circuit 15 so that it emits light when the low level drive signal DR ₁ is output from the control circuit 14.

The drive circuit 18 includes a pnp transistor Q ₂ and resistance elements R ₃ and R ₄ .

The drive circuit 19 includes a pnp type transistor Q ₃ and a resistance element R ₆ .
The base of the transistor Q ₃ is connected to the output line of the drive signal DR ₃ of the control circuit 14 via the resistance element R ₆ , the emitter is connected to the supply line of the power supply voltage _VCC , and the collector is the power supply terminal of the amplifier 20. It is connected.
For example, when the drive signal DR ₃ is output at a low level from the control circuit 14 at every positive time, the drive circuit 19 turns on the transistor Q ₃ and supplies drive power to the amplifier 20.

  The amplifier 20 receives driving power from the drive circuit 19 and receives an alarm signal S1045 from the control circuit 14 and causes the speaker 21 to ring.

FIG. 3 shows a block configuration of a standard radio signal receiving system 11 according to the time information receiving apparatus and the radio-controlled timepiece of the present invention.
The standard radio wave signal receiving system 11 includes an antenna 11a and a long wave receiving circuit 11b. The long wave receiving circuit 11b includes a tuning circuit 111, an RF (Radio Frequency) amplifier 112, a filter circuit 113, a post-stage (post) amplifier 114, a detection circuit. The circuit 115 and the waveform shaping circuit 116 are included.

  The antenna 11a is configured by a bar antenna, for example, and receives a standard radio wave (40 KHz or 60 KHz) including time information.

  In the tuning circuit 111, a coil and a capacitor are connected in parallel, and the capacitance value is changed by switching the capacitor to tune to a standard radio wave frequency of 40 KHz or 60 KHz, and attenuate other frequencies.

The RF amplifier 112 uses a small signal amplifying circuit to amplify an input signal and F (Noise Figure) is improved, and a good S / N (Signal / Noise) ratio is obtained.
The RF amplifier 112 constitutes an AGC amplifier that can automatically vary the amplification degree according to the level of the input signal by an AGC (Automatic Gain Control) control signal. For example, when the input signal is large, the gain of the RF amplifier 112 is lowered to lower the level of the output signal. When the level of the input signal is small, the gain of the RF amplifier 112 is raised to increase the level of the output signal. To do.

  The filter circuit 113 is a B.C. P. F (Band Pass Filter) is configured, and frequencies other than the pass frequency band are sharply attenuated. As a result, the filter circuit 113 passes only the reception frequency and attenuates or removes other signals, noise, and the like. Further, the filter circuit 113 can be configured using other filters in addition to the crystal filter.

  The post-stage amplifier 114 is composed of an amplifier circuit with a large dynamic range, further amplifies the received signal (standard radio wave) selected by the filter circuit 113, and increases the signal amplitude.

  For example, an envelope detection circuit is used as the detection circuit 115 and is amplified by the post-stage amplifier 114 to detect the received signal. The detection circuit 115 is provided with a rectifier circuit (not shown), and a DC voltage output from the rectifier circuit is fed back to the RF amplifier 112 as an AGC control voltage. The gain of the RF amplifier 112 is automatically controlled according to the level of this AGC control voltage.

  For example, the waveform shaping circuit 116 detects and holds the peak voltage and the bottom voltage of the detection signal detected by the detection circuit 115, and uses the average value of the peak voltage and the bottom voltage as a threshold value. Then, the detection signal detected by the detection circuit 115 is compared with the above-mentioned threshold value. When the detection signal is larger than the threshold value, an “H” level pulse is generated. When the detection signal is smaller than the threshold value, an “L” level pulse is generated. appear. As a result, rectangular pulses of “1” and “0” levels are output from the waveform shaping circuit 116 to the control circuit 14 (see FIG. 2) at the subsequent stage as time information (TCO).

Next, the operation of the standard radio signal receiving system 11 will be described.
The antenna 11a receives a long wave (40 kHz, 60 KHz) standard time radio wave having the format shown in FIG.
A standard time radio wave (reception signal) received by the antenna 11a is input to the tuning circuit 111, and for example, a tuning frequency of 40 KHz is selected, and other signals are attenuated.

  The received signal selected by the tuning circuit 111 is supplied to the RF amplifier 112. When the received signal is small (or when the electric field strength is weak), the gain of the RF amplifier 112 is increased by the AGC voltage, while the received signal is large. Controls the signal level of the output signal by lowering the gain by the AGC voltage.

  The reception signal amplified by the RF amplifier 112 is input to the filter circuit 113, and only the reception signal of 40 KHz is selected, and the signal or noise other than the band is attenuated. The received signal selected by the filter circuit 113 is further supplied to the post-stage amplifier 114 to amplify the amplitude of the output voltage to a level where it can be detected.

  The reception signal amplified by the post-stage amplifier 114 is subjected to envelope detection by the detection circuit 115 to generate a pulse signal. This pulse signal is supplied to the subsequent waveform shaping circuit 116, and the peak voltage and the bottom voltage are held. Further, an average value is obtained from the bottom voltage and the peak voltage and set as a threshold voltage.

  The pulse signal input to the waveform shaping circuit 116 is compared with a threshold voltage. When the pulse signal is higher than the threshold voltage, an “H” level voltage is output, and when the pulse signal is lower than the threshold voltage, an “L” level voltage is output. Is output. That is, a rectangular pulse is generated according to the high and low waveform voltage of the pulse signal as compared with the threshold voltage, and is derived as a TCO signal.

  Next, FIG. 4 shows a block configuration of the synchronization signal processing circuit 200. The synchronization signal processing circuit 200 is connected to the subsequent stage of the waveform shaping circuit 116 and detects (or determines) the synchronization signal of the TCO signal.

  The synchronization signal processing circuit 200 includes a plurality of data 1 acquisition circuits 201 to data 3 acquisition circuits 203, falling cycle determination circuits 205 to 207, a second synchronization data storage circuit 210, and a second synchronization processing circuit 220. Here, an example in which the data acquisition circuit and the falling period determination circuits 205 to 207 are each composed of three is shown, but the number of these is not limited.

The data 1 acquisition circuit 201 to the data 3 acquisition circuit 203 include, for example, a counter circuit that performs a count operation in synchronization with the falling of the waveform, the falling time (data) at the start of the TCO signal, and the 1 second cycle Time (data) such as a falling edge of a pulse waveform existing within (or one cycle period) is measured. In the following example, a configuration and operation for capturing time at a falling edge will be described.
Further, as will be described later, the data 1 acquisition circuit 201 to the data 3 acquisition circuit 203 shown in FIG. 4 sequentially captures the time related to the pulse generated in the time series of the TCO signal for each different cycle. For example, as shown in FIG. 5, the data 1 acquisition circuit 201 starts acquiring data from the falling time at time t1, the data 2 acquisition circuit 202 starts acquiring data from the falling time at time t3, The data 3 acquisition circuit 203 starts data acquisition from the falling time at time t5. Furthermore, the data 1 acquisition circuit 201 acquires time t7, the data 2 acquisition circuit 202 acquires time t9, and repeats the same operation as.

  The fall period determination circuit 205 (˜207) determines the fall time of each pulse based on the fall time data of the pulse waveform of the TCO signal supplied from the data 1 acquisition circuit 201 (˜data 3 acquisition circuit 203). The period is calculated. This process can be performed by software using a microcomputer or the like, but the period can also be determined using hardware.

The falling period determination circuits 205 to 207 determine whether or not the falling period of the pulse waveform is a one second period. Specifically, when the received radio wave is weak due to noise, the 1-second period (1 cycle) fluctuates. Therefore, the 1-second period is determined by adding a predetermined allowable range to 1 second. For example, if the allowable range is 200 ms (milliseconds), the range from 0.8 second to 1.2 seconds is defined as a specified value, and the pulse at the falling time existing in the range of the specified value is measured. The start time in each 1-second period (1 cycle period) is determined from the pulse, and a 1-second period synchronization signal is set.
Further, when there are a plurality of pulses in one cycle period due to noise or the like, the falling time of the first pulse is measured from the start time, the period from the start time is measured, and this period is 0.8 to 1.. It is determined whether it is within the specified value of 2 seconds. As a result of the determination, if this specified value is satisfied, the start time is regarded as a synchronization signal with a period of 1 second, assuming that the period is 1 second. If the determination result does not satisfy the specified value, then the fall time of the second pulse is measured, the fall time of the second pulse is measured from the start time, and the period from the start time is the above-mentioned specified value. It is calculated whether or not the value is within the value, and it is determined whether or not the start time is a start time with a cycle of 1 second according to the result.

Further, when there are, for example, two pulses in one cycle period due to noise or the like, the start time is reset to the falling time of the pulse generated by the first noise, and similar measurement and determination operations are performed.
If there is further noise, the third pulse performs the same operation with the fall time as the start time.
Such an operation is repeated in each of the falling period determination circuits 205 to 207 to determine the start time. Further details will be described later.

As shown in FIG. 10, if only one data acquisition circuit and one falling period determination circuit are provided, a buffer circuit that accumulates data when determining a start time of a 1 second period from a repetition period of a predetermined second. (Capacity) and the like are required in comparison with the configuration of FIG. In addition, if there is only one data acquisition circuit and one falling period determination circuit, it takes time for data acquisition and determination processing.
On the other hand, as shown in FIG. 4, a plurality of data 1 acquisition circuits 201 to data 3 acquisition circuits 203 and a plurality of falling period determination circuits 205 to 207 corresponding thereto are provided in parallel. Since the data acquisition circuit and the falling period determination circuit are combined so as to acquire the falling times of different one-second periods in sequence, data acquisition for a predetermined second (for example, 8 seconds) and determination processing for each of these seconds The processing time can be shortened comprehensively.

  Next, data within a specified value is input to the second synchronization data storage circuit 210 from the above-described falling period determination circuits 205 to 207, and stored in the storage means. The storage means includes a RAM of a semiconductor device, but is not necessarily limited thereto.

The second synchronization processing circuit 220 includes, for example, a microcomputer (not shown), a control program for controlling the microcomputer, an application program for performing second synchronization processing, and the like. Alternatively, it may be configured by hardware other than this, and may be configured by combining hardware and software.
The second synchronization processing circuit 220 determines the second synchronization signal by performing data processing using the data output from the second synchronization data storage circuit 210 by the means described above.

Next, the specific operation of the synchronization signal processing circuit 200 will be described with reference to the waveform diagrams of FIGS.
Here, in order to simplify the description, a configuration example in which there are three data acquisition circuits and three corresponding falling cycle determination circuits will be described.
When the TCO signal shown in FIG. 5 is supplied to the synchronization signal processing circuit 200, the data 1 acquisition circuit 201 operates at the falling time at time t1 and starts acquiring time data. At time t3, the data 2 acquisition circuit 202 operates and starts acquiring time data. Further, at time t5, the data 3 acquisition circuit 203 operates to start acquisition of time data. Similarly, at time t7, the data 1 acquisition circuit 201 starts acquiring time data, at time t9, the data 2 acquisition circuit 202 starts acquiring time data, and further, the data according to the fall of the waveform of the TCO signal. 3 acquisition circuit 203...

Next, the operation of each data 1 acquisition circuit 201 to data 3 acquisition circuit 203 will be described.
For example, it is assumed that the TCO signal shown in FIG. The waveform of the TCO signal falls at time t1 as shown in FIG. 5, and a pulse is generated at times t2 and t3 due to noise or the like, and falls at time t5 and shows a period of approximately 1S (seconds).
Data acquisition is started with time t1 as a tentative first start time. Data at time t1, time data at times t2 and t3, and time data at falling time t5 of the pulse waveform are acquired.
In the data 2 acquisition circuit 202 and the data 3 acquisition circuit 203, the same data acquisition operation is performed in each acquisition period.
In addition to this, for example, the data 1 acquisition circuit 201 relates to the acquisition timing of the falling time data t1 to t5, and takes in the data at time t3 after the period determination processing at time t1 and time t2 is completed. After the determination, the time data at time t4 is fetched and the period determination process is performed, and so on. The same applies to the other data 2 acquisition circuit 202 and data 3 acquisition circuit 203.
Therefore, the timing of fetching time data in each cycle of each data 1 acquisition circuit 201 to data 3 acquisition circuit 203 depends on the operating speed, processing speed, etc. of the falling period determination circuits 205 to 207 connected to the subsequent stage. Since it can be changed, it is not limited to these methods.

  The falling cycle determination circuit 205 determines whether each period in each time data is within a predetermined specified value from time t1 using the time data t1, t2, t3, t5 supplied from the data 1 acquisition circuit 201. To do. As shown in FIGS. 5 and 8, the 1-second period of the TCO signal fluctuates due to the signal level and noise of the received signal, or noise is generated within a period of about 1 second. Spread and judge. For example, as described above, when the allowable range is 200 ms (milliseconds), the specified value of approximately 1 second is set from 0.8 seconds to 1.2 seconds.

For example, in FIG. 6B, the falling period determination circuit 205 uses the time t1 as the first start time, and obtains the period from the time t1 to the falling time t2 of the next pulse. It is determined whether or not the period from the time t1 to t2 is within the specified value of 0.8 seconds to 1.2 seconds described above, and if it is within the specified value, it is regarded as valid data. . If the obtained data is 0.8 seconds or less or 1.2 seconds or more, it is not valid data, so this data is discarded and the next operation is started.
A period from time t1 to time t3 is obtained, and it is determined whether or not it is within a specified value of 0.8 seconds to 1.2 seconds. If it is determined that the determination result is within the specified value, it is considered appropriate. If the determination result is outside the specified value, the data is discarded, and the next operation is performed. The determination process from time t1 to time t4 is performed, and further, time t1. From time to time t5, the same determination process is performed.

Further, the falling cycle determination circuit 205 performs the same falling cycle determination operation by replacing the start time of the TCO signal described above with t1 and using the time t2 as a new start time.
As shown in FIG. 6C, the time t2 is set as the second start time, and the period from this time t2 to the falling time t3 of the next pulse is obtained. It is determined whether or not the period from time t2 to time t3 is within the specified value of 0.8 seconds to 1.2 seconds described above. If it is within this specified value, it is regarded as valid data, and if the obtained data is 0.8 seconds or less or 1.2 seconds or more, it is not valid data. Move to operation.
A period from time t2 to time t4 is obtained, and it is determined whether or not it is within a specified value of 0.8 seconds to 1.2 seconds. If it is determined that the determination result is within the above-mentioned range, the data is discarded if it is within or outside the specified value, and the next operation is performed to obtain the period from time t2 to time t5. Is determined to be valid.
When data at times 4 and t5 are discarded, a period between time t2 and time t6 is further obtained. If this period is within a specified value of, for example, 0.8 to 1.2 seconds, it is regarded as valid data. Secured. However, if the period between time t2 and time t6 is 1.2 seconds or longer, this data is determined to be invalid and discarded.

In FIG. 6A, since a pulse due to noise is also generated at time t3, the falling cycle determination operation is further performed using time t3 as the start time.
As shown in FIG. 6D, the start time is changed from time t0 to t3. The time t3 is set as the third start time, and the period from the time t3 to the falling time t4 of the next pulse is obtained. It is determined whether or not the period from the time t3 to t4 is within the specified value of 0.8 seconds to 1.2 seconds described above, and if it is within this range, it is regarded as valid data. If the obtained data is less than the specified value of 0.8 seconds or less or 1.2 seconds, it is not valid data, so this data is discarded and the next operation is started. Next, a period from time t3 to time t5 is obtained, and it is determined whether or not it is within a specified value of 0.8 seconds to 1.2 seconds. It is considered that the determination result is valid if it is within the above-mentioned specified value. If it is outside the specified value, this data is discarded, and the next operation is performed to obtain the period from time t3 to time t6. Is determined to be valid.

Further, in the operation of the falling cycle determination circuit 205, when data acquisition starts at time t1, there is no data whose falling cycle is within the specified value of 0.8 to 1.2 seconds. Then, the control signal (falling cycle NG) is output again to the data 1 acquisition circuit 201 so that the data 1 acquisition circuit 201 can start acquiring data at time t7 of the TCO signal in FIG.
The above-described operation is also performed in the data 2 acquisition circuit 202 and the falling cycle determination circuit 206, and also in the data 3 acquisition circuit 203 and the falling cycle determination circuit 207, and is valid as a 1 second cycle from the falling cycle determination circuits 206 and 207. Time data is output.

  The falling cycle data relating to the time t1 or t7 shown in FIG. 5 from the falling cycle determining circuit 205, and the falling cycle data relating to the time t3 or t9 shown in FIG. 5 are output from the determination circuit 205 and are stored in the second synchronization data storage circuit 210, respectively.

Data obtained from times t1, t3, t5, t7, and t9 stored in the second synchronization data storage circuit 210 is supplied to the second synchronization processing circuit 220, and a second synchronization signal is obtained.
For example, the second synchronization signal is obtained from the data output from the falling period determination circuit 205, from the data output from the falling period determination circuit 206, and from the data output from the falling period determination circuit 207, respectively.
If the cycle determination data at the fall time t1 is invalid in the fall cycle determination circuit 205, the fall cycle data at time t7 is output as valid data, and other than that, the fall cycle determination circuit 206 at the time t3. If the falling cycle data is output and the falling cycle data at time t5 is output from the falling cycle determination circuit 207, it is necessary to rearrange these cycle data. In other cases, the periodic data is rearranged so as to follow the elapsed time.

  As described above, the data 1 acquisition circuit 201 to the data 3 acquisition circuit 203 and the corresponding falling cycle determination circuits 205 to 207 are provided in parallel, and the pulse position of the data acquisition in the repetition period of about 1 second of the TCO signal. By sequentially setting to different times, parallel processing is performed, so that the determination time can be shortened.

  As described above, the synchronization signal processing circuit is provided in the control circuit of the time information receiving device and the radio-controlled timepiece, and the outer synchronization signal processing circuit includes a plurality of data acquisition circuits and a plurality of falling period determination circuits corresponding thereto, Period determination means, second synchronization data storage circuit, second synchronization processing circuit is provided, time data is sequentially acquired by the data acquisition circuit in different cycles with the passage of time, the falling period of each cycle is determined and stored, By performing the second synchronization processing using the stored data, it is possible to reduce the number of processing programs for synchronization detection compared to the prior art and to reduce the processing time for the synchronization detection. Even when the start waveform of the TCO signal is unstable due to noise or the like, an accurate synchronization signal can be obtained.

  In a time information receiving apparatus and a radio-controlled timepiece that receive a standard time radio signal according to the present invention and corrects the time, a receiving circuit that receives the standard time radio signal, processes the received signal, and outputs time information A plurality of data acquisition circuits corresponding to the long wave reception circuit 11 of the standard radio wave signal reception system and capturing the edges of the waveform of the time information derived from the reception circuit are a data 1 acquisition circuit 201 to a data 3 acquisition circuit 203. A plurality of period determination circuits provided corresponding to the data acquisition circuits and determining the period from the time data of the edges supplied from the data acquisition circuits are provided in the falling period determination circuits 205 to 207, respectively. Correspondingly, a synchronization processing circuit for obtaining a synchronization signal from the period data determined by the plurality of period determination circuits is a second synchronization data storage circuit 210 and a second synchronization processing circuit 22. Corresponding to.

FIG. 1 is a front view showing the appearance of the radio-controlled timepiece. FIG. 2 is a block diagram showing a signal processing system circuit of the radio-controlled timepiece. FIG. 3 is a block diagram of a long wave receiving circuit relating to the present time receiving apparatus and the radio-controlled timepiece. FIG. 4 is a block diagram of the synchronization signal processing circuit. FIG. 5 is a diagram illustrating a waveform of the time information signal. FIG. 6 is a waveform diagram of the time information signal when noise is present. FIG. 7 is a waveform diagram of the modulated received signal. FIG. 8 is a diagram showing time data of one frame. FIG. 9 is a waveform diagram of time information when the reception state of the radio-controlled timepiece changes. FIG. 10 is a circuit block diagram of a radio-controlled timepiece as another conventional example. FIG. 11 is a waveform diagram of a time information signal when noise or the like exists within a one second period.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Signal processing system circuit, 11 ... Standard radio wave signal receiving system, 11a, 310 ... Antenna, 11b, 320 ... Long wave receiving circuit, 14 ... Control circuit, 20 ... Amplifier, 21 ... Speaker, 100 ... Radio wave correction clock, 103 ... Second hand, 104 ... minute hand, 105 ... hour hand, 111 ... tuning circuit, 112 ... RF amplifier, 113 ... filter circuit, 114 ... latter stage amplifier, 115 ... detection circuit, 116 ... waveform shaping circuit, 142 ... light emitting element, 144 ... light receiving element , 160 ... optical sensor, 200 ... synchronization signal processing circuit, 201 to 203, 331 ... data acquisition circuit, 205 to 207 ... falling period determination circuit, 210 ... data storage circuit for second synchronization, 220, 333 ... second synchronization processing circuit 332: Data storage circuit.

Claims (4)

In the time information receiver that receives the standard time radio signal and corrects the time,
A receiving circuit for receiving the standard time radio wave signal and processing the received signal to derive time information;
A plurality of data acquisition circuits for sequentially capturing the time of successive rising edges or successive falling edges of the waveform with the passage of time of the time information derived from the reception circuit;
A plurality of period determination circuits which are provided in parallel corresponding to the data acquisition circuits , and determine the period in parallel from the time data of the edges supplied from the data acquisition circuits;
A synchronization processing circuit for obtaining a synchronization signal from the period data determined by the plurality of period determination circuits;
A time information receiving device. The period determination circuit sequentially obtains a period from an arbitrary falling or rising edge of the waveform of the time information to a falling or falling edge of each waveform within a predetermined period, and the period of each waveform is within a predetermined value The time information receiving device according to claim 1, wherein the time information is determined to be valid data and invalid data is determined when the value is not a predetermined value. In the radio correction clock that receives the standard time radio signal and corrects the time,
A receiving circuit for receiving the standard time radio wave signal and processing the received signal to derive time information;
A plurality of data acquisition circuits for sequentially capturing the time of successive rising edges or successive falling edges of the waveform with the passage of time of the time information derived from the reception circuit;
A plurality of period determination circuits which are provided in parallel corresponding to the data acquisition circuits , and determine the period in parallel from the time data of the edges supplied from the data acquisition circuits;
A synchronization processing circuit for obtaining a synchronization signal from the period data determined by the plurality of period determination circuits;
An electric wave correction clock. The period determination circuit sequentially obtains a period from an arbitrary falling or rising edge of the waveform of the time information to a falling or falling edge of each waveform within a predetermined period, and the period of each waveform is within a predetermined value The radio-controlled timepiece according to claim 3, wherein the time-corrected data is determined to be invalid data and the invalid data is determined when other than a predetermined value.

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