JP4984226B2 - Pulse width modulation circuit - Google Patents

Description

  In the present invention, the pulse width modulation circuit is used for voltage control in a switching regulator (DC-DC converter, AC-DC converter), inverter (DC-AC conversion circuit), digital amplifier (class D amplifier), or the like. The present invention relates to a modulation circuit and a switching regulator to which the pulse width modulation circuit is applied.

  A triangular wave generating means for generating a triangular wave signal (PWM carrier signal) having a constant amplitude by charging and discharging a capacitor by a switching element; a comparing means for generating a pulse width modulation signal by comparing the triangular wave signal and the modulated signal; There has been proposed a pulse width modulation circuit including current switching means for discretely changing the charging / discharging current of the capacitor at a timing synchronized with a triangular wave signal (accordingly, the period of the triangular wave also changes discretely).

When the period of the triangular wave signal is fixed, when applied to a switching regulator (DC-DC converter) or the like, the switching noise power contained in the output voltage concentrates on a specific frequency, resulting in a high peak. A noise spectrum of values is generated.
On the other hand, according to the above pulse width modulation circuit, the period of the triangular wave signal is discretely changed, so that the peak value of the noise spectrum is suppressed (for example, see Patent Document 1). .

On the other hand, a switching regulator that switches a switching element by a pulse width modulation signal from a pulse width modulation circuit is connected to the peripheral device via a power supply line in order to supply its output as a power source to the peripheral device.
The output of the switching regulator includes switching noise having a period corresponding to the generation period of the triangular wave signal generated by the pulse width modulation circuit. Thus, conventionally, a technique for transmitting predetermined data from a switching regulator to the peripheral device using the switching noise has been proposed.

  In this technique, the pulse width modulation circuit is configured to be able to generate first and second triangular wave signals (which have different periods) corresponding to communication data “0” and “1”, respectively. The pulse width modulation circuit is controlled so that the first and second triangular wave signals are generated for a predetermined unit time corresponding to the data “0” and “1”, respectively. In the peripheral device on the receiving side, the data is demodulated based on the number of received switching noises in the unit time (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 2004-266780 Japanese Patent Laid-Open No. 2005-33534

Incidentally, in Patent Document 2, since the generation period of the triangular wave signal corresponding to data “0” and “1” is fixed, the unit time is measured by counting the number of generated triangular wave signals. Can do. That is, when the unit time is T ₀ and the generation periods of the triangular wave signals corresponding to the data “0” and “1” are T ₁ and T ₂ , the count value is (T ₀ / T ₁₎ is the unit time T ₀ since it is now measured, also the unit time T ₀ since the count value becomes (T ₀ / T ₂₎ at the time of transmission of the data "1" is measured The

On the other hand, in the pulse width modulation circuit according to Patent Document 1, since the period of the triangular wave signal is discretely changed (frequency spread), the period cannot be an absolute temporal reference, For this reason, it is difficult to use the period for measuring the unit time T ₀ .
Therefore, when the pulse width modulation circuit according to Patent Document 1 is applied to the switching regulator of Patent Document 2 having a data transmission function, a dedicated time measuring means for measuring the unit time T ₀ is provided. However, this leads to a complicated configuration and an increase in cost.

Accordingly, an object of the present invention is to provide a pulse width modulation circuit capable of utilizing the period as a temporal reference even though the period of the triangular wave signal is discretely changed.
Another object of the present invention is to provide a switching regulator to which the pulse width modulation circuit having the above function is applied.

The pulse width modulation circuit according to the present invention comprises a triangular wave generating means for generating a triangular wave signal having a constant amplitude having a period defined by the charging / discharging current of the capacitor, and the charging / discharging current of the capacitor at a timing synchronized with the triangular wave signal. Current modulation means for discretely changing from a reference current value; and comparison means for generating a pulse width modulation signal by comparing the triangular wave signal and the modulated signal. The current modulation means allocates the discrete change component having an equal value to one and the other two periods of the two continuous periods of the triangular wave signal, and assigns the discrete change component to the one and the other periods, respectively. to the reference current value Ru is configured to add and subtract. Two types of reference current values are set, and these two types of reference current values are selected and designated.

  Pseudo random number generating means for generating pseudo random numbers at a timing synchronized with the triangular wave signal can be provided. In this case, the current modulation means is configured to set a discrete change component of the charge / discharge current based on the pseudorandom number.

  The current modulation means may include a plurality of switches that are selectively turned on and off based on the pseudo random number and a plurality of current sources that can be selected by these switches. In this current modulation means, the output current of each current source selected by each switch is added, and the added current is set as a discrete change component of the charge / discharge current.

It is possible to construct a switching regulator with a pre-Symbol pulse width modulation circuit as a voltage control means. In this switching regulator, the error signal becomes the modulated signal of the pulse width modulation circuit.

According to the present invention, the charge / discharge current of the capacitor that defines the period of the triangular wave signal is formed from the reference current value and the discrete change component. Then, a discrete change component having an equal value is assigned to one and the other two cycles of the triangular wave signal, and the discrete change component is added to the reference current value in each of the one and the other cycles. And subtracted. Therefore, although the period of the triangular wave signal is discretely changed, the sum of the periods of the continuous triangular wave signal becomes twice the period of the triangular wave signal corresponding to the reference current value, and the next continuous triangular wave Similarly, the sum of the signal periods is twice the period of the triangular wave signal corresponding to the reference current value.
That is, when the period of the triangular wave signal corresponding to the reference current value is regarded as one unit, and the sum of the periods of the continuous triangular wave signal is regarded as one unit, the two coincide in time. Therefore, although the periods of the continuous triangular wave signals are different from each other, their sum has a function as a temporal reference.

  Therefore, for example, if the pulse width modulation circuit according to the present invention is applied to the voltage control of a switching regulator having a communication function using switching noise, in addition to the effect of suppressing the noise spectrum of a high peak value, Therefore, there is an effect that communication can be performed without providing a dedicated time management means (time measuring means). Moreover, according to the present invention, a switching regulator having the above functions can be provided.

FIG. 1 is a block diagram showing a switching regulator (DC-DC converter) to which a pulse width modulation circuit according to the present invention is applied.
The switching regulator includes a pulse width modulation circuit 10, the output voltage feedback circuit 20, drive circuit 30 includes semiconductor switches 40a, 40b, a reactor L and capacitor C, by switching the input voltage V _in the semiconductor switches 40a, by 40b, The voltage V _out corresponding to the target value defined by the reference voltage V _ref is output.

The pulse width modulation circuit 10 compares a triangular wave generator 11 that generates a triangular wave signal V _osc with a constant amplitude, and the triangular wave signal V _osc and the error voltage signal V _FB that is the output of the output voltage feedback circuit 20 to perform pulse width modulation. A comparator 12 that generates a signal, a current modulation circuit 13, and a pseudo-random number generation circuit 14 are provided. The error voltage signal V _FB corresponds to V _ref −k · V _out (where k is a voltage dividing ratio when the voltage V _out is divided and detected, and k = 1 when not divided). Then, it becomes a modulated signal in the pulse width modulation circuit 10.

FIG. 2 is a circuit diagram showing a configuration example of the triangular wave generator 11 and the current modulation circuit 13.
The triangular wave generator 11 includes a timing capacitor C _T , semiconductor switches 111 a (pMOS transistors) and 111 b (nMOS transistors) for switching charge / discharge paths of the timing capacitor C _T , a capacitor charging current source 112 a, a capacitor a current source 112b for discharging the timing capacitor C _T pin voltage respectively upper threshold voltage V _OU of the comparator 113 and 114 to be compared with the lower threshold voltage V _OL, and a flip-flop 114.

Here, the operation of the triangular wave generator 11 will be described with a state where the relationship of V _osc <V _OU is established and the logic level of the output Q of the flip-flop 114 is “L” as an initial state.
In this initial state, the semiconductor switch 111b is turned off and the semiconductor switch 111a is turned on, and the timing capacitor C _T is charged with the current K ₁ · I _ref (K ₁ is a constant) of the current source 111a. As shown, the output voltage V _osc rises at a constant rate of change. When the voltage V _osc rises and exceeds the upper threshold voltage V _OU , the comparator 113 sets the flip-flop 114, so that the logic level of the output Q of the flip-flop 114 is switched to “H”. Accordingly, since the semiconductor switch 111a is turned on the semiconductor switch 111b is turns off, the current K ₂ · I _ref of timing capacitor C _T is the current source 112b (K ₂ is a constant, K ₂ = K ₁ in this example) by As a result, the output voltage V _osc falls at a constant rate of change.
When the voltage V _osc drops and falls below the lower threshold voltage V _OL , the flip-flop 114 is reset, and the logic level of the output Q is switched to “L”. The triangular wave generator 11 generates a triangular wave signal V _osc as shown by repeating such an operation.

Next, the current modulation circuit 13 will be described. The oscillation period of the triangular wave generator 11 is determined by the output currents K ₁ I _ref and K ₂ I _ref of the current sources 112a and 112b, which are charging / discharging currents of the timing capacitor C _T. Current modulation circuit 13, the current K ₁ I _ref, be one that generates a current I _ref in K ₂ I _ref, the timing capacitor C _T of the charge and discharge current minimum standards become the magnitude of the current I _ref1 (or A constant current source 131 that outputs I _ref1 ′), a D / A converter 132 that converts an n-bit digital modulation signal into an analog current output I _ref2 , and a decoder 133.
The constant current source 131 is configured to generate two types of constant currents I _ref1 and I _ref1 ′, and any one of these currents is designated based on external data input to an input bit m described later. The

D / A converter 132, a plurality of switches S ₁ to be selectively opened or short circuit based on the digital modulated signal of n bits outputted from the decoder 133, S _1, and · · · S _n, these switches S _1, S _2, is selected by · · · S _n, different constant current 1I _SS of each ^{_{size, 2I SS, ···, 2 n}} I SS (2 0 I SS, 2 1 I SS, ··· , 2 ⁿ I _SS) a plurality of constant current sources for outputting 134-1 and 134-2 are constituted by a · · · 134-n, the switches S _1, S _2, the selection operation of the · · · S _n A current I _ref2 obtained by adding a plurality of constant currents to be determined is output.
The output current I _ref2 of the D / A converter 132 is added to the output current I _ref1 (or I _ref1 ′) of the constant current source 131 to form the current I _ref . The currents K ₁ I _ref and K ₂ I _ref are generated from the current I _ref by a current mirror circuit (not shown).

The period of the triangular wave signal V _osc output from the triangular wave generator 11 coincides with the period of the clock signal output from the flip-flop 114. Here, if the reference period of the clock signal is T ₁ shown in FIG. 4A, the present embodiment always follows the clock signal of the period (T ₁ −Δt _i ) shown in FIG. 4B. The clock signal having the period (T ₁ + Δt _i ) shown in (c) is continued, or the clock signal having the period (T ₁ −Δt _i ) is always followed by the clock signal having the period (T ₁ + Δt _i ). Composed. With this configuration, the total period of two consecutive clock signals is always 2T ₁ .

On the other hand, in the present embodiment, since the communication data to be described later is formed, the clock signal of the cycle (T ₂ −Δt _i ) shown in FIG. 4E and the cycle shown in FIG. T ₂ + Δt _i ) is also output. These clock signals are also generated so other follows the one, therefore, the period of the signals to be continuously always becomes 2T _2.
Here, time Δt _i is a periodic spread component of the clock signal. The periodic spread components Δt ₁ , Δt ₂ ,..., Δt _i ,... Are preferably close to random numbers, and therefore, in this embodiment, a pseudo-random number generation circuit 14 (FIG. 5) described later is used. ) To form a periodic diffusion component close to a random number.

The period of the triangular wave signal V _osc , that is, the period of the clock signal output from the flip-flop 114 is such that the both-ends voltage (integrated voltage) due to constant current charging / discharging of the timing capacitor C _T reaches the threshold value (V _OU , V _OL ). Therefore, it is expressed as K (constant) / constant current value.
Here, if the constant current value that gives the cycle T _j (j = 1 or 2) is I _j and the constant current value that gives the cycle T _j -Δt is I _j + ΔI, 1 / (1-α) = 1 + α is applied, the constant current value that gives the cycle T _j −kΔt is I _j + kΔI, and the constant current value that gives the cycle T _j + kΔt is I _j −kΔI. (K is an integer).

In the D / A converter 132 shown in FIG. 2, a constant current value of I _ss to 2 ⁿ I _ss can be selected by opening and closing the switches S _{1 to} S _n .
In the current modulation circuit 13, (I _ref1 +2 ⁿ I _ss ) is associated as the current value I _ref for defining the basic period T _1, and the current value I for defining the basic period T _{2. A} current value (I _ref2 +2 ⁿ I _ss ) is associated with _ref .
Accordingly, the period of the clock signal output from the flip-flop 114 is set to (T ₁ + kΔt ₀₁ ) by subtracting the current value k × I _ss from the current value (I _ref1 +2 ⁿ I _ss ), By adding the constant current value k × I _ss to the current value (I _ref1 +2 ⁿ I _ss ), the cycle of the clock signal is set to (T ₁ −kΔt ₀₁ ). Where Δt ₀₁ = C _T · (V _OU −V _OL ) (1 / K ₁ + 1 / K ₂ ) ((1 / (I _ref1 +2 ⁿ I _ss ) −1 / (I _ref1 +2 ⁿ I _ss + I _ss )) = 2C _T · (V _OU −V _OL ) ((1 / (I _ref1 +2 ⁿ I _ss ) −1 / (I _ref1 + (2 ⁿ +1) I _ss )) / K ₁ . The period (T ₁ −kΔt ₀₁ ) and (T ₁ + kΔt ₀₁ ) are respectively the period (T ₁ −Δt _i ) shown in FIG. 4B and (T ₁ + Δt shown in FIG. 4C). _i ).

Similarly, the period of the clock signal is set to (T ₂ + kΔt ₀₂ ) by subtracting the current value k × I _ss from the current value (I _ref2 +2 ⁿ I _ss ), and the current value (I By adding the constant current value k × I _ss to ( _ref 2 +2 ⁿ I _ss ), the cycle of the clock signal is set to (T ₂ −kΔt ₀₂ ). Here, Δt ₀₂ = 2C _T · (V _OU −V _OL ) ((1 / (I _ref1 ′ +2 ⁿ I _ss ) −1 / (I _ref1 ′ + (2 ⁿ +1) I _ss )) / K ₁ The periods (T ₂ −kΔt ₀₂ ) and (T ₂ + kΔt ₀₂ ) are respectively represented by the periods (T ₂ −Δt _i ) and (f) shown in FIG. This corresponds to (T ₂ + Δt _i ).

The pseudo-random number generation circuit 14 is constituted by, for example, a linear feedback shift register circuit as shown in FIG. This linear feedback shift register circuit (LFSR) includes D flip-flops D-FF _{1 to} D-FF _n-1 cascaded in (n−1) stages (6 stages in the example shown in FIG. 5), exclusive logic A sum circuit XOR, and generates (n−1) -bit pseudorandom numbers r _{1 to} r _n-1 (M-sequence code) as digital modulation data.
The output of the linear feedback shift register circuit is supplied to the decoder 133 in order to change k of the current value k × I _ss according to the pseudo random numbers r _{1 to} r _n−1 . This linear feedback shift register circuit performs a shift operation by an output QB (inverted signal of output Q) of the D flip-flop 115 described later triggered by the output of the D flip-flop 114.

Hereinafter, the operation of the present switching regulator will be described.
The current modulation circuit 13 has bits 1 to n and a bit m as digital input bits. Here, assuming that the number of bits n of the D / A converter 132 is 4, bits 1 to n of the digital input bits are 1 to 4. In the case of n = 4, as shown in FIG. 6, the input bits 1 to 3 are “variation range designation bits”, and the input bit n = 4 is “plus / minus (P / M) switching bit”. The input bit m is assigned as a basic period (T ₁ / T ₂ ) switching bit).

When the number of bits n of the D / A converter 132 is 4, the current value I _ref corresponding to the basic period T ₁ (I _ref1 +2 ⁿ I _ss ) and the current value I _ref corresponding to the basic period T ₂ Certain (I _ref1 '+2 ⁿ I _ss ) are set to (I _ref1 + 8I _ss ) and (I _ref1 ' + 8I _ss ), respectively.
The input bits 1 to 3 are given digital modulation data in accordance with the pseudo random number from the linear feedback shift register circuit which is the pseudo random number generation circuit 14 shown in FIG. 5, and the input bit n = 4 has the D flip-flop 115. Output Q is given.

Here, in the initial state, for example, digital modulation data “1”, “1”, “0” is given to input bits 1, 2, 3, and data “0” is inputted to input bits n = 4 and m, respectively. Is given.
At this time, the data “0” of the input bit n = 4 means a command “plus current” (the cycle is negatively reversed), and the data “0” of the input bit m is “basic” This means a command “select cycle T ₁ ”.

Therefore, the decoder 133 is a decimal number “1” × 2 ¹ + “1” × 2 ² + corresponding to the digital modulation data “1”, “1”, “0” input to the input bits 1, 2, 3. Based on “0” × 2 ³ = 3, data “1”, “1”, “0”, “1” such that the current to be added is 3I _ss are stored in each bit 1 of the D / A converter 132. Output to 2, 3, n (= 4).

Accordingly, the switches S ₁ , S ₂ and S _{4 of} the D / A converter 132 are turned on, and the constant current I _ref2 = I _ss + 2I _ss + 8I _ss = 11I _ss is output from the D / A converter 132. The reference constant current I _ref output from the current modulation circuit 13 is I _ref = (I _ref1 + I _ref2 ) = (I _ref1 + 11I _ss ) = (current value corresponding to the period T ₁ (I _ref1 + 8I _ss )) + _3.Iss .
As a result, the flip-flop 114 of the triangular wave generator 11 generates a clock signal (T ₁ −Δt _i ) having a period (T ₁ −Δt _i ) obtained by subtracting the time Δt _i corresponding to the current 3 · I _ss from the basic period T ₁ (FIG. 4B). )) Is output.

When the clock signal having the above cycle (T ₁ −Δt _i ) is output (that is, when the output Q of the D flip-flop 115 is “0”), the output QB, which is an inverted signal of the output Q of the flip-flop 114, is “ Since the D flip-flop 115 is triggered and its output Q is inverted to “1” at the timing of changing from “0” (L: LOW) to “1” (H: HIGH), the input bit n = 4 is set to “ The command “1” is input to “minus the current” (the cycle is reversed).
Therefore, the decoder 133 converts the data “1”, “0”, “1”, “0” such that the current to be minus is 3I _ss into each bit 1, 2, 3, n ( = 4).

Accordingly, the switches S ₁ and S _{3 of} the D / A converter 132 are turned on, and the constant current I _ref2 = I _ss + 4I _ss = 5I _ss is output from the D / A converter 132. The constant current I _ref output from the above is I _ref = (I _ref1 + I _ref2 ) = (I _ref1 + 5I _ss ) = (current value corresponding to the cycle T ₁ (I _ref1 + 8I _ss )) − 3I _ss .
As a result, from the flip-flop 114 of the triangular wave generator 11, a clock signal having a period (T ₁ + Δt _i ) obtained by adding a time Δt _i corresponding to the current 3 · I _ss from the basic period T ₁ (FIG. 4C). Reference) will be output.

Next, the case where the data of the input bit m of the current modulation circuit 13 is “1” in the above example will be described. In this case, since the constant current I _ref1 'is output from the constant current source 131, the reference constant current I _ref output from the current modulation circuit 13 is I _ref = (I _ref1 ' + I _ref2 ) = (I _ref1 '+ 11I _ss ) = (current value corresponding to period T ₂ (I _ref1 ′ + 8I _ss )) + 3 · I _ss As a result, a clock signal (see FIG. 4E) having a period (T ₂ −Δt _i ) is output from the flip-flop 114 of the triangular wave generator 11.

This clock signal triggers the D flip-flop 115 as in the case where the data of the input bit m is “0”. As a result, the data of the input bit n = 4 changes to “1”, so that the current modulation circuit 13 corresponds to I _ref = (I _ref1 ′ + I _ref2 ) = (I _ref1 ′ + 5I _ss ) = (period T ₂ . The current value (I _ref1 '+ 8I _ss ))-3 · I _ss is output, and as a result, the time Δt corresponding to the current 3 · I _ss in the basic period T ₂ from the flip-flop 114 of the triangular wave generator 11. clock signal _i plus the period (T ₂ + Δt _i) (see FIG. 4 (f)) so that is output.

When a clock signal having the period (T ₁ + Δt _i ) or period (T ₂ + Δt _i ) is output (that is, when the output Q of the D flip-flop 115 is “1”, the output QB of the flip-flop 114 is “ The output Q of the D flip-flop 115 changes to “0” at the timing of changing from “0” to “1”. As a result, the command “1” “decrease current” is input again to the input bit n = 4, and the output QB of the D flip-flop 115 changes from “0” to “1” to change the linear feedback shift. Since the register circuit is shifted, the same operation as described above is executed based on the new pseudo random number data added to the input bits 1, 2, and 3.

As described above, according to the present embodiment, since the clock signal having the period (T ₁ + Δt _i ) follows the clock signal having the period (T ₁ −Δt _i ), the total period of these clock signals is 2T _1. It becomes. Similarly, since the clock signal having the cycle (T ₂ + Δt _i ) follows the clock signal having the cycle (T ₂ −Δt _i ), the sum of the cycles of these two clock signals is 2T _2. .

The following table, input bits 1,2,3 of the current modulation circuit 13, n (= 4) and the logical value of m, the period T ₁ of the above clock signal, T _1-1 ~T _1-7, T ₁₊ The relationships between _{1 to} T _{1 + 7} and T ₂ , T _{2-1 to} T _2-7 , and T _{2 + 1 to} T _{2 + 7} are shown.

The data of the input bits 1, 2, and 3 in this table are given by the pseudo-random numbers r _{1 to} r _n−1 and define the discrete component of the current I _ref , that is, the periodic diffusion component Δt _i (period variation range). .
The periods T _1-i (i = 0 to 7) and T _{1 + i} correspond to the periods (T ₁ −Δt _i ) and (T ₁ + Δt _i ), respectively, and the periods T _2-i and T _{2 + i} corresponds to the periods (T ₂ −Δt _i ) and (T ₂ + Δt _i ), respectively. (As shown in paragraphs 0025 and 0026, Δt _i for T ₁ is different from Δt _i for T _2. )
The cycle T _1-i corresponds to the current I _ref1 + 8I _ss + i × I _ss = I _ref1 + (8 + i) I _ss , and the cycle T _{1 + i} is the current I _ref1 + 8I _ss −i × I _ss = This corresponds to I _ref1 + (8−i) I _ss .

As is clear from the above table, the data of the input bit n (= 4) is not only used as data for defining the current I _ref2 , but also switches between _adding and subtracting the periodic diffusion component Δt _i. It is also used as data for instructing. Here, it goes without saying that the relationship between the value of the input bit n (= 4) and the period spread component Δt _i plus or minus may be reversed from the above example.
The data of the input bits 1, 2, and 3 given by the pseudo-random numbers r _{1 to} r _n-1 are a clock signal having a period (T ₁ −Δt _i ) and a clock having a period (T ₁ + Δt _i ) following the clock signal. It is maintained during the signal generation period.

FIG. 7 shows an operation time chart. In FIG. 7, a triangular wave generator CLK is a clock signal (output QB) output from the flip-flop 114.
Both the reference clock (CLK) signal of the reference period T ₁ (indicated by 10) and the reference clock (CLK) signal of the reference period T ₂ (indicated by 20) are clocks without period modulation. Signal. This reference clock signal does not exist but is shown for ease of understanding the operation.
As described above, since the input data of the input bit n is supplied from the D flip-flop 115 triggered by the clock signal output from the flip-flop 114, as shown in FIG. Is output (every time the output QB of the flip-flop 114 rises), “1” and “0” are switched.

The clock signal (triangular wave generator (CLK)) generated while the data of the input bit n is “0” has a period (for example, 10−2 = 8) obtained by subtracting the period spread component from the reference period T _1. The clock signal generated while the same data is “1” has a period (10 + 2 = 12) in which the above-mentioned period spread component is added to the reference period T ₁ . Therefore, when the former and the latter are referred to as a minus clock signal and a plus clock signal, respectively, the sum of their periods is twice (8 + 12 = 2 × 10) the period T ₁ of the reference clock signal.
The data DA _- IN [2: 0] given to the input bits 3, 2, 1 from the linear feedback shift register circuit, that is, the data for changing the periodic spread component is transmitted to the linear feedback shift register circuit. Since the output QB of the output D flip-flop 115 is obtained by dividing the change of the output QB of the flip-flop 114 by half, it is maintained during the generation of the continuous negative clock signal and the positive clock signal. Is done. The data of the input bit m designates the reference periods T ₁ (10) and T ₂ (20).

The pulse width modulation circuit 10 shown in FIG. 1 including the triangular wave generator 11, the current modulation circuit 13, and the pseudorandom number generation circuit 14 operating as described above has a cycle of the clock signal output from the flip-flop 114 of FIG. A corresponding triangular wave signal V _OSC is output.
Accordingly, the comparator 12 of the switching regulator shown in FIG. 1 compares the error voltage signal V _FB is the output of the output voltage feedback circuit 11 and the triangular wave signal V _OSC, the corresponding said error voltage signal V _FB PWM This signal is converted into a signal, and this PWM signal is output to the drive circuit 30.

Drive circuit 30, the input voltage V _in on-time ratio based on the PWM signal to be switched and controls the semiconductor switch 40a, a 40b. Switched input voltage V _in is smoothed by the reactor L and capacitor C, is output as a voltage V _out.
The pulse width modulation circuit 10 can be used not only as such a switching regulator but also as a means for generating a PWM signal in an inverter circuit, a digital amplifier, or the like.

The switching noise of the semiconductor switches 40a and 40b is superimposed on the output voltage _Vout of the switching regulator. When the period of this switching noise is constant, there arises a problem that the power of this noise is concentrated on a specific frequency and a noise spectrum with a high peak value is generated. However, according to the switching regulator, since the semiconductor switches 40a and 40b are switched based on the PWM signal output from the pulse width modulation circuit 10, the above problem does not occur.

That is, since the period of the triangular wave signal V _OSC forming the PWM signal is diffused by the data DA _- IN [2: 0] (pseudorandom number data) shown in FIG. 7, the period of the PWM signal is also diffused. Is done. For this reason, the semiconductor switches 40a and 40b are switched at an irregular cycle. As a result, the noise spectrum accompanying the switching is averaged and the peak value is reduced.

Next, utilization of switching noise included in the output voltage _Vout of the switching regulator as communication information will be described.
Output voltage V _out of the switching regulator, peripheral devices (e.g., memory, display device, another switching regulator or the like) because it is supplied as a power supply to said output voltage V _out through the power supply line to the peripheral device The switching noise included in is transmitted. Therefore, by modulating switching noise with predetermined communication data on the switching regulator side, this data can be transmitted to the peripheral device via the power supply line. The transmission data can be recognized by demodulating the modulated switching noise by the peripheral device.

In FIG. 7, a short cycle minus clock signal and a plus clock signal correspond to a short cycle reference clock signal, and a long cycle minus clock signal and a plus clock signal correspond to a long cycle reference clock signal.
Therefore, if the frequency of the short-cycle reference clock signal is f ₁ and the frequency of the long-cycle reference clock signal is f ₂ , the frequency is f _{1 when} considering the short-cycle minus clock signal and the plus clock signal as a pair. Can be considered. Similarly, if a long-period negative clock signal and a positive clock signal are considered as a pair, the frequency can be regarded as f ₂ .

Communication data is input to the input bit m from a communication data generator (not shown). For example, when the communication data is 010, the data “0”, “1”, and “0” of each bit are sequentially input for a predetermined reference time T ₀ . As a result, as shown in FIG. 8, after the short cycle minus clock signal and plus clock signal (frequency f ₁ ) are generated for a time T ₀ , the long cycle minus clock signal and plus clock signal (frequency f ₂ ) are generated. Is generated at time T ₀ , and then a short-cycle negative clock signal and positive clock signal are generated again at time T ₀ . This means that in the switching regulator, switching noise of frequency f ₁ , switching noise of frequency f ₂ and switching noise of frequency f ₁ are sequentially generated for the time T ₀ . In FIG. 8, for simplicity of explanation, frequency spreading is ignored, but in reality, the period changes for each period as described above.

As described above, the sum of the period of the minus clock signal and the period of the subsequent plus clock signal is a fixed time (twice the period of the reference clock signal). Therefore, in the present embodiment, the reference time T ₀ is managed (measured) based on the relationship that the periodic sum is constant.
That is, from the above relationship, the short cycle minus clock signal and the plus clock signal are generated in total T ₀ / T _{1 at the} reference time T ₀ , and the long cycle minus clock signal and the plus clock signal are generated. Are generated in total T ₀ / T _{2 at} the reference time T ₀ . Therefore, when data “0” is input to the input bit m, the reference time T ₀ can be counted by counting the total number of T ₀ / T _{1 of the} short cycle minus clock signal and plus clock signal. Similarly, when data “1” is input to the input bit m, the reference time T ₀ is counted by counting a total of T ₀ / T _{2 of the} long-cycle negative clock signal and positive clock signal. can do.

Therefore, a counter (not shown) presets the count value T ₀ / T ₁ when the data “0” is input to the input bit m, and counts the short cycle negative clock signal and the positive clock signal. When the count value reaches the preset value T ₀ / T ₁ , a time-up signal is output.

The time-up signal is given to the communication data generator, and the communication data generator outputs the next data “1”. Along with this, the counter presets the count value T ₀ / T ₁ and counts the long cycle minus clock signal and plus clock signal, and the time when the count value reaches the preset value T ₀ / T ₂ is reached. An up signal is output. Therefore, the communication data generator outputs the next data “0”, and the minus clock signal and the plus clock signal with a short period are counted again for the reference time T ₀ .

  Thus, the clock signal shown in FIG. 8 is formed based on the communication data 010, and the switching noise corresponding to this is transmitted from the switching regulator to the peripheral device. Therefore, as described above, if a demodulating unit that demodulates the switching noise and recognizes the communication data 010 is provided in the peripheral device, the communication data 010 can be used for controlling the peripheral device.

As is clear from the above description, according to the present embodiment, although the period of the triangular wave output from the triangular wave generator 112 is irregularly changed according to the pseudo-random number, the minus clock signal and Since the relationship that the cycle sum of the plus clock signal is constant (twice the basic cycle T ₁ or T ₂ ) is obtained, the reference time T ₀ shown in FIG. 8 can be measured based on this relationship. Therefore, it is not necessary to provide a dedicated timing means incorporating a clock signal generator in order to measure the reference time T ₀ for managing the time of communication data, thereby reducing the cost of a switching regulator or the like having a communication function. Can be achieved.

1 is a block diagram showing a switching regulator to which a pulse width modulation circuit according to the present invention is applied. It is a circuit diagram which shows the structural example of a triangular wave generator and a current modulation circuit. It is a time chart which shows the effect | action of a triangular wave generator. It is a time chart which shows the period of a reference clock signal, and its change form. It is a block diagram which shows the structural example of the linear feedback shift register circuit which produces | generates pseudorandom numbers (M series code | symbol). It is a block diagram which shows the function provided with respect to each input bit. 5 is a time chart showing the relationship between a reference clock signal, a minus based on a short reference period, a plus clock signal, a minus based on a long reference period, and a plus clock signal. It is explanatory drawing which illustrated the frequency change of the clock signal based on communication data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pulse width modulation circuit 11 Triangular wave generator 12, 113a, 113b Comparator 13 Current modulation circuit 14 Pseudorandom number generation circuit 20 Output voltage feedback circuit 30 Drive circuit 40a, 40b, 111a, 111b Semiconductor switch 114, 115 Flip-flop 131,134- 1-134-n Current source 132 D / A converter 133 Decoder C _T capacitor

Claims (4)

A triangular wave generating means for generating a triangular wave signal having a constant amplitude having a period defined by the charge / discharge current of the capacitor;
Current modulation means for discretely changing the charge / discharge current of the capacitor from a reference current value at a timing synchronized with the triangular wave signal;
Comparing means for generating a pulse width modulated signal by comparing the triangular wave signal and the modulated signal,
The current modulation means allocates the discrete change component having an equal value to one and the other two periods of the two continuous periods of the triangular wave signal, and assigns the discrete change component to the one and the other periods, respectively. Configured to add and subtract to the reference current value ,
Further, a pulse width modulation circuit characterized in that two kinds of the reference current values are set and the two kinds of reference current values are selected and designated .   Pseudo random number generating means for generating a pseudo random number at a timing synchronized with the triangular wave signal is provided, and the current modulation means is configured to set a discrete change component of the charge / discharge current based on the pseudo random number. The pulse width modulation circuit according to claim 1.   The current modulation means includes a plurality of switches that are selectively turned on and off based on the pseudo-random numbers, and a plurality of current sources that can be selected by these switches, and each current source selected by each switch 3. The pulse width modulation circuit according to claim 2, wherein the output current is added and the added current is set as a discrete change component of the charge / discharge current. 4. 4. A switching regulator, wherein the pulse width modulation circuit according to claim 1 is applied, and an error signal is used as the modulated signal.