JP4974384B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Some conventional semiconductor devices are provided with a low dielectric constant film wiring laminated structure portion having a laminated structure of a plurality of low dielectric constant films and the same number of wirings on a semiconductor substrate (for example, Patent Document 1). reference). Here, when an insulating film made of silicon oxide or the like having a dielectric constant higher than that of the low dielectric constant film is used instead of the low dielectric constant film, when the distance between the wirings becomes smaller due to miniaturization, the distance between the wirings As a result, the delay of the signal transmitted through the wiring increases. Therefore, in order to improve this point, a low dielectric constant film is used instead of the insulating film made of silicon oxide or the like.

JP 2008-130880 A (FIG. 13)

  By the way, the low dielectric constant film has low mechanical strength, is easily affected by moisture, and thus easily peels off. In particular, in a porous low-permittivity film containing air, the dielectric constant can be further reduced, but this is remarkable. Therefore, in the above-described conventional semiconductor device, the side surface of the low dielectric constant film wiring laminated structure is covered with an insulating film made of an organic resin so that the low dielectric constant film wiring laminated structure is difficult to peel off.

  In the above conventional semiconductor device manufacturing method, first, a low dielectric constant film having a laminated structure of a plurality of low dielectric constant films and the same number of wiring layers on a semiconductor substrate in a wafer state (hereinafter referred to as a semiconductor wafer). A wiring laminated structure portion is formed, and a low dielectric constant film wiring laminated structure portion having a passivation film made of an inorganic material such as silicon oxide is prepared. In this case, openings are formed in the passivation film in the dicing street and the regions on both sides thereof.

  Next, a groove is formed in a part of the low dielectric constant film wiring laminated structure exposed through the opening of the passivation film by laser processing by laser irradiation. Here, since the low dielectric constant film is fragile, if a groove is formed by cutting with a blade, a large number of cuts and breaks occur on the cut surface of the low dielectric constant film. Therefore, the groove is formed by laser processing by laser irradiation. The recommended method is Then, when an insulating film made of an organic resin is formed in the groove and on the upper surface of the passivation film, the side surface (cut surface) of the low dielectric constant film wiring laminated structure is covered with the insulating film, and the low dielectric constant film wiring laminated structure is It can be made difficult to peel.

  By the way, in order to completely remove a part of the low dielectric constant film wiring laminated structure exposed through the opening of the passivation film, the upper surface of the semiconductor wafer in the region where the groove is to be formed by laser processing by laser irradiation. The side will be removed to some extent. Finally, the semiconductor wafer and the insulating film formed thereon are cut along the dicing street in the center of the groove to obtain individual semiconductor devices.

  However, in the semiconductor device obtained in this way, the side surface (cut surface) of the semiconductor substrate is exposed, so that the side surface of the semiconductor substrate is not protected and cracks or the like may occur on the side surface of the semiconductor substrate. There is a problem. Note that when the depth of the groove formed by laser processing by laser irradiation is increased, the side surface of the semiconductor substrate can be covered with the insulating film up to that depth, but not only the laser processing time is increased, but the side surface of the semiconductor substrate is also increased. Protection cannot be perfect.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can completely protect the side surface of a semiconductor substrate.

According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a low dielectric constant film wiring laminate in which a low dielectric constant film having a relative dielectric constant of 3.0 or less and a wiring are laminated on one surface of a semiconductor wafer; A step of preparing the structure portion is formed, and laser processing by laser irradiation penetrates the low dielectric constant film wiring laminated structure portion in a predetermined width region wider than that including dicing streets. Forming a first groove reaching the intermediate surface in the thickness direction to expose a side surface of the low dielectric constant film wiring multilayer structure portion and an intermediate surface of the semiconductor wafer; and the low dielectric constant film wiring multilayer structure Forming a connection pad portion for an electrode on the insulating film formed on the portion and connecting to the connection pad portion of the wiring of the low dielectric constant film wiring laminated structure portion; and external connection on the electrode connection pad portion For bump Forming a pole, forming a sealing film made of organic resin around the bump electrode for external connection in the first groove and on the insulating film, and dicing in the first groove Forming a second groove deeper than the lower surface of the low dielectric constant film wiring laminated structure portion in the sealing film corresponding to the street; and at least the second groove on the lower surface side of the semiconductor wafer A step of reducing the thickness of the semiconductor wafer by grinding until it is exposed, and separating the semiconductor wafer to obtain a plurality of semiconductor devices.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a low dielectric constant film wiring laminate in which a low dielectric constant film having a relative dielectric constant of 3.0 or less and a wiring are laminated on one surface of a semiconductor wafer; A step of preparing a structure portion formed thereon, a step of forming an insulating film on the low dielectric constant film wiring laminated structure portion in a region other than a predetermined width region wider than that including a dicing street, and the insulation Forming a connection pad portion for an electrode on the film by connecting to the connection pad portion of the wiring of the low dielectric constant film wiring laminated structure portion, and forming a bump electrode for external connection on the connection pad portion for the electrode And forming a first groove reaching the intermediate surface in the thickness direction of the semiconductor wafer through the low dielectric constant film wiring laminated structure portion in the predetermined width region by laser processing by laser irradiation, Low dielectric constant A step of exposing the side surface of the wiring laminated structure and the intermediate surface of the semiconductor wafer, and forming a sealing film made of an organic resin around the external connection bump electrode in the first groove and on the insulating film Forming a second groove deeper than a lower surface of the low dielectric constant film wiring laminated structure portion in the sealing film in a portion corresponding to the dicing street in the first groove, and the semiconductor Grinding the lower surface side of the wafer until at least the second groove is exposed, thereby reducing the thickness of the semiconductor wafer and separating the semiconductor wafer to obtain a plurality of semiconductor devices. It is characterized by this.
According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the glass transition temperature of the low dielectric constant film is 400 ° C. or higher. .
According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the first aspect , wherein the second groove has a bottom surface and an upper surface of the semiconductor wafer below the second groove. The sealing film is formed so as to remain in between.
According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect , wherein the second groove is formed using a dicing blade. To do.
A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is the method according to any one of the first to fifth aspects, wherein the step of forming the electrode connection pad portion includes forming the electrode on the insulating film. This is a step of forming an upper layer wiring having a connection pad portion for use.
According to a seventh aspect of the present invention, in the semiconductor device manufacturing method according to the sixth aspect, the external connection bump electrode is a columnar electrode formed on a connection pad portion of the upper wiring. It is characterized by.
According to an eighth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the seventh aspect of the present invention, further comprising a step of forming a solder ball on the columnar electrode.
According to a ninth aspect of the present invention, in the semiconductor device manufacturing method according to the eighth aspect of the present invention, the solder ball is formed after the sealing film is formed and the second groove is formed. It is characterized by being done before
A method of manufacturing a semiconductor device according to a tenth aspect of the present invention is the method for manufacturing a semiconductor device according to the eighth or ninth aspect , wherein after the step of forming a solder ball on the columnar electrode, the lower surface side of the semiconductor wafer is placed on the lower surface side. Before the step of grinding until the groove of 2 is exposed, the method includes a step of attaching a protective tape on which an ultraviolet curable adhesive material is formed to the upper surfaces of the solder balls and the sealing material. is there.

  According to the present invention, the first groove reaching the intermediate surface in the thickness direction of the semiconductor wafer through the low dielectric constant film wiring laminated structure in the predetermined width region wider than that including the dicing street is formed, A sealing film made of an organic resin is formed on the insulating film formed in the first groove and on the low dielectric constant film wiring laminated structure, and the sealing film corresponding to the dicing street in the first groove In addition, the second groove deeper than the lower surface of the low dielectric constant film wiring laminated structure is formed, and the lower surface side of the semiconductor wafer is ground until at least the second groove is exposed, thereby reducing the thickness of the semiconductor wafer. In addition, since the semiconductor wafer is separated to obtain a plurality of semiconductor devices, the side surface of the semiconductor substrate can be completely covered with the sealing film, and thus the protection of the side surface of the semiconductor substrate can be completed. .

  FIG. 1 is a sectional view showing an example of a semiconductor device manufactured by the manufacturing method of the present invention. This semiconductor device includes a silicon substrate (semiconductor substrate) 1. On the upper surface of the silicon substrate 1, an integrated circuit having a predetermined function, in particular, an element (not shown) such as a transistor, a diode, a resistor, or a capacitor is formed, and a peripheral portion of the upper surface is connected to each element of the integrated circuit. Further, connection pads 2 made of aluminum metal or the like are provided. Although only two connection pads 2 are shown in the figure, a large number are actually arranged around the upper surface of the silicon substrate 1.

  On the upper surface of the silicon substrate 1, there is provided a low dielectric constant film wiring laminated structure portion 3 for connecting the elements of the integrated circuit. The low dielectric constant film wiring laminated structure 3 has a structure in which a plurality of layers, for example, four low dielectric constant films 4 and the same number of wirings 5 made of copper or the like are alternately laminated. In this case, the wiring 5 of each layer is mutually connected between layers. One end of the lowermost wiring 5 is connected to the connection pad 2 through an opening 6 provided in the lower dielectric constant film 4. The connection pad portion 5 a of the uppermost wiring 5 is arranged in the periphery of the upper surface of the uppermost low dielectric constant film 4.

  As a material for the low dielectric constant film 4, a polysiloxane-based material having an Si—O bond and an Si—H bond (HSQ: Hydrogen silsesquioxane, relative dielectric constant 3.0), an Si—O bond and an Si—CH 3 bond. Polysiloxane materials (MSQ: Methyl silsesquioxane, dielectric constant 2.7 to 2.9), carbon doped silicon oxide (SiOC: Carbon dielectric silicon 2.7 to 2.9), organic polymer materials A low-k material can be used, and a material having a relative dielectric constant of 3.0 or less and a glass transition temperature of 400 ° C. or more can be used.

Organic polymer low-k materials include “SiLK (relative dielectric constant 2.6)” manufactured by Dow Chemical, Honeywell.
For example, “FLARE (relative dielectric constant 2.8)” manufactured by Electronic Materials may be used. Here, the glass transition temperature being 400 ° C. or more is to sufficiently withstand the temperature in the manufacturing process described later. In addition, the porous type | mold of said each material can also be used.

  In addition to the above, the material of the low dielectric constant film 4 has a relative dielectric constant of greater than 3.0 in a normal state. Those having a transition temperature of 400 ° C. or higher can be used. For example, fluorine-doped silicon oxide (FSG: Fluorinated Silicate Glass, relative dielectric constant: 3.5 to 3.7), boron-doped silicon oxide (BSG: Boron-doped Silicate Glass, relative dielectric constant: 3.5), silicon oxide (ratio) The dielectric constant is 4.0 to 4.2).

  A passivation film (insulating film) 7 made of an inorganic material such as silicon oxide is provided on the upper surfaces of the uppermost wiring 5 and the lower dielectric constant film 4. An opening 8 is provided in the passivation film 7 in a portion corresponding to the connection pad portion 5 a of the uppermost wiring 5. A protective film (insulating film) 9 made of an organic resin such as a polyimide resin is provided on the upper surface of the passivation film 7. An opening 10 is provided in the protective film 9 in a portion corresponding to the opening 8 of the passivation film 7.

  An upper wiring 11 is provided on the upper surface of the protective film 9. The upper layer wiring 11 has a two-layer structure of a base metal layer 12 made of copper or the like provided on the upper surface of the protective film 9 and an upper metal layer 13 made of copper provided on the upper surface of the base metal layer 12. . One end of the upper wiring 11 is connected to the connection pad 5 a of the uppermost wiring 5 through the openings 8 and 10 of the passivation film 7 and the protective film 9. In the above description, only one of the passivation film 7 and the protective film 9 can be used.

  A columnar electrode (external connection bump electrode) 14 made of copper is provided on the upper surface of the connection pad portion (electrode connection pad portion) of the upper layer wiring 11. A sealing film 15 made of an organic resin such as an epoxy resin is formed on the peripheral surface of the silicon substrate 1, the low dielectric constant film wiring laminated structure 3, the passivation 7 and the protective film 9, and the upper surface of the protective film 9 including the upper wiring 11. The upper surface is provided so as to be flush with the upper surface of the columnar electrode 14. A solder ball 16 is provided on the upper surface of the columnar electrode 14.

  Here, the side surfaces of the silicon substrate 1, the low dielectric constant film wiring laminated structure 3, and the passivation film 7 substantially form one surface and are covered with the sealing film 15. The side surface of the protective film 9 is disposed on the inner side than the side surfaces of the silicon substrate 1, the low dielectric constant film wiring laminated structure 3, and the passivation film 7. The lower surface of the sealing film 15 provided on the peripheral side surface of the silicon substrate 1 is flush with the lower surface of the silicon substrate 1.

(First example of manufacturing method)
Next, a first example of this semiconductor device manufacturing method will be described. First, as shown in FIG. 2, a connection pad 2, four low dielectric constant films 4 and wirings 5, and a passivation film 7 are formed on a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21). Then, the one in which the connection pad portion 5a of the uppermost wiring 5 is exposed through the opening 8 formed in the passivation film 7 is prepared.

  In this case, the thickness of the semiconductor wafer 21 is somewhat thicker than the thickness of the silicon substrate 1 shown in FIG. Examples of the material for the low dielectric constant film 4 include those described above, including those having a porous type, those having a relative dielectric constant of 3.0 or less and a glass transition temperature of 400 ° C. or more. be able to. In FIG. 2, an area indicated by reference numeral 22 is an area corresponding to dicing street.

  Next, as shown in FIG. 3, the passivation film 7 and four layers of low dielectrics in the dicing street 22 and the regions on both sides thereof (a predetermined width region wider than that including the dicing street 22) are obtained by laser processing by laser irradiation. A first groove 23 that penetrates through the rate film 4 and reaches the intermediate surface in the thickness direction of the semiconductor wafer 21 is formed. In this case, the first groove 23 is formed in a frame shape so as to surround each device region (each inner region of the dicing street 22) in a plan view.

  In this state, the four layers of the low dielectric constant film 4 laminated on the semiconductor wafer 21 are separated by the first groove 23, thereby forming the low dielectric constant film wiring laminated structure portion 3. Further, the side surfaces of the semiconductor wafer 21, the low dielectric constant film wiring laminated structure portion 3 and the passivation film 7 in the first groove 23 portion are substantially formed and exposed. Further, the upper surface (intermediate surface) of the semiconductor wafer 21 in the portion of the first groove 23 is exposed.

  Next, as shown in FIG. 4, an organic resin such as a polyimide resin is formed on the upper surface of the passivation film 7 including the inside of the first groove 23 by spin coating, screen printing, or the like. Then, the protective film 9 is formed by patterning by photolithography. In this state, an opening 10 is formed in the protective film 9 in a portion corresponding to the opening 8 of the passivation film 7. Further, the side surface of the protective film 9 is disposed on the inner side than the side surface of the passivation film 7. The protective film 9 may be formed before the first groove 23 is formed.

  Next, as shown in FIG. 5, the upper surface of the protective film 9 including the upper surface of the connection pad portion 5a of the uppermost wiring 5 exposed through the openings 8 and 10 of the passivation film 7 and the protective film 9 is protected. A base metal layer 12 is formed on the side surface of the film 9, the upper surface of the periphery of the passivation film 7, and the inner wall surface and the bottom surface of the first groove 23. In this case, the base metal layer 12 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a plating resist film 24 is patterned on the upper surface of the base metal layer 12. In this case, an opening 25 is formed in the plating resist film 24 in a portion corresponding to the upper metal layer 13 formation region. Next, the upper metal layer 13 is formed on the upper surface of the base metal layer 12 in the opening 25 of the plating resist film 24 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path. Next, the plating resist film 24 is peeled off.

  Next, as shown in FIG. 6, a plating resist film 26 is patterned on the upper surface of the base metal layer 12 including the upper metal layer 13. In this case, an opening 27 is formed in the plating resist film 26 in a portion corresponding to the connection pad portion (columnar electrode 14 formation region) of the upper metal layer 13. Next, the columnar electrode 14 is formed on the upper surface of the connection pad portion of the upper metal layer 13 in the opening 27 of the plating resist film 26 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path.

  Next, the plating resist film 26 is peeled off, and then unnecessary portions of the base metal layer 12 are removed by etching using the upper metal layer 13 as a mask. As shown in FIG. The metal layer 12 remains. In this state, the upper metal layer 13 and the underlying metal layer 12 remaining under the upper metal layer 13 form the upper wiring 11 having a two-layer structure.

  Next, as shown in FIG. 8, the upper surface and side surfaces of the upper layer wiring 11, the upper surface and side surfaces of the columnar electrode 14, the upper surface and side surfaces of the protective film 9, and the periphery of the passivation film 7 by spin coating, screen printing, A sealing film 15 made of an organic material such as an epoxy resin is formed so as to cover the upper surface and above the first groove 23 so as to have a thickness greater than the height of the columnar electrode 14. Therefore, in this state, the upper surface of the columnar electrode 14 is covered with the sealing film 15.

  Next, the upper surface side of the sealing film 15 is appropriately ground using a grinding wheel (not shown) to expose the upper surface of the columnar electrode 14 as shown in FIG. 9, and the exposed columnar electrode is exposed. The upper surface of the sealing film 15 including the upper surface of 14 is planarized. Next, as shown in FIG. 10, solder balls 16 are formed on the upper surface of the columnar electrode 14.

  Next, as shown in FIG. 11, using a dicing blade 28 having a width smaller than that of the first groove 23, the sealing film 15 in a portion corresponding to the dicing street 22 in the substantially central portion in the first groove 23. Then, a second groove 29 deeper than the lower surface of the low dielectric constant film wiring laminated structure 3 is formed. In this case, the bottom surface of the second groove 29 is set to be lower than the lower surface of the low dielectric constant film wiring laminated structure portion 3 and above the upper surface of the semiconductor wafer 21 in the portion of the first groove 23. Therefore, in this state, the sealing film 15 remains to some extent between the bottom surface of the second groove 29 and the upper surface of the semiconductor wafer 21 in the portion of the second groove 29.

  Next, as shown in FIG. 12, an ultraviolet curable uncured adhesive material 31 provided on the lower surface of the protective tape 30 is attached to the upper surface of the sealing film 15 including the solder balls 16. In this case, the adhesive material 31 is thicker than the solder ball 16. Therefore, in this state, the solder ball 16 is completely covered with the adhesive material 31. In FIG. 12, the adhesive material 31 is illustrated as being bonded to the entire surface of the solder ball 16, but the adhesive material 31 is bonded to a part of the upper side, not the entire surface of the solder ball 16. Just be fine.

  Next, the sealing film 15 on the lower surface side of the semiconductor wafer 21 and the portion of the second groove 29 is ground using a grinding wheel (not shown) until at least the second groove 29 is exposed. Then, as shown in FIG. 13, the thickness of the semiconductor wafer 21 is reduced, and the semiconductor wafer 21 is separated into individual silicon substrates 1, thereby being separated by the second groove 29 as a whole. Although the semiconductor device is divided into pieces, the upper surface of the sealing film 15 including the solder balls 16 of each individual semiconductor device is adhered to the protective tape 30 via the adhesive material 31, so that each individual semiconductor device is separated. It will not fall apart.

  Next, ultraviolet rays are irradiated from the upper surface side of the protective tape 30, the adhesive material 31 is cured, and the adhesive force is reduced. Next, as shown in FIG. 14, the lower surface of the silicon substrate 1 and the sealing film 15 of each individual semiconductor device is pasted on the upper surface of the adhesive material 33 provided on the upper surface of the pickup tape (support tape) 32. wear. This adhesive material 33 is also an ultraviolet curable type and is in an uncured state. Next, the adhesive material 31 is peeled off together with the protective tape 30 from the upper surfaces of the solder balls 16 and the sealing film 15 of the individual semiconductor devices. Next, the adhesive tape 33 is cured by irradiating ultraviolet rays from the pickup tape 32 side, and the individual semiconductor devices are picked up from the adhesive tape 33 of the pickup tape 32 with reduced adhesive strength. Multiple devices are obtained.

  If the adhesive material 33 provided on the upper surface of the pickup tape 32 is not an ultraviolet curing type, the adhesive material 33 provided on the upper surface of the pickup tape 32 is attached to the lower surface of the silicon substrate 1 and the sealing film 15 of the semiconductor device. After attaching, the adhesive material 31 may be cured by irradiating ultraviolet rays from the upper surface side of the protective tape 30.

  In the semiconductor device thus obtained, the lower surface of the sealing film 15 formed on the side surfaces of the silicon substrate 1 and the low dielectric constant film wiring laminated structure 3 is flush with the lower surface of the silicon substrate 1. Since the side surface of the low dielectric constant film wiring multilayer structure 3 is completely covered by the sealing film 15, the low dielectric constant film wiring multilayer structure 3 can be made difficult to peel off from the silicon substrate 1, and The side surface of the silicon substrate 1 can be completely protected from cracks and the like.

  By the way, in the method of manufacturing the semiconductor device, as shown in FIG. 3, after forming the first groove 23 and forming the wiring 11 and the columnar electrode 14 as shown in FIG. 7, as shown in FIG. In addition, since the sealing film 15 is filled in the first groove 23, the period during which the first groove 23 is in a space state becomes relatively long. As a result, the semiconductor wafer 21 may break at the first groove 23 during handling. Then, next, the case where the period when the inside of the 1st groove | channel 23 is a space state can be shortened is demonstrated.

(Second example of manufacturing method)
Next, a second example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this case, after preparing what is shown in FIG. 2, as shown in FIG. 15, an organic resin such as polyimide resin is formed on the upper surface of the passivation film 7 by spin coating, screen printing, or the like, and photolithography is performed. The protective film 9 is formed by patterning by the method.

  In this state, an opening 10 is formed in the protective film 9 in a portion corresponding to the opening 8 of the passivation film 7. An opening 41 is formed in the protective film 9 in the dicing street 22 and the regions on both sides thereof. The opening 41 of the protective film 9 is formed in a frame shape so as to surround each device region (each inner region of the dicing street 22) in a plan view.

  Next, as shown in FIG. 16, the upper surface of the protective film 9 and the protection including the upper surface of the connection pad portion 5 a of the uppermost wiring 5 exposed through the openings 8 and 10 of the passivation film 7 and the protective film 9. A base metal layer 12 is formed on the upper surface of the passivation film 7 and the side surfaces of the protective film 9 exposed through the opening 41 of the film 9 by electroless plating or the like.

  Next, a plating resist film 24 is patterned on the upper surface of the base metal layer 12. In this case, an opening 25 is formed in the plating resist film 24 in a portion corresponding to the upper metal layer 13 formation region. Next, the upper metal layer 13 is formed on the upper surface of the base metal layer 12 in the opening 25 of the plating resist film 24 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path. Next, the plating resist film 24 is peeled off.

  Next, as shown in FIG. 17, a plating resist film 26 is patterned on the upper surface of the base metal layer 12 including the upper metal layer 13. In this case, an opening 27 is formed in the plating resist film 26 in a portion corresponding to the connection pad portion (columnar electrode 14 formation region) of the upper metal layer 13. Next, the columnar electrode 14 is formed on the upper surface of the connection pad portion of the upper metal layer 13 in the opening 27 of the plating resist film 26 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path.

  Next, the plating resist film 26 is peeled off, and then unnecessary portions of the base metal layer 12 are removed by etching using the upper metal layer 13 as a mask. As shown in FIG. The metal layer 12 remains. In this state, the upper metal layer 13 and the underlying metal layer 12 remaining under the upper metal layer 13 form the upper wiring 11 having a two-layer structure.

  Next, as shown in FIG. 19, the passivation film 7 and four layers of low dielectrics in the dicing street 22 and the regions on both sides thereof (a predetermined width region wider than that including the dicing street 22) are obtained by laser processing by laser irradiation. A first groove 23 that penetrates through the rate film 4 and reaches the intermediate surface in the thickness direction of the semiconductor wafer 21 is formed. In this case, the first groove 23 is formed in a frame shape inside the side surface of the protective film 9 so as to surround each device region in a plan view.

  In this state, the four layers of the low dielectric constant film 4 laminated on the semiconductor wafer 21 are separated by the first groove 23, thereby forming the low dielectric constant film wiring laminated structure portion 3. Further, the side surfaces of the semiconductor wafer 21, the low dielectric constant film wiring laminated structure portion 3 and the passivation film 7 in the first groove 23 portion are substantially formed and exposed. Further, the semiconductor wafer 21 in the portion of the first groove 23 is exposed. Here, the state shown in FIG. 19 is the same as the state shown in FIG. Therefore, a plurality of semiconductor devices shown in FIG. 1 are obtained through the same steps as those in the first example of the manufacturing method.

  As described above, in this method of manufacturing a semiconductor device, after forming the wiring 11 and the columnar electrode 14 as shown in FIG. 18, the first groove 23 is formed as shown in FIG. As shown in FIG. 8, since the sealing film 15 is filled in the first groove 23, the period during which the first groove 23 is in a space state can be shortened, and as a result, during handling. The possibility that the semiconductor wafer 21 may break at the first groove 23 can be reduced.

  In the above-described embodiment, the upper layer wiring 11 is formed on the protective film 9 and the columnar electrode 14 is formed on the connection pad portion of the upper layer wiring 11. The present invention can also be applied to a structure in which only the connection pad portion is formed on top and the external connection bump electrodes such as the columnar electrode 14 and the solder ball 16 are formed on the connection pad portion.

Sectional drawing of an example of the semiconductor device manufactured by the manufacturing method of this invention. Sectional drawing of what was initially prepared in the 1st example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of a predetermined | prescribed process in the 2nd example of the manufacturing method of the semiconductor device shown in FIG. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Low dielectric constant film wiring laminated structure part 4 Low dielectric constant film 5 Wiring 7 Passivation film 9 Protective film 11 Upper layer wiring 14 Columnar electrode 15 Sealing film 16 Solder ball 21 Semiconductor wafer 22 Dicing street 23 1st Groove 29 Second groove

Claims (10)

Preparing a low dielectric constant film wiring laminated structure in which a low dielectric constant film having a relative dielectric constant of 3.0 or less and a wiring are laminated on one surface of a semiconductor wafer;
A first groove reaching the intermediate surface in the thickness direction of the semiconductor wafer through the low dielectric constant film wiring laminated structure in a predetermined width region including a dicing street by laser processing by laser irradiation. Forming a step of exposing a side surface of the low dielectric constant film wiring multilayer structure and an intermediate surface of the semiconductor wafer; and
Forming a connection pad portion for an electrode on an insulating film formed on the low dielectric constant film wiring multilayer structure portion by connecting to a connection pad portion of a wiring of the low dielectric constant film wiring multilayer structure portion;
Forming an external connection bump electrode on the electrode connection pad portion;
Forming a sealing film made of an organic resin around the bump electrode for external connection in the first groove and on the insulating film;
Forming a second groove deeper than a lower surface of the low dielectric constant film wiring laminated structure portion in the sealing film in a portion corresponding to the dicing street in the first groove;
Grinding the lower surface side of the semiconductor wafer until at least the second groove is exposed, reducing the thickness of the semiconductor wafer, and separating the semiconductor wafer to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: Preparing a low dielectric constant film wiring laminated structure in which a low dielectric constant film having a relative dielectric constant of 3.0 or less and a wiring are laminated on one surface of a semiconductor wafer;
Forming an insulating film on the low dielectric constant film wiring laminated structure in a region other than the predetermined width region wider than that including the dicing street; and
Forming a connection pad portion for an electrode on the insulating film by connecting to a connection pad portion of a wiring of the low dielectric constant film wiring laminated structure; and
Forming an external connection bump electrode on the electrode connection pad portion;
By forming a first groove that penetrates the low dielectric constant film wiring laminated structure portion in the predetermined width region and reaches the intermediate surface in the thickness direction of the semiconductor wafer by laser processing by laser irradiation, the low dielectric constant is formed. Exposing the side surface of the rate film wiring laminated structure and the intermediate surface of the semiconductor wafer;
Forming a sealing film made of an organic resin around the bump electrode for external connection in the first groove and on the insulating film;
Forming a second groove deeper than a lower surface of the low dielectric constant film wiring laminated structure portion in the sealing film in a portion corresponding to the dicing street in the first groove;
Grinding the lower surface side of the semiconductor wafer until at least the second groove is exposed, reducing the thickness of the semiconductor wafer, and separating the semiconductor wafer to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the low dielectric constant film has a glass transition temperature of 400 ° C. or higher. In the invention described in any one of claims 1 to 3, wherein the second groove is to be formed as the sealing film between the bottom surface and the top surface of the semiconductor wafer thereunder are left A method of manufacturing a semiconductor device. In the invention described in any one of claims 1 to 4, a method of manufacturing a semiconductor device formed of the second groove is characterized by performed using a dicing blade. In the invention of any one of claims 1 to 5, the step of forming the electrode connection pad portion is a step of forming the upper wiring having the electrode connection pad portions on the insulating film A method of manufacturing a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the bump electrode for external connection is a columnar electrode formed on a connection pad portion of the upper wiring.   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a solder ball on the columnar electrode.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the solder ball is formed after the sealing film is formed and before the second groove is formed. In the invention according to claim 8 or 9, after the step of forming a solder ball on the columnar electrode, before the step of grinding the lower surface side of said semiconductor wafer to said second groove is exposed, ultraviolet curing A method of manufacturing a semiconductor device, comprising a step of attaching a protective tape on which an adhesive material of a mold is formed to the upper surfaces of the solder balls and the sealing material.

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