JP4973837B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4973837B2 JP4973837B2 JP2006067776A JP2006067776A JP4973837B2 JP 4973837 B2 JP4973837 B2 JP 4973837B2 JP 2006067776 A JP2006067776 A JP 2006067776A JP 2006067776 A JP2006067776 A JP 2006067776A JP 4973837 B2 JP4973837 B2 JP 4973837B2
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- resin material
- semiconductor device
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- manufacturing
- wiring pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- Wire Bonding (AREA)
Description
複数の電気的接続部を有する配線パターンが形成されたベース基板を用意する工程と、
前記ベース基板に、前記配線パターンを部分的に覆うように第1の樹脂材料を設ける工程と、
前記第1の樹脂材料を半硬化させる工程と、
前記ベース基板に複数の電極を有する半導体チップを搭載して、前記電気的接続部と前記電極とを対向させて電気的に接続する工程と、
前記ベース基板と前記半導体チップとの間に第2の樹脂材料を設ける工程と、
前記第1の樹脂材料を硬化させて前記配線パターンを部分的に覆うレジスト層を形成し、かつ、前記第2の樹脂材料を硬化させて前記電気的接続部及び前記電極を封止する封止部を形成する工程と、
を含む。
前記第1及び第2の樹脂材料は、熱硬化性の材料であってもよい。
前記配線パターンの表面はスズめっき層であってもよい。
本発明は、以上の実施の形態に限定されるものではない。
Claims (3)
- 第1の面において複数の電気的接続部を有する配線パターンが形成されたベース基板を用意する工程と、
前記電気的接続部避け、前記配線パターンの前記第1の面と接する面とは反対側の第2の面を部分的に覆うように第1の樹脂材料を設ける工程と、
前記第1の樹脂材料を半硬化させる工程と、
前記ベース基板に複数の電極を有する半導体チップを搭載して、前記電気的接続部と前記電極とを対向させて電気的に接続する工程と、
前記ベース基板と前記半導体チップとの間に第2の樹脂材料を設ける工程と、
前記第1の樹脂材料を硬化させて前記配線パターンを部分的に覆うレジスト層を形成し、かつ、前記第2の樹脂材料を硬化させて前記電気的接続部及び前記電極を封止する封止部を形成する工程と、
を含む半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1及び第2の樹脂材料は、熱硬化性の材料である半導体装置の製造方法。 - 請求項1又は請求項2記載の半導体装置の製造方法において、
前記配線パターンの表面はスズめっき層である半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006067776A JP4973837B2 (ja) | 2006-03-13 | 2006-03-13 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006067776A JP4973837B2 (ja) | 2006-03-13 | 2006-03-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007250573A JP2007250573A (ja) | 2007-09-27 |
JP4973837B2 true JP4973837B2 (ja) | 2012-07-11 |
Family
ID=38594589
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006067776A Expired - Fee Related JP4973837B2 (ja) | 2006-03-13 | 2006-03-13 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP4973837B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5180137B2 (ja) * | 2009-04-10 | 2013-04-10 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP5999432B2 (ja) * | 2013-02-01 | 2016-09-28 | 東芝ライテック株式会社 | 発光装置及び照明装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000216195A (ja) * | 1999-01-22 | 2000-08-04 | Mitsubishi Electric Corp | 半導体装置、その製造方法およびこの製造方法に用いる接着剤 |
JP3715861B2 (ja) * | 2000-03-21 | 2005-11-16 | ローム株式会社 | 半導体装置の組立方法 |
JP2005026636A (ja) * | 2003-07-04 | 2005-01-27 | Sony Corp | 半導体装置及びその製造方法 |
-
2006
- 2006-03-13 JP JP2006067776A patent/JP4973837B2/ja not_active Expired - Fee Related
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JP2007250573A (ja) | 2007-09-27 |
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