JP4965161B2 - Memory card controller - Google Patents

Description

  The present invention relates to a memory card controller that can be used for various small memory cards, and more particularly to a memory card controller having a high-speed serial interface circuit such as an IEEE1394 interface circuit.

  In recent years, in the field of digital equipment, the capacity of flash memory cards has been increasing in order to enable recording and playback of high-quality, long-time movies, music, and still images, and high-speed data when handling large volumes of data. Realizing the transfer was an important issue. Small memory cards are remarkably widespread in portable devices due to the convenience of carrying them, but battery-powered portable devices are required to have low power consumption so that they can withstand long-time driving while maintaining the high performance of memory cards. ing. The role played by the controller controlling the memory card in order to bring out the best performance of the memory card while reducing power consumption is important. In digital devices using small memory cards, it is necessary to reduce power consumption and reduce costs while incorporating many functions to improve performance.

FIG. 5 is a schematic block diagram showing a configuration example of a conventional memory card controller.
In FIG. 5, the memory card controller 100 includes a primary side PCI bus interface circuit 101, a memory card interface circuit unit 102, and an IEEE 1394 interface circuit unit 103. The card slot 133 has a specification that allows use of a small memory card 134 such as a Memory Stick (MS) (registered trademark) or an SD card (registered trademark). The memory card interface circuit unit 102 is connected to the card slot 133. And an SD card interface circuit (shown as an SDIF circuit) 111, an MS interface circuit (shown as an MSIF circuit) 112, and an I / O control circuit 113. .

  The IEEE 1394 interface circuit unit 103 includes an IEEE 1394 PLL circuit 115 that generates and outputs a PLL clock CLKi of 393.216 MHz when a clock of 24.576 MHz is input from an external oscillator 131, and the PLL clock signal CLKi Is used only in some blocks of the IEEE 1394 interface circuit unit 103 via the PLL control circuit 116. An IEEE 1394 connector (shown as a connector in the figure) 132 is connected to the IEEE 1394 interface circuit unit 103.

FIG. 6 is a diagram showing a flow of a clock supplied to the memory card interface circuit unit 102 configured as shown in FIG.
As shown in FIG. 6, the PCI clock CLKp is input from the PCI bus 120 through the PCI interface circuit 101 to the SD card interface circuit 111 and the MS interface circuit 112 in the memory card interface circuit unit 102. ing.

Conventionally, the PLL control on the memory card side is related to the clock control. In order to reduce the power consumption without affecting the performance of the memory card, the PLL oscillation stop control and the clock supply in the oscillation state are provided. Some have taken a means to properly use the shutoff control (see, for example, Patent Document 1). Some memory card controllers include a memory card PLL (for example, see Non-Patent Document 1).
JP 2002-109490 A Data manual for PCI 7621, 7611, 7421, 7411 at Texas Instruments (3.5.11 48-MHz Clock Requirements).

However, the maximum standard of the operating frequency of the SD card and the MS is larger than the PCI clock frequency of 33 MHz, and there is a problem that the maximum performance cannot be obtained with the PCI clock CLKp used in the memory card interface circuit unit 102. It was.
Therefore, as shown in FIG. 7, there is a method in which a clock used in the memory card interface circuit unit 102 is supplied from an external oscillator 135. However, in such a method, it is necessary to provide an external oscillator 135, which not only leads to an increase in cost, but also the clock supplied to the SD card interface circuit 111 and the MS interface circuit 112 has a single frequency.

  Therefore, for example, in order to be able to use the SD card and the MS, it is necessary to input from the oscillator 135 a clock having an MS clock frequency of 40 MHz which is slower than the SD card clock frequency of 50 MHz. There was a problem that the performance of the card deteriorated. Further, an external oscillator may be provided corresponding to each of the SD card interface circuit 111 and the MS interface circuit 112 to supply a clock having an optimum frequency. There is a problem that it is necessary to provide an additional oscillator and the cost is significantly increased.

  The present invention generates clocks corresponding to various small memory cards from clocks generated by a PLL circuit in an IEEE 1394 interface circuit forming a high-speed serial interface, and generates the generated clocks for the respective small memory cards. An object of the present invention is to provide a memory card controller that can improve the performance and reduce the cost without increasing the power consumption by supplying it corresponding to the interface circuit.

The memory card controller according to the present invention is necessary for each memory card interface circuit section having each memory card interface circuit for correspondingly interfacing with different types of connected memory cards, and for each memory card interface circuit. In a memory card controller comprising a high-speed serial interface circuit unit that interfaces with a connected device that generates and uses a first clock having a frequency higher than the frequency of each clock
Each frequency dividing circuit that divides the first clock by a different predetermined frequency dividing ratio so as to obtain a desired operating frequency of the corresponding memory card and supplies the frequency dividing circuit to the corresponding memory card interface circuit. Having a frequency divider circuit section ,
Each of the memory card interface circuits performs an interface between a corresponding memory card and a host device that controls the operation of the memory card, and either one of the first clock and a second clock supplied from the host device. A clock switching control circuit unit that exclusively selects and outputs one of the clocks, and the clock switching control circuit unit outputs the first clock to each of the frequency dividing circuits when the first clock is selected; wherein the second case where the clock is selected, it is shall be output the second clock to the interface circuit for each memory card.

  In this case, the second clock has a frequency lower than the frequency of at least one of the clocks required for each memory card interface circuit.

  In addition, the clock switching control circuit unit exclusively selects and outputs either the first clock or the second clock based on a command input from the host device.

  Further, the clock switching control circuit unit selects and outputs the second clock when the input of the first clock is stopped.

  The clock switching control circuit unit receives a third clock from an external oscillator, and is one of the first clock, the second clock, and the third clock based on a command input from the host device. When the third clock is selected, the third clock is output to each of the frequency divider circuits.

  The clock switching control circuit unit outputs the first clock after the frequency of the input first clock is stabilized when the first clock is selected when the first clock generation is started by the high-speed serial interface circuit unit.

  The clock switching control circuit unit prohibits the output stop operation of the first clock when at least one of the connected memory cards is operating with respect to the high-speed serial interface circuit unit. When the access to the memory card is completed, the prohibition of the first clock output stop operation is canceled.

  According to the memory card controller of the present invention, the first clock generated by the high-speed serial interface circuit unit is divided by different predetermined frequency division ratios and supplied to the corresponding memory card interface circuits. Since the frequency dividing circuit portion including the circuit is provided, the performance can be improved and the cost can be reduced without increasing the power consumption.

  Further, even if the frequency of the second clock from the host device is low, better performance can be obtained. Even if the supply of the first clock is stopped, access to the memory card is prevented by supplying the second clock. The low power consumption mode can be used as before. As described above, when it is desired to operate with low power consumption, the operation of the high-speed serial interface circuit unit is stopped, the output of the first clock is stopped, and the second clock from the host device is used. The power can be reduced most, and the performance higher than the conventional one can be obtained with the low power consumption almost equal to the conventional one.

  In addition, by allowing the third clock from the external oscillator to be input, not only can the test with the semiconductor test equipment be facilitated, but also the high-speed serial interface circuit unit is stopped when not necessary. Power consumption can be reduced.

Further, when the first clock is selected at the start of the generation of the first clock, the memory card can be stably accessed by outputting after the frequency of the input first clock is stabilized, and the memory card can be stably accessed. Can always maintain high performance.
Further, when at least one of the connected memory cards is in operation, the memory card can be stably accessed by prohibiting the output stop operation of the first clock, and the memory card is always high. Performance can be maintained.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a schematic block diagram showing a configuration example of a memory card controller according to the first embodiment of the present invention.
In FIG. 1, a memory card controller 1 includes a PCI interface circuit 2, an interface with a PCI bus 20 connected to a host device (not shown), a memory card interface circuit unit 3, and an IEEE 1394 interface circuit unit 4. I have. Further, the memory card controller 1 includes a clock switching control circuit 5, a frequency dividing circuit unit 6, and a configuration register (shown as a register in the figure) 7. Note that the memory card controller 1 may be integrated in one IC.

  The PCI interface circuit 2 is connected to the PCI bus 20 and interfaces with the PCI bus 20. The memory card interface circuit unit 3 is connected to the card slot 21 and performs an interface with a small memory card 22 such as an MS or SD card connected to the card slot 21. The memory card interface circuit unit 3 includes an SD card interface circuit (shown as an SDIF circuit in the figure) 11, an MS interface circuit (shown as an MSIF circuit in the figure) 12, and an I / O control circuit 13. The O control circuit 13 exclusively connects the card slot 21 to either the SD card interface circuit 11 or the MS interface circuit 12 in accordance with the small memory card 22 connected to the card slot 21. The IEEE 1394 interface circuit unit 4 is a high-speed serial interface circuit unit, and the clock switching control circuit 7 is a clock switching control circuit unit.

  The IEEE 1394 interface circuit unit 4 is connected to an IEEE 1394 connector (shown as a connector in the figure) 23, and performs an interface with a device connected to the IEEE 1394 connector 23. The memory card interface circuit unit 3 and the IEEE 1394 interface circuit unit 4 are respectively connected to the PCI interface circuit 2. The IEEE 1394 interface circuit unit 4 includes a PLL circuit 15 for IEEE 1394 and a PLL control circuit 16 that controls the operation of the PLL circuit 15 for IEEE 1394. The IEEE 1394 PLL circuit 15 receives a clock of 24.576 MHz from the external oscillator 24 and generates a 393.216 MHz PLL clock CLKi from the input clock. The PLL clock CLKi passes through the PLL control circuit 16. It is used in a part of the blocks of the IEEE1394 interface circuit unit 4 and is output to the clock switching control circuit 5.

  In addition to the PLL clock CLKi, the clock switching control circuit 5 receives the PCI clock CLKp via the PCI interface circuit 2 and outputs the PLL clock CLKi to the frequency divider 6 and outputs the PCI clock CLKp. In this case, the data is output to the SD card interface circuit 11 and the MS interface circuit 12, respectively. The frequency divider 6 includes an SD frequency divider 17 that is an SD card frequency divider and an MS frequency divider 18 that is an MS frequency divider, and the SD frequency divider 17 includes a clock switching control circuit 5. When the PLL clock CLKi is input, the PLL clock CLKi is divided by a predetermined frequency dividing ratio and output to the SD card interface circuit 11. Further, when the PLL clock CLKi is input from the clock switching control circuit 5, the MS frequency dividing circuit 18 divides the PLL clock CLKi by a predetermined frequency dividing ratio and outputs it to the MS interface circuit 12. The configuration register 7 is connected to the PCI interface circuit 2, and the data set in the configuration register 7 is always input to the clock switching control circuit 5.

In such a configuration, FIG. 2 is a diagram showing the flow of the clock in the case of the configuration of FIG.
As shown in FIG. 2, the clock switching control circuit 5 receives the input PCI clock CLKp according to the data set in the configuration register 7 from the host device via the PCI bus 20 and the PCI interface circuit 2. It outputs to the SD card interface circuit 11 and the MS interface circuit 12, respectively, or outputs the input PLL clock CLKi to the SD divider circuit 17 and the MS divider circuit 18, respectively. The clock switching control circuit 5 exclusively outputs either the PCI clock CLKp or the PLL clock CLKi according to the data set in the configuration register 7.

A case where the PLL clock CLKi is selected by the clock switching control circuit 5 will be described. In this case, the SD frequency dividing circuit 17 divides the input PLL clock CLKi having a frequency of 393.216 MHz by 8 for the SD card (49.152 MHz) and supplies it to the SD card interface circuit 11. Further, the MS frequency dividing circuit 18 divides the input PLL clock CLKi by 10 (39.3216 MHz) for the MS and supplies it to the MS interface circuit 12.
When the clock switching control circuit 5 selects the PCI clock CLKp, the clock switching control circuit 5 stops the supply of the clock to the SD frequency dividing circuit 17 and the MS frequency dividing circuit 18, and uses the PCI clock CLKp as the SD card interface circuit 11 and the MS frequency. Each is supplied to the interface circuit 12.

  Here, PCI power management D2 and D3 states indicating a low power consumption mode are set in the configuration register 7 from the host device via the PCI bus 20 and the PCI interface circuit 2. When the PCI power management D2 and D3 states indicating the low power consumption mode are set in the configuration register 7, the PLL control circuit 16 stops the operation of the IEEE1394 PLL circuit 15 and stops the output of the PLL clock CLKi. At the same time, when the PCI power management D2 and D3 states indicating the low power consumption mode are set in the configuration register 7, the clock switching control circuit 5 selects the PCI clock CLKp and uses the PCI clock CLKp as the SD card interface circuit 11. And the MS interface circuit 12. In addition, when the IEEE1394 PLL circuit 15 starts operating after returning from the low power consumption mode or the like, the clock switching control circuit 5 selects the PLL clock CLKi after the PLL clock CLKi becomes stable and selects the PCI. Output exclusively instead of the clock CLKp.

  When the clock switching control circuit 5 selects and outputs the PCI clock CLKp, for example, when the supply of the PLL clock CLKi is stopped, the performance is lower than when the PLL clock CLKi is used by switching to the PCI clock CLKp. However, there is an advantage that the access restriction to the small memory card 22 is not required and the low power consumption mode can be used as before. As a method for causing the clock switching control circuit 5 to perform clock switching, it is automatically performed by hardware as described above, or notification that the hardware can be switched to the software side by an interrupt output or the like. A method in which software sets internal registers (not shown) provided in the SD card interface circuit 11 and the MS interface circuit 12 can be considered.

Further, the clock switching control circuit 5 refers to the setting of an internal register (not shown) provided in the SD card interface circuit 11 and the MS interface circuit 12, thereby enabling a small memory connected to the card slot 21. The operation state of the card 22 is detected. In order to avoid the adverse effects of the clock switching performed by the clock switching control circuit 5 during the operation of the small memory card 22, the clock switching control circuit 5 indicates that the small memory card 22 is operating with respect to the PLL control circuit 16. Sometimes, the operation stop of the IEEE1394 PLL circuit 15 in the low power consumption mode or the like is prohibited, and the prohibition of the operation stop of the IEEE1394 PLL circuit 15 is canceled when the access to the small memory card 22 is completed. To do.
The reason for leaving the operation mode only with the PCI clock CLKp is that the power consumption can be reduced by not operating the PLL circuit 15 for IEEE1394 when the IEEE1394 device is not used.

  As long as the small memory card does not enter the low power consumption mode, etc., the device connected to the IEEE1394 connector 23 has low power consumption so that it does not require a reduction in power consumption and can be applied to a system that emphasizes performance. Even if the mode is entered, the operation of the IEEE 1394 PLL circuit 15 should not be stopped. When at least one of the small memory cards 22 connected to the card slot 21 recovers from the low power consumption mode or the like and starts to operate, the clock switching control circuit 5 causes the PLL circuit 15 for the IEEE 1394 to be connected to the PLL control circuit 16. Control for starting the operation may be set in an internal register provided in the PCI interface circuit 2.

  As described above, the memory card controller according to the first embodiment divides the clocks corresponding to the various small memory cards 22 from the PLL clock CLKi generated by the IEEE1394 PLL circuit 15 in the IEEE1394 interface circuit unit 4. Since each of the generated clocks is supplied to each of the interface circuits 11 and 12 for each small memory card, it is not necessary to provide an external oscillator. Since it is possible to supply a frequency close to the maximum operating frequency standard of each small memory card 22 without adding a PLL circuit, it is possible to improve performance without increasing power consumption. Cost can be reduced.

Second embodiment.
In the first embodiment, a clock from an external oscillator is further input to the clock switching control circuit 5, and the clock switching control circuit 5 is any one of the PCI clock CLKp, the PLL clock CLKi, or the external clock CLKe. One of them may be exclusively selected and output, and this is the second embodiment of the present invention.
FIG. 3 is a schematic block diagram showing a configuration example of the memory card controller according to the second embodiment of the present invention. In FIG. 3, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described.

3 is different from FIG. 1 in that an external clock CLKe from an external oscillator 25 is input to the clock switching control circuit 5 of FIG. 1, and the clock switching control circuit 5 includes the PCI clock CLKp and the PLL clock CLKi. Alternatively, any one of the external clocks CLKe is selected and output. Accordingly, the clock switching control circuit 5 in FIG. 1 is replaced with the clock switching control circuit 5a, and the memory card controller 1 in FIG. 1 is replaced with the memory card controller 1a.
In FIG. 3, the memory card controller 1a includes a PCI interface circuit 2, a memory card interface circuit unit 3, an IEEE 1394 interface circuit unit 4, a clock switching control circuit 5a, a frequency dividing circuit unit 6, a configuration register 7, and the like. It has. The memory card controller 1a may be integrated in one IC.

  The clock switching control circuit 5a receives the PLL clock CLKi, the PCI clock CLKp, and the external clock CLKe, respectively, and outputs the PLL clock CLKi or the external clock CLKe to the frequency divider 6 and outputs the PCI clock CLKp. In this case, the data is output to the SD card interface circuit 11 and the MS interface circuit 12, respectively. When the PLL clock CLKi or the external clock CLKe is input from the clock switching control circuit 5a, the SD frequency dividing circuit 17 divides the PLL clock CLKi or the external clock CLKe by a predetermined frequency dividing ratio, and the SD card interface circuit. 11 is output. Further, when the PLL clock CLKi or the external clock CLKe is input from the clock switching control circuit 5a, the MS frequency dividing circuit 18 divides the PLL clock CLKi or the external clock CLKe by a predetermined frequency dividing ratio, and the MS interface. Output to the circuit 12. The data set in the configuration register 7 is always input to the clock switching control circuit 5a.

In such a configuration, FIG. 4 is a diagram showing the flow of the clock in the configuration of FIG.
As shown in FIG. 4, the clock switching control circuit 5 a receives the input PCI clock CLKp according to the data set in the configuration register 7 from the host device via the PCI bus 20 and the PCI interface circuit 2. It outputs to the SD card interface circuit 11 and the MS interface circuit 12, respectively, or outputs the input PLL clock CLKi or external clock CLKe to the SD frequency divider 17 and MS frequency divider 18, respectively. The clock switching control circuit 5a exclusively outputs any one of the PCI clock CLKp, the PLL clock CLKi, or the external clock CLKe according to the data set in the configuration register 7. The frequency of the external clock CLKe may be the same frequency as the PLL clock CLKi or a different frequency. The other operation of the clock switching control circuit 5a is the same as that of the clock switching control circuit 5 in the first embodiment, and thus the description thereof is omitted.

  As described above, the memory card controller according to the second embodiment can obtain the same effects as those of the first embodiment, and can use the PCI clock CLKp and the external clock without using the PLL clock CLKi. It is also possible to operate the memory card interface circuit unit 3 using any one of CLKe. In addition, providing an input terminal for operation using the external clock CLKe can facilitate the test of the memory card controller. Regarding the setting of such a test mode, the internal register setting, Or the setting with an external terminal can be considered.

  The frequency dividing ratio in the frequency dividing circuit section 6 in each of the first and second embodiments is an example, and considering the correspondence to various memory cards, the optimum frequency dividing ratio in each card is set. It should be set.

  When a multimedia card (MMC) (registered trademark) and xD Picture Card (xD picture card) (registered trademark) are used as a small memory card, an MMC interface circuit and an xD picture are provided in the memory card interface circuit unit 3. A card interface circuit is provided, and a frequency dividing circuit for MMC that supplies a clock to the interface circuit for MMC and a frequency dividing circuit for an xD picture card that supplies a clock to the interface circuit for xD picture card are respectively divided. What is necessary is just to provide in the circuit part 6. FIG. As described above, when a memory card other than the above-described types is used, an interface circuit and a frequency dividing circuit for the memory card may be provided.

  In the description of the first and second embodiments, the case where one small memory card is connected to the card slot has been described as an example for the sake of simplicity, but this is only an example. The present invention is not limited to this, and can also be applied to cases where various types of small memory cards are simultaneously connected to the card slot.

1 is a schematic block diagram showing a configuration example of a memory card controller according to a first embodiment of the present invention. It is the figure which showed the flow of the clock in the case of the structure of FIG. It is the schematic block diagram which showed the structural example of the memory card controller in the 2nd Embodiment of this invention. FIG. 4 is a diagram showing a clock flow in the case of the configuration of FIG. 3. It is the general | schematic block diagram which showed the structural example of the conventional memory card controller. FIG. 6 is a diagram showing a clock flow in the case of the configuration of FIG. 5. It is the schematic block diagram which showed the other structural example of the conventional memory card controller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Memory card controller 2 PCI interface circuit 3 Memory card interface circuit part 4 IEEE1394 interface circuit part 5,5a Clock switching control circuit 6 Dividing circuit part 7 Configuration register 11 Interface circuit for SD card 12 Interface circuit for MS 13 I / O control circuit 15 PLL circuit for IEEE1394 16 PLL control circuit 17 SD divider circuit 18 MS divider circuit 20 PCI bus 21 Card slot 22 Small memory card 23 IEEE1394 connector 24, 25 Oscillator

Claims (7)

A memory card interface circuit unit having an interface circuit for each memory card that performs an interface with a different type of connected memory card, and a frequency higher than each clock frequency required for each interface circuit for the memory card In a memory card controller comprising a high-speed serial interface circuit unit that interfaces with a connected device that generates and uses a first clock of a frequency,
Each frequency dividing circuit that divides the first clock by a different predetermined frequency dividing ratio so as to obtain a desired operating frequency of the corresponding memory card and supplies the frequency dividing circuit to the corresponding memory card interface circuit. Having a frequency divider circuit section ,
Each of the memory card interface circuits performs an interface between a corresponding memory card and a host device that controls the operation of the memory card, and either one of the first clock and a second clock supplied from the host device. A clock switching control circuit unit that exclusively selects and outputs one of the clocks, and the clock switching control circuit unit outputs the first clock to each of the frequency dividing circuits when the first clock is selected; wherein the second case where the clock is selected, the memory card controller, wherein also be output from each of the second clock to the interface circuit for each memory card. 2. The memory card controller according to claim 1, wherein the second clock has a frequency lower than at least one frequency of each clock required by each of the memory card interface circuits . Said clock selection control circuit, based on the input instruction from the host apparatus, according to claim 1, characterized in that output exclusively selected and one of the first clock or the second clock or 2. The memory card controller according to 2. 4. The memory card controller according to claim 1, wherein the clock switching control circuit unit selects and outputs the second clock when the input of the first clock is stopped . The clock switching control circuit unit receives a third clock from an external oscillator, and outputs one of the first clock, the second clock, and the third clock based on a command input from the host device. 5. The memory card controller according to claim 4 , wherein when the third clock is selected exclusively, the third clock is output to each of the frequency dividing circuits . The clock switching control circuit unit, when the first clock is selected at the start of generation of the first clock by the high-speed serial interface circuit unit, outputs after the frequency of the input first clock is stabilized. Item 6. The memory card controller according to Item 1, 2, 3, 4, or 5. The clock switching control circuit unit prohibits the output stop operation of the first clock when at least one of the connected memory cards is operating with respect to the high-speed serial interface circuit unit . 7. The memory card controller according to claim 1, wherein the prohibition of the output stop operation of the first clock is canceled when the access to the memory card is completed .

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