JP4957122B2 - Power supply circuit and imaging apparatus - Google Patents

Description

  The present invention relates to a power supply circuit and an imaging apparatus equipped with the power supply circuit.

  The following semiconductor integrated circuit for power supply control is known. This semiconductor integrated circuit for power supply control improves the power efficiency by switching the slew rate of the control signal that controls the power transistor of the switching regulator based on the signal indicating the operating state of the device that is susceptible to noise. (For example, Patent Document 1).

JP 2006-129593 A

  However, in the switching regulator provided in the conventional circuit, when the target output voltage is included in the range of the input voltage, the input voltage is once increased to the output voltage or more by using a booster circuit and a step-down circuit or a buck-boost circuit. After boosting, it is necessary to step down to the target output voltage, which may reduce power supply efficiency.

The power supply circuit according to the invention of claim 1 is a power supply circuit that adjusts and outputs an input voltage, and boosts and outputs the input voltage to a target voltage set within a fluctuation range of the input voltage; Measuring means for measuring an input voltage; and when the measured input voltage is less than a first value, the target voltage is changed to a first target value, and the measured input voltage is a first value. And changing means for changing the target voltage to a second target value larger than the first target value , wherein the first target value is the first value, The target value is substantially the maximum value within the fluctuation range of the input voltage .
An image pickup apparatus according to a second aspect of the present invention includes: an image pickup element that picks up a subject image; an image processing circuit that performs image processing on an image signal output from the image pickup element; and the power supply circuit according to claim 1. The power supply circuit outputs an output voltage to at least one of the image sensor and the image processing circuit.

  According to the present invention, an output voltage can be generated without reducing power supply efficiency.

  FIG. 1 is a block diagram illustrating a configuration of an embodiment of a digital camera according to the present embodiment. The digital camera 100 includes a lens barrel 1, a CCD 2, an AFE circuit 3, a motor 4, a motor DrIC 5, a TFT (display device) 6, a voice input / output device 7, a DSP / CPU 8, an SDRAM 9, and a flash. A memory 10, a card I / F 11, an operation member 12, a power supply circuit 13, and a battery 14 are provided.

  The lens barrel 1 is a unit in which a zoom lens and an AF lens are incorporated. The zoom lens and the AF lens are driven by the motor 4, and the respective lens positions are adjusted. The motor 4 is electrically controlled by the motor DrIC5. The CCD 2 that is an image pickup device picks up an object image incident through the lens barrel 1 and outputs an analog image signal. An AFE (Analog Front End) circuit 3 is an analog image processing circuit. After analog processing such as gain control is performed on the analog image signal output from the CCD 2, A / D conversion is performed to convert the digital image signal. Output.

  The digital image signal output from the AFE circuit 3 is subjected to various image processing by the DSP / CPU 8 and then compressed into a predetermined file format, for example, Jpeg format, and recorded in the SDRAM 9 as a buffer memory. The DSP / CPU 8 records the image file recorded in the SDRAM 9 on a recording medium such as a flash memory 10 or a memory card inserted in the card I / F 11. It is assumed that whether the image file is recorded in the flash memory 10 or the memory card inserted in the card I / F 11 is set in advance by the user.

  The TFT 6 is a rear liquid crystal monitor, for example, and displays image data output from the DSP / CPU 8. The voice input / output device 7 includes, for example, a microphone and a speaker, and takes in surrounding sounds through the microphone, and outputs operation sounds and voices during moving image reproduction through the speakers. The operation member 12 is operated by a user, and includes, for example, a release switch and various operation buttons. The DSP / CPU 8 controls the digital camera 100 by executing processing corresponding to the operation content based on the operation of the operation member 12 by the user.

  The power supply circuit 13 outputs the battery voltage (input voltage) supplied from the battery 14 to the elements 2 to 12 described above. At this time, since each element requires different voltages, the power supply circuit 13 converts the battery voltage supplied from the battery 14 into a voltage (output voltage) required by each output destination, Output to element. In the present embodiment, the battery 14 is, for example, two AA batteries, and the battery voltage in this case is in the range of + 1.7V to + 3.5V.

  FIG. 2 is a block diagram showing a configuration of an embodiment of the power supply circuit 13. The power supply circuit 13 includes a booster circuit, an inverting circuit, and a step-down circuit for converting an input voltage into an output voltage for outputting to each of the elements 2 to 12. FIG. 2 shows an example of outputting to CCD 2, AFE 3, motor 4, DSP / CPU 8, SDRAM 9, and flash memory 10 out of each of elements 2 to 12. In the present embodiment, the input voltage is applied to these elements. A case of converting to an output voltage for output to each element will be described. In FIG. 2, output voltages for output to the DSP / CPU 8, SDRAM 9, and flash memory 10 are collectively referred to as “logic”.

  The power supply circuit 13 includes booster circuits A to C, an inverting circuit D, and step-down circuits E and F. The booster circuits A to C are circuits for generating a desired high output voltage from a low input voltage. The inverting circuit D is a circuit for generating a negative output voltage from a positive input voltage. The step-down circuits E and F are circuits for generating a desired low output voltage when the input voltage is higher than the desired output voltage.

  In this embodiment, when the input voltage is within the range of +1.7 V to +3.5 V, the output voltage for the motor 4 is +5 V, the output voltage for the AFE 3 is +3.3 V to +3.5 V, and the output voltage for the CCD 2 is The case where the output voltages are + 12V and −7V and the output voltage for logic is + 1.5V and + 3.3V will be described.

  The step-up circuit A generates an output voltage (+ 5V) for the motor 4 from the input voltage and outputs it to the motor 4. The booster circuit B generates an output voltage (+3.3 V to +3.5 V) for the AFE 3 from the input voltage and outputs it to the AFE 3. The booster circuit C generates an output voltage (+ 12V) for the CCD 2 from the input voltage and outputs it to the CCD 2. The inverting circuit D generates an output voltage (−7V) for the CCD 2 from the input voltage and outputs it to the CCD 2. The step-down circuit E generates a logic output voltage (+1.5 V) from the input voltage and outputs it to the DSP / CPU 8. The step-down circuit F generates a logic output voltage (+3.3 V) from the boosted voltage (+5 V) output from the step-up circuit A and outputs it to the DSP / CPU 8, SDRAM 9, and flash memory 10.

  The output voltage for the AFE 3 is generally + 3.3V, but in this embodiment, it is set to + 3.3V to + 3.5V. The power supply specifications of the AFE 3 and peripheral circuits are type (standard value) + 3.3V and max (maximum value) + 3.6V, so that the output voltage can be designed to be + 3.3V to + 3.5V. There is no problem. If the output voltage for AFE3 is kept at + 3.3V, as shown in FIG. 3, similarly to the output voltage for logic (+ 3.3V), the voltage from the + 5V voltage generated by the booster circuit A is reduced. It is necessary to generate + 3.3V at B2 and output it to AFE3. In the case of such a configuration, there arises a problem that power supply efficiency is lowered. For example, when the power supply efficiency is 90% for both the booster circuit A and the step-down circuit B2, the power supply efficiency is reduced to 90% × 90% = 81%.

  In addition to generating the output voltage for the AFE 3 by combining the booster circuit A and the step-down circuit B, a step-up / step-down circuit for generating a desired output voltage from the input voltage by performing step-up and step-down may be used. In this case, however, there arises a problem that the circuit scale becomes large. Further, when switching from the step-up operation to the step-down operation, and when switching from the step-down operation to the step-up operation, noise is generated in the output voltage. For example, as shown in FIG. 4, when the input voltage is larger than + 3.3V, the step-down operation is performed to generate the output voltage for AFE3, and when the input voltage falls below + 3.3V, the operation is switched to the step-up operation. To generate an output voltage for AFE3. At this time, noise is generated in the output voltage at the point X when the step-down operation is switched to the step-up operation. There is a risk that the image being captured is disturbed due to this noise.

  In order to avoid such problems, in this embodiment, the output voltage for AFE 3 is selected from + 3.3V and + 3.5V. As a result, when the input voltage is +3.3 V or higher, the booster circuit B may boost the input voltage to 3.5 V that matches the maximum value of the input voltage, and the output voltage is less than +3.3 V. In such a case, the booster circuit B may boost the input voltage to 3.3 V and output it. That is, the output voltage for the AFE 3 can be generated using only the booster circuit B, and there is no need to use a combination of the booster circuit and the step-down circuit or use a step-up / down circuit as in the prior art.

  Note that the output voltage of the booster circuit is designed in consideration of the value of the voltage drop caused by the booster circuit itself. Although the maximum value of the set value of the output voltage of the booster circuit B in the present embodiment is +3.5 V, which is the maximum value of the input voltage, it is not limited to this. The maximum value of the set value of the output voltage of the booster circuit B may be approximately + 3.5V. For example, considering the voltage drop caused by the above-described booster circuit B itself, + 3.45V may be used instead of + 3.5V. Moreover, it is good also as + 3.6V which is the maximum value of the power supply use of AFE3 instead of + 3.5V.

  In FIG. 2, as for the output voltage for logic (+3.3 V) output from the step-down circuit F, the voltage stepped up by the step-up circuit A is the same as the output voltage for the AFE 3 described in FIG. The voltage is stepped down by F to generate a desired voltage. Therefore, if it remains as it is, the same problems as in the conventional case will occur. Therefore, when the output voltage for logic can be set to + 3.3V to + 3.5V, the output is made by using only the booster circuit B in the same manner as the output voltage for AFE3 by designing as described above. A voltage can be generated.

  Next, the booster circuit B in the present embodiment will be described. FIG. 5 is a block diagram showing a configuration of a conventional general booster circuit. Such a booster circuit has a circuit configuration in which the input voltage and the coil L are added in series in order to obtain an output voltage (Vout) higher than the input voltage from the battery 14. First, by turning on the transistor Tr, a charging current is passed to accumulate energy in the coil L. Next, when the transistor Tr is turned off, an electromotive force is generated in the coil L by the stored energy, and a discharge current is supplied to Vout at a voltage higher than the input voltage to raise the output voltage.

  The output voltage output at this time is adjusted by the PWM controller. That is, the PWM controller adjusts the output voltage so as to be a target voltage determined by the resistance values of the resistors R1 and R2. The PWM controller stabilizes the output voltage by adjusting the energy accumulated depending on the ON time of the transistor Tr.

  In such a conventional booster circuit, since the target value of the output voltage is determined by the resistance values of the resistors R1 and R2, the output voltage cannot be changed according to the conditions. That is, in the conventional booster circuit, when the input voltage is + 3.3V or more, the output voltage needs to be + 3.5V, and when the input voltage is less than + 3.3V, the output voltage needs to be + 3.3V. A certain booster circuit B cannot be realized. Therefore, in the present embodiment, as shown in FIG. 6, a resistor group for determining the target value of the output voltage is provided outside the booster circuit B, and the resistors R2 and R3 are switched by the CPU 13a included in the power supply circuit 13. Two types of target values can be set. The resistor R2 is for setting the target value of the output voltage to + 3.3V in combination with the resistor R1, and the resistor R3 is set to have the target value of the output voltage of + 3.5V in combination with the resistor R1. It is for setting.

  In the configuration example shown in FIG. 6, the CPU 13 a measures the input voltage from the battery 14 by controlling the A / D 13 b when the input voltage of the power supply circuit 13 is stabilized. In the present embodiment, the A / D 13b measures the input voltage assuming that the voltage of the digital camera 100 is stable in the following cases (1) to (3).

(1) When the power supply (main switch) of the digital camera 100 is turned on by the user The power supply (main switch) is turned on when the user operates the main switch to turn it on. When the main switch is off, power is supplied only to the IC that detects the main switch on in the DSP / CPU 8. The DSP / CPU 8 periodically monitors the state of the main switch. When the DSP / CPU 8 detects that the main switch is turned on, the DSP / CPU 8 outputs a power supply command to the power supply circuit 13. The power supply circuit 13 supplies power to each circuit other than the above-described IC of the digital camera 100 in accordance with a power supply command.

  When the power of the digital camera 100 is turned on, as shown in FIG. 7A, the DSP / CPU 8 is initialized, and the CCD 2 starts to be driven when power is supplied. Thereafter, when the power is supplied, the backlight (BL) starts to be driven, and the DSP / CPU 8 displays a viewfinder image on the TFT 6. At this time, when a predetermined time elapses after power is supplied to the CCD 2, the input voltage of the power supply circuit 13 is stabilized. Therefore, the DSP / CPU 8 outputs a timing signal indicating the input voltage measurement start timing to the CPU 13a at a timing T1 after a predetermined time from the start of driving of the CCD 2. When the CPU 13a detects the timing signal, the A / D 13b measures the input voltage.

  The DSP / CPU 8 displays a viewfinder image by converting a digital image signal captured by the CCD 2 and output from the AFE circuit 3 into a display signal and outputting it to the TFT 6 at a predetermined frame rate.

(2) When the sleep mode is canceled by the user The sleep mode is a low power consumption mode of the digital camera 100. The release of the sleep mode refers to switching from a low power consumption mode to a state where power is supplied to each circuit when the user operates the operation member 12 (for example, a half-press operation of the shutter release button). In the sleep mode, power is supplied only to the IC that detects the operation of each operation member 12 in the DSP / CPU 8. The DSP / CPU 8 periodically monitors the state of each operation member 12. When the DSP / CPU 8 detects that the operation member 12 has been operated, the DSP / CPU 8 outputs a power supply command to the power supply circuit 13. The power supply circuit 13 supplies power to each circuit other than the above-described IC in the digital camera 100 in accordance with a power supply command.

  FIG. 7B shows a flow from when the digital camera 100 shifts to the sleep mode until the sleep mode is canceled. When the backlight is driven and the viewfinder image is displayed on the TFT 6 and the mode is shifted to the sleep mode, the power supply is stopped and the CCD 2 and the backlight are stopped driving. The DSP / CPU 8 enters a standby state in which the state of each operation member 12 is periodically monitored. Thereafter, when the sleep mode is canceled due to the operation of the operation member 12 by the user, the DSP / CPU 8 returns from the standby state to the photographing mode. Then, after the CCD 2 starts to be driven by supplying power, the backlight (BL) starts to be driven by supplying power, and the DSP / CPU 8 displays a viewfinder image on the TFT 6.

  At this time, when a predetermined time elapses after power is supplied to the CCD 2, the input voltage of the power supply circuit 13 is stabilized. Therefore, the DSP / CPU 8 outputs a timing signal indicating the input voltage measurement start timing to the CPU 13a at a timing T2 after a predetermined time from the start of driving of the CCD 2. When the CPU 13a detects the timing signal, the A / D 13b measures the input voltage.

  Note that the sleep mode may be realized by the following configuration. Each circuit (CCD2, AFE3, etc.) itself has two modes, a normal mode and a low power consumption mode. The power supply circuit 13 supplies power to each circuit regardless of whether the digital camera 100 is in the sleep mode. In the low power consumption mode of each circuit, each circuit consumes a minimum amount of power even when it is supplied with power from the power supply circuit 13, and is not substantially driven. In this state, each circuit substantially stops its normal function. In the normal mode of each circuit, each circuit is driven by receiving power supply from the power supply circuit 13. In this state, each circuit performs a normal function.

  In this configuration, the DSP / CPU 8 outputs a sleep command to each circuit, so that the digital camera 100 shifts to the sleep mode. Specifically, the DSP / CPU 8 outputs a sleep command by writing the sleep mode setting in a register of each circuit. Each circuit switches to the sleep mode (low power consumption mode) as described above in accordance with the sleep command. Further, the DSP / CPU 8 outputs a sleep release command to each circuit, whereby the digital camera 100 is released from the sleep mode. Specifically, the DSP / CPU 8 outputs a sleep cancel command by writing the sleep cancel setting to the register of each circuit. Each circuit switches to the normal mode as described above in accordance with the sleep release instruction.

(3) When an instruction to shift to a shooting mode for displaying the viewfinder image on the TFT 6 is issued from a state where the viewfinder image is not displayed on the TFT 6, FIG. 7C shows the display of the viewfinder image on the TFT 6. The flow when non-display is switched is shown. When the backlight is driven and the viewfinder image is displayed on the TFT 6 and the user operates the operation member 12 to instruct the display of the menu screen or the reproduction of the image, the power supply is stopped. As a result, the CCD 2 stops driving, and a menu screen and a reproduced image are displayed on the TFT 6.

  Thereafter, when the DSP / CPU 8 detects that the user has operated the operation member 12 to select the photographing mode, the CCD 2 starts driving (starts up) when power is supplied, and the DSP / CPU 8 displays the view on the TFT 6. Display the viewfinder image. At this time, the input voltage of the power supply circuit 13 is stabilized when a predetermined time has elapsed from the start of driving of the CCD 2. Therefore, the DSP / CPU 8 outputs a timing signal indicating the input voltage measurement start timing to the CPU 13a at a timing T3 after a predetermined time from the start of driving of the CCD 2. When the CPU 13a detects the timing signal, the A / D 13b measures the input voltage. Further, the DSP / CPU 8 displays the viewfinder image on the TFT 6 at the timing of T3. The viewfinder image is displayed at the timing T3 when the power supply circuit 13 is stabilized. Therefore, a stable viewfinder image is displayed on the TFT 6.

  Note that the timing of transition to the shooting mode may be after a predetermined time is counted by a timer from the start of display of the menu screen or the playback screen.

  When the input voltage measured by the A / D 13b is less than + 3.3V, the CPU 13a controls the switch 13c to connect to the resistor R2, and sets the target value of the output voltage to + 3.3V. On the other hand, when the input voltage measured by the A / D 13b is + 3.3V or more, the CPU 13a controls the switch 13c to connect the circuit to the resistor 3 and sets the target value of the output voltage to + 3.5V. Set to.

  As described above, by using the power supply circuit 13 in the present embodiment, the booster circuit B can generate the output voltage for the AFE 3 in accordance with the value of the input voltage. That is, it is not necessary to combine a booster circuit and a step-down circuit or use a step-up / step-down circuit as in a conventional power supply circuit. As a result, it is possible to prevent a reduction in power supply efficiency caused by combining the booster circuit and the step-down circuit. Furthermore, the problem that the circuit scale generated by using the step-up / step-down circuit becomes large and the problem that noise occurs in the output voltage can be solved.

  FIG. 8 is a flowchart showing processing of the digital camera 100 in the present embodiment. The processing shown in FIG. 8 is executed by the CPU 13a included in the power supply circuit 13 at the input voltage measurement timing described in (1) to (3).

  In step S10, the CPU 13a acquires the input voltage measurement result from the A / D 13b. Then, it progresses to step S20 and it is judged whether an input voltage is + 3.3V or more. When determining that the input voltage is + 3.3V or higher, the CPU 13a controls the switch 13c to connect to the resistor 3, and sets the target value of the output voltage to + 3.5V. On the other hand, when determining that the input voltage is less than + 3.3V, the CPU 13a controls the switch 13c to connect to the resistor R2, and sets the target value of the output voltage to + 3.3V. Thereafter, the process ends.

According to the present embodiment described above, the following operational effects can be obtained.
(1) The output voltage for AFE 3 corresponding to the input voltage is generated using only the booster circuit B. As a result, it is possible to prevent a reduction in power supply efficiency caused by combining the booster circuit and the step-down circuit. Moreover, the problem that the circuit scale generated by using the step-up / step-down circuit becomes large and the problem that noise occurs in the output voltage can be solved. And disturbance of the picked-up image resulting from the noise of an output voltage can be suppressed.

(2) The output voltage for the AFE 3 is set to +3.3 V to +3.5 V so that the output voltage and the maximum voltage of the input voltage coincide within the input voltage fluctuation range (+1.7 V to +3.5 V). I did it. Thus, when the input voltage is +3.3 V or more, the input voltage may be boosted to 3.5 V by the booster circuit B and output. When the input voltage is less than +3.3 V, the booster circuit is sufficient. The input voltage may be boosted to 3.3V at B and output.

(3) When the input voltage measured by the A / D 13b is less than + 3.3V, the CPU 13a controls the switch 13c to connect to the resistor R2 and set the target value of the output voltage to + 3.3V. I made it. Further, when the input voltage measured by the A / D 13b is + 3.3V or higher, the switch 13c is controlled and connected to the resistor 3, and the target value of the output voltage is set to + 3.5V. As a result, the output voltage for AFE 3 corresponding to the input voltage can be generated using only the booster circuit B.

(4) The A / D 13b measures the input voltage when the power of the digital camera 100 is turned on by the user (the main switch is turned on). That is, after the power of the digital camera 100 is turned on and the initialization of the DSP / CPU 8 is completed, the input voltage is measured at the timing of T1 after a predetermined time from the start of driving of the CCD 2 by supplying power. I tried to do it. As a result, the input voltage can be measured at an optimal timing in consideration of the stabilization of the input voltage of the power supply circuit 13 after a predetermined time has elapsed since the power was supplied to the CCD 2.

(5) The A / D 13b measures the input voltage when the sleep mode is canceled by the user. That is , after the DSP / CPU 8 returns from the standby state to the photographing mode, the input voltage is measured at a timing T2 after a predetermined time has elapsed since the CCD 2 started to be driven by supplying power. As a result, the input voltage can be measured at an optimal timing in consideration of the stabilization of the input voltage of the power supply circuit 13 after a predetermined time has elapsed since the power was supplied to the CCD 2.

(6) The A / D 13b measures the input voltage when an instruction to shift to a shooting mode in which the viewfinder image is displayed on the TFT 6 from the state where the viewfinder image is not displayed on the TFT 6 is given. That is, the input voltage is measured at a timing T3 after a predetermined time from the start of driving of the CCD 2. As a result, the input voltage can be measured at an optimum timing, taking into account that the input voltage of the power supply circuit 13 is stabilized after a predetermined time has elapsed since the power was supplied to the CCD 2.

-Modification-
The digital camera according to the above-described embodiment can be modified as follows.
(1) In the above-described embodiment, the case where two AA batteries are used as the battery 14 and the battery voltage is in the range of +1.7 V to +3.5 V has been described. In this case, since the output voltage for AFE3 falls within the input voltage range as described above, the output voltage for AFE3 is set to +3.3 V to +3.5 V, and booster circuit B is configured as shown in FIG. The target value of the output voltage is set according to the input voltage. However, when another battery is used as the battery 14, the target value of the output voltage to other elements whose output voltage is within the range of the battery voltage may be set according to the input voltage.

  For example, when 8 AA batteries are used as the battery 14, the battery voltage is + 6.8V to + 14V. Therefore, the output voltage (+ 12V) for the CCD 2 output by the booster circuit C is the input voltage. Within range. Therefore, in this case, the output voltage of the CCD 2 is set to + 12V to + 14V, and the booster circuit C is configured as shown in FIG. When the input voltage is less than + 12V, the target value of the output voltage generated by the booster circuit C is set to + 12V. When the input voltage is + 12V or more, the output voltage generated by the booster circuit C is The target value may be set to + 14V.

(2) In the above-described embodiment, when the power of the digital camera 100 is turned on, when the digital camera 100 returns from the sleep mode, and when any viewfinder image is not displayed on the TFT 6. A / D 13b explained the example of measuring the input voltage. However, the A / D 13b may measure the input voltage at other times when the voltage of the digital camera 100 is stabilized.

(3) In the above-described embodiment, the example in which the power supply circuit 13 is mounted on the digital camera 100 has been described. However, you may make it mount in apparatuses other than a digital camera.

  Note that the present invention is not limited to the configurations in the above-described embodiments as long as the characteristic functions of the present invention are not impaired.

It is a block diagram which shows the structure of one Embodiment of a digital camera. It is a block diagram which shows the structure of the power supply circuit 13 in this Embodiment. It is a block diagram which shows the structure of the conventional power supply circuit. It is a figure which shows the specific example of the noise generation in a buck-boost circuit. It is a block diagram which shows the structure of the conventional booster circuit. It is a block diagram which shows the structure of one Embodiment of the booster circuit B and its peripheral circuit in this Embodiment. It is a figure which shows the specific example in case the voltage of the digital camera 100 is stabilized. 2 is a flowchart showing processing of the digital camera 100. FIG.

Explanation of symbols

100 digital camera, 1 lens barrel, 2 CCD, 3 AFE circuit, 4 motor, 5 motor DrIC, 6 TFT, 7 voice input / output device, 8 DSP / CPU, 9 SDRAM, 10 flash memory, 11 card I / F, 12 Operation member, 13 power supply circuit, 14 battery

Claims (5)

In the power supply circuit that adjusts and outputs the input voltage,
Boosting means for boosting and outputting the input voltage to a target voltage set within the fluctuation range of the input voltage;
Measuring means for measuring the input voltage;
When the measured input voltage is less than a first value, the target voltage is changed to a first target value, and when the measured input voltage is greater than or equal to a first value, the target voltage is Changing means for changing to a second target value larger than the first target value ,
The power supply circuit according to claim 1, wherein the first target value is the first value, and the second target value is a substantially maximum value within a fluctuation range of the input voltage . An image sensor for capturing a subject image;
An image processing circuit for performing image processing on an image signal output from the image sensor;
A power supply circuit according to claim 1 ,
The power supply circuit outputs an output voltage to at least one of the image sensor or the image processing circuit. The imaging device according to claim 2 ,
The imaging device is characterized in that the measuring means measures the input voltage after a main switch of the imaging device is turned on or after a low power consumption mode of the imaging device is released. The imaging device according to claim 2 ,
A signal output means for converting the image signal output from the image sensor into a display signal and outputting it at a predetermined frame rate;
Display means for displaying a finder image based on the display signal output from the signal output means;
A mode transition instruction means for instructing transition to a shooting mode for displaying the finder image in a state where the finder image is not displayed on the display means;
The imaging apparatus is characterized in that the measuring means measures the input voltage based on the mode transition instruction means instructing the transition to the photographing mode. The imaging apparatus according to claim 4 ,
Based on the mode transition instruction means instructing the transition to the photographing mode, the image sensor is started by starting the power supply from the power supply circuit to the image sensor, and the driving of the signal output means is started. Control means for causing the display means to start displaying the finder image by instructing
The imaging apparatus measures the input voltage during a period after the imaging device is activated and until the finder image starts to be displayed on the display unit.

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