JP4953794B2 - Bus arbitration method for bus system and bus system - Google Patents

Description

  The present invention relates to a bus system using a bus arbitration device that preferentially arbitrates access from a master having a strict deadline until a deadline to a slave. In particular, in a bus system in which there are a plurality of buses to be arbitrated by a bus arbitration device and are configured in multiple stages via a bridge, the bus system includes a bus arbitration device that notifies the urgent evaluation value of the master between the bus arbitration devices About.

  Usually, the master needs to complete the transfer of the requested amount of data within the requested time. If the amount of data to be transferred is large for the requested time, the master's deadline guarantee is strict. Conversely, if the amount of data to be transferred is small for the requested time, deadline guarantee is easy. .

  For example, Patent Literature 1 describes a bus arbitration device that preferentially allocates a bus to a device that is behind the reference. For this allocation, the bus arbitration device disclosed in Patent Document 1 includes a reference counter that operates with a clock based on a transfer rate required for each device, and a transfer data counter that measures the amount of data actually transferred. Provide. The values of these two counters are compared during bus arbitration.

  In order to guarantee a deadline, we proposed a deadline guarantee arbiter as shown in FIG. 4 (for example, Japanese Patent Application No. 2005-314842). The deadline guarantee arbiter sets the data amount to be transferred and the time until the data transfer is completed as shown in FIG. 5 for each master in the data amount setting register and the deadline setting register. Here, (A) to (C) shown in FIG. 5 correspond to master A to master C, respectively.

  The deadline guarantee arbiter calculates the urgency evaluation value (= remaining data amount / remaining time) for each master and gives priority to the master that needs the bus right most to guarantee the deadline. And give the bus right. In the example shown in FIG. 5, the urgency evaluation values A1, B1, and C1 at time t1 are obtained as follows, and A1> C1> B1. At time t1, master A> master C> master B has priority. The bus right is given at a degree.

A1 = (transfer data amount a−d1a) ÷ (deadline a−t1)
= 0.75
B1 = (transfer data amount b−d1b) ÷ (deadline b−t1)
= 0.38
C1 = (transfer data amount c−d1c) ÷ (deadline c−t1)
= 0.46
As a result of master A having priority over masters B and C and acquiring the bus right until time t2, urgency evaluation values A2, B2, and C2 at time t2 are obtained as follows, and B2>A2> C2. Therefore, at the time t2, the bus right is given with the priority of master B> master A> master C.

A2 = (transfer data amount a−d2a) ÷ (deadline a−t2)
= 0.59
B2 = (transfer data amount b−d2b) ÷ (dead line b−t2)
= 0.7
C2 = (transfer data amount c−d2c) ÷ (deadline c−t2)
= 0.1
In this way, the deadline guarantee arbiter shortens the time to acquire the bus right and guarantees the master's deadline by preferentially using the bus by the master having the severest deadline at a certain point in time. That is, the deadline guarantee arbiter can guarantee a deadline for the master-slave pair.

  For example, in the system configuration shown in FIG. 6, when the master A10 and the master B11 request data transfer to the slave 18, the deadline guarantee arbiter P16 first arbitrates the right to use the bus between the master A10 and the master B11. . As a result of the arbitration, when the master A 10 has obtained the right to use the bus, the urgency evaluation value of the master A 10 is notified to the bridge 15 connecting the P bus 19 and the Q bus 20.

Next, the bridge 15 tries to acquire the right to use the Q bus 20 based on the urgency evaluation value from the master A10. Then, the deadline guarantee arbiter Q17 calculates the urgency evaluation value among the bridge 15, the master C12, and the master D13 that are requests from the P bus 19, and determines the master that accesses the slave 18 using the Q bus 20. .
Japanese Patent Laid-Open No. 10-289203

  However, in the system configuration shown in FIG. 6, when each deadline guarantee arbiter operates independently, the following problem occurs. Even if the master A10 makes a request with a low urgency evaluation value and the urgency evaluation value is notified to the bridge, if a request with a high urgency evaluation value is received from the master C12 and the master D13, the master A10 will always The right to use the Q bus 20 cannot be acquired. Even if the master B11 requests with a high urgency evaluation value, the deadline assurance arbiter Q17 uses the urgent evaluation value from the master A10, so that there is a possibility that the deadline for the request of the master B11 cannot be guaranteed. is there.

  An object of the present invention is to give a bus use right to a master having a transfer request with the highest priority in response to transfer requests from a plurality of masters generated on a plurality of buses.

  Another object of the present invention is to guarantee the master's deadline by always using the master's urgency evaluation value with the strictest deadline guarantee.

The present invention provides a bridge that connects a first bus and a second bus, a first bus arbitration device that arbitrates the right to use the first bus, and arbitrates the right to use the second bus. A bus arbitration method of a bus system comprising a second bus arbitration device, wherein the first bus arbitration device issues a transfer request from a first master connected to the first bus, and the first bus If the second master connected to the network does not issue a transfer request, the first master is permitted to use the first bus, and the bridge is connected to the first master by the first bus arbitration device. If the use of the first bus is permitted, a transfer request is issued to the second bus arbitration device, and the second bus arbitration device issues a transfer request from the bridge and the master connected to the second bus. , The second threshold based on the urgency of the transfer request issued by the bridge. When the urgency of the transfer request issued by the master connected to the second bus is high, the master connected to the second bus is permitted to use the second bus, and the first bus arbitration device uses the second bus by the bridge. If the second master issues a transfer request with a higher degree of urgency than the transfer request issued by the first master when use of the bus is not permitted, the emergency of the transfer request issued by the second master The second bus arbitration device notifies the second bus arbitration device of the urgent level notified from the first bus arbitration device and the transfer request issued by the master connected to the second bus. characterized in that arbitrates the right to use the second bus based on the urgency.

According to the present invention, can it to confer efficient use right of bus master to issue a high priority transfer request to transfer requests from a plurality of masters generated on multiple buses.

In addition, every time a request with a high degree of urgency is received from the master, the urgency level is transmitted to another bus arbitration device, so that bus arbitration can be performed using the strictest urgency level . As a result, even when the master performs a transfer with a high degree of urgency later, it is possible to guarantee a deadline for all transfers.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a bus system including a deadline guarantee arbiter (bus arbitration device) according to the present embodiment. FIG. 2 is a diagram showing an example of the configuration of the deadline guarantee arbiter in the present embodiment.

  In FIG. 1, the bus system includes a master A10, a master B11, a master C12, a master D13, a bridge 15, a slave 18, an arbiter P16, which is a deadline guarantee arbiter, an arbiter Q17, a P bus 19, and a Q bus 20.

  Master A10, master B11, master C12, and master D13 each perform transfer with a deadline.

  The arbiter P16 arbitrates the right to use the bus between the master A10 and the master B11, and the arbiter Q17 arbitrates the right to use the bus between the bridge 15, the master C12, and the master D13.

  In the present embodiment, the arbiter Q17 determines the master to which the bus use right is given in consideration of the urgency evaluation value 21 output from the arbiter P16. The processing for giving the bus use right will be described in further detail.

  As shown in FIG. 2, the arbiter P16 includes a data amount setting register 201, a deadline setting register 203, a data transfer amount counter 205, a timer 207, an urgency evaluation value calculation unit 209, and an urgency evaluation value selection unit 211 of the master A10. Have Further, the master A 10 includes an urgency evaluation value transmission unit 213 and an urgent evaluation value reception unit 215.

  Here, the data transfer amount of the master A10 is set in the data amount setting register 201, and the time for performing the data transfer of the master A10 is set in the deadline setting register 203. The data transfer amount counter 205 decrements the data amount that the master A 10 has completed transfer from the setting value of the data amount setting register 201 and counts the remaining data amount. The timer 207 starts counting down from the time stored in the deadline setting register 203 after the first slave access request arrives from the master A10, and outputs the remaining time. The urgency evaluation value calculation unit 209 calculates the urgency evaluation value by dividing the remaining data amount counted by the data transfer amount counter 205 by the remaining time output by the timer 207.

  The urgency evaluation value selection unit 211 compares the urgency evaluation value calculated by the urgency evaluation value calculation unit 209 with the urgency evaluation value received by the urgency evaluation value reception unit 215, and has the highest urgency level. Choose one. The urgency evaluation value transmission unit 213 transfers the urgency evaluation value 301 output from the urgency evaluation value calculation unit 209 to another deadline guarantee arbiter. The urgency evaluation value receiving unit 215 receives the urgency evaluation value 303 transferred from another deadline guarantee arbiter, and notifies the urgency evaluation value selection unit 211 of the urgency evaluation value.

  Similarly, the arbiter P16 includes a data amount setting register 202, a deadline setting register 204, a data transfer amount counter 206, a timer 208, an urgency evaluation value calculation unit 210, and an urgency evaluation value selection unit 212 of the master B11. Further, the master B 11 includes an urgency evaluation value transmission unit 214 and an urgent evaluation value reception unit 216. The registers, counters, timers and the like have the same functions as the registers, counters, timers, etc. of the master A10 described above.

  Furthermore, the arbiter P16 compares the urgency evaluation values 305 and 306 notified from the urgency evaluation value selection units 211 and 212, respectively, and gives priority to access from the master having the highest urgency (priority) to the slave. It has a mediation unit 217 that mediates.

  The configuration of the arbiter Q17 is the same as that of the arbiter P16 except that the master A10 and the master B11 of the arbiter P16 shown in FIG. 2 are replaced with the master C12 and the master D13.

  Here, a process for guaranteeing a master deadline using the master's urgency evaluation value that is always the most strict with deadline guarantee will be described.

  Master A10 and master B11 are arbitrated by arbiter P16. If the master A10 has issued the transfer request req00 and the master B11 has not issued the transfer request req01, the arbiter P16 allows the master A10 to use the P bus 19. In this case, the bridge 15 uses the urgency evaluation value of the master A10 as the master of the Q bus 20, and issues a transfer request req00 to the arbiter Q17. Here, if the master C12 that is the master of the Q bus 20 issues a transfer request req10, the master D13 issues a transfer request req11, and if the urgency evaluation value is req11> req10> req00, the arbiter Q17 sends a Q to the master D13. The use of bus 20 is permitted.

  At this time, when the transfer request req01 is also generated from the master B11 and the urgency evaluation value is req01> req11> req10> req00, there is a problem with the conventional method. That is, there is a possibility that the deadline of the transfer request req01 cannot be guaranteed because the transfer request req00 cannot acquire the right to use the Q bus 20 even though the urgency evaluation value of the transfer request req01 is high.

  In the present embodiment, the urgency evaluation value of req00, which is a transfer request from the master A10, is compared with the urgency evaluation value of req01, which is a transfer request from the master B11, when req01 is issued later by the master B11. Here, if the urgency evaluation value of the transfer request req01 is high, the arbiter P16 notifies the arbiter Q17 to use the urgency evaluation value of the transfer request req01 for mediation of the right to use the Q bus 20.

  Thereby, the arbiter Q17 recognizes that the urgency evaluation value of the transfer request from the bridge 15 is the highest, receives the transfer request req00 from the master A10, and gives the master A10 the right to use the Q bus 20. Therefore, the transfer of the master A10 is completed, and the transfer of the master B11 is started early.

  FIG. 3 is a flowchart showing the processing of the deadline guarantee arbiter in the present embodiment. This process is performed by the arbiter P16 or the arbiter Q17.

  First, if there is a transfer request from the master to the slave 18 in step S301, the process proceeds to step S302, and it is determined whether or not transfer requests are issued from a plurality of masters. Here, if a transfer request is issued from a single master instead of a plurality of masters, the process proceeds to step S303, and the right to use the bus is given to that master. Then, the process returns to step S301 and waits until there is a new transfer request.

  On the other hand, if a transfer request is issued from a plurality of masters in step S302, the process proceeds to step S304, and the urgency evaluation values of the plurality of masters issuing the transfer requests are calculated. Next, in step S305, it is determined whether or not the bus configuration is a multi-stage bus configuration via a bridge and there is an arbiter at the upper level. Here, if there is an arbiter at the upper level in a multi-stage bus configuration, the process is performed by the arbiter P16, and the process proceeds to step S306, where it is determined whether or not the master having the highest urgency evaluation value has been given the bus use right. judge. If the right to use the bus is given to the master with the highest urgency evaluation value, the process returns to step S301.

  However, if the right to use the bus is not given to the master with the highest urgency evaluation value in step S306, the process proceeds to step S307, and the highest urgency evaluation value is notified to the upper arbiter, that is, arbiter Q17. To do. In step S308, the right to use the bus is given to the master with the highest urgency evaluation value.

  On the other hand, in step S305, if there is no arbiter at the upper level in the multi-stage bus configuration, processing is performed in arbiter Q17, and the processing proceeds to step S308 to give the bus use right to the master with the highest urgency evaluation value. If the urgency evaluation value 21 is notified from the arbiter P16, the arbiter Q17 gives the right to use the bus to the master having the highest urgency evaluation value including the urgency evaluation value 21.

  As described above, even when a transfer request with a high urgency evaluation value comes later, the urgency evaluation value is propagated between the deadline guarantee arbiters, so that deadline guarantee can be performed efficiently.

  A recording medium recording software program codes for realizing the functions of the above-described embodiments is supplied to a system or apparatus, and a computer (CPU or MPU) of the system or apparatus stores program codes stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, based on the instruction of the program code, an OS (operating system) running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing. .

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows an example of a structure of the bus system provided with the deadline guarantee arbiter (bus arbitration apparatus) in this embodiment. It is a figure which shows an example of a structure of the deadline guarantee arbiter in this embodiment. It is a flowchart which shows the process of the deadline guarantee arbiter in this embodiment. It is a figure which shows the structure of the conventional deadline guarantee arbiter. It is a figure which shows the relationship between the transfer data amount of a some master, and a deadline. It is a figure which shows an example of a structure of the bus system provided with the conventional deadline guarantee arbiter.

Explanation of symbols

10 Master A
11 Master B
12 Master C
13 Master D
15 Bridge 16 Arbiter P
17 Arbiter Q
18 Slave 19 P bus 20 Q bus 21 Urgency evaluation value

Claims (2)

A bridge that connects the first bus and the second bus; a first bus arbitration device that arbitrates the right to use the first bus; and a second bus that arbitrates the right to use the second bus. A bus arbitration method for a bus system comprising an arbitration device,
If the first master connected to the first bus issues a transfer request and the second master connected to the first bus does not issue a transfer request, the first bus arbitration device Allow the master to use the first bus,
The bridge issues a transfer request to the second bus arbitration device when the first bus arbitration device authorizes the first master to use the first bus;
In the second bus arbitration device, the bridge and the master connected to the second bus issue a transfer request, and the transfer issued by the master connected to the second bus from the urgency of the transfer request issued by the bridge. If the urgency of the request is high, the master connected to the second bus is allowed to use the second bus,
The first bus arbitration device issues a transfer request having a higher urgency than the transfer request issued by the first master when the second master is not permitted to use the second bus by the bridge. If issued, notify the second bus arbitration device of the urgency of the transfer request issued by the second master,
The second bus arbitration device uses the second bus based on the urgency level notified from the first bus arbitration device and the urgency level of the transfer request issued by the master connected to the second bus. A bus arbitration method for a bus system, characterized by arbitrating a right. A bridge that connects the first bus and the second bus; a first bus arbitration device that arbitrates the right to use the first bus; and a second bus that arbitrates the right to use the second bus. A bus system comprising an arbitration device,
If the first master connected to the first bus issues a transfer request and the second master connected to the first bus does not issue a transfer request, the first bus arbitration device Allow the master to use the first bus,
The bridge issues a transfer request to the second bus arbitration device when the first bus arbitration device authorizes the first master to use the first bus;
In the second bus arbitration device, the bridge and the master connected to the second bus issue a transfer request, and the transfer issued by the master connected to the second bus from the urgency of the transfer request issued by the bridge. If the urgency of the request is high, the master connected to the second bus is allowed to use the second bus,
The first bus arbitration device issues a transfer request having a higher urgency than the transfer request issued by the first master when the second master is not permitted to use the second bus by the bridge. If issued, notify the second bus arbitration device of the urgency of the transfer request issued by the second master,
The second bus arbitration device uses the second bus based on the urgency level notified from the first bus arbitration device and the urgency level of the transfer request issued by the master connected to the second bus. A bus system characterized by mediating rights.

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