JP4940540B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device for physical quantity distribution detection in which a plurality of unit components are arranged. More specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged, and the physical quantity distribution converted into an electric signal by the unit components is converted into an electric signal. The present invention relates to a technique for reading out a signal and acquiring information for a predetermined purpose, which is suitable when using a semiconductor device with physical quantity distribution detection such as a solid-state imaging device.

  For example, a plurality of unit components (for example, pixels) having a detection unit that is sensitive to changes in physical quantities such as electromagnetic waves or pressure (contact, etc.) input from the outside, such as light and radiation, in a line or matrix form Such physical quantity distribution detecting semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell). For example, many CMOS solid-state imaging devices have such a configuration.

  For example, in Patent Document 1, a logic circuit, an analog circuit, an analog-digital conversion circuit, or the like is formed on a sensor chip as a CMOS type solid-state imaging device by using the same CMOS circuit manufacturing process, and the pixel read from the imaging unit There has been proposed a mechanism for performing various signal processing applied to a signal on the same sensor chip as the imaging unit.

JP 2004-112845 A

  By the way, in order to read out the pixel signal from the imaging unit in the amplification type solid-state imaging device, the address control is performed on the imaging unit in which a plurality of unit pixels are arranged, and the signals from the individual unit pixels are arranged in the order of the determined addresses. Or arbitrarily select and read. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons and holes) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  Here, there are various circuit configurations for extracting a signal from the pixel. As a typical example, an electrical signal corresponding to the amount of charge accumulated in a photoelectric conversion element such as a photodiode is converted into a voltage value in the pixel. And take it out.

  As a configuration example, a floating follower (FD) having a diffusion layer having a parasitic capacitance as a main part is used as a charge storage unit, and a source follower is configured by an amplifying transistor and a load MOS transistor in a unit pixel. An FDA (Floating Diffusion Amp) configuration is known (see Non-Patent Document 1).

Kazuya Yonemoto, Chapter 6 of “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publisher, August 10, 2003, first edition

  In this case, a change in the potential (FD potential) of the floating diffusion is read out via an output signal line (for example, a vertical signal line) corresponding to the output of the source follower. The output from the pixel is obtained with this voltage value, and is processed by a subsequent amplifier, an AD (Analog-Digital) converter, or the like.

  However, a signal taken out via an output signal line (for example, a vertical signal line) is affected by a difference in signal conversion ability such as floating diffusion conversion efficiency and amplification transistor sensitivity. It is also affected by optical shading. Hereinafter, problems due to these influences will be described.

<Relationship of vertical signal line potential to FD potential>
FIG. 17 is a diagram illustrating the relationship of the potential on the vertical signal line with respect to the FD potential. When the potential of the floating diffusion is sufficiently high and the output potential is also high, since the load MOS transistor operates in the saturation region, a constant current is supplied, and the potential of the vertical signal line is linear with respect to the change of the FD potential. To change.

  However, when the potential of the floating diffusion decreases due to the lower power supply voltage, the potential of the vertical signal line also decreases, and when the load MOS transistor operates in the linear region, the supply current becomes unstable, so the FD potential On the other hand, the change in the vertical signal line is not linear.

  When such a non-linear region is used, the change in output voltage with respect to the amount of light is not constant, which causes a problem that the gradation of the image is not output accurately. Increasing the power supply voltage will solve the problem, but it will not be possible to meet the demand for lower power supply voltage.

<Example of cross-sectional structure in the vicinity of FD of pixel>
FIG. 18 is a diagram illustrating an example of a cross-sectional structure near a floating diffusion in a pixel. Here, a cross section of the reset transistor 36, the floating diffusion 38, and the amplifying transistor 42 is shown.

  The floating diffusion 38 has a diffusion layer 532b that forms the drain of the reset transistor 36 as a main part, and a wiring metal film 560b that is a metal wiring on the interlayer film 540 (in the interlayer film 542) as a first layer and a connection hole 550b, It is connected to the gate wiring 530 of the amplifying transistor 42 via 550c.

  Here, as can be seen from the figure, the capacitance component of the floating diffusion 38 is determined from the diffusion capacitance, the overlap capacitance with the gate, or the wiring capacitance. In recent years, the capacity of the floating diffusion 38 is reduced due to the reduction of pixels.

  Further, the conversion efficiency ([V / e −] = V / Q) of the floating diffusion 38 is inversely proportional to the FD capacity C from the relational expression of Q = CV. That is, the conversion efficiency increases as the capacitance of the floating diffusion 38 decreases, and a larger signal voltage can be obtained for the same signal charge amount Q. As a result, the nonlinear region of the source follower is used. That is, if the conversion efficiency ([V / e −] = V / Q) of the floating diffusion is too large, there is a possibility that an area without the linearity of the source follower may be used when reading a signal from the pixel. is there.

  Similarly, the sensitivity of the amplifying element also affects the linearity of the source follower, and depending on the sensitivity, there is a possibility of using a region having no linearity.

<Shading phenomenon>
FIG. 19 is a diagram for explaining the shading phenomenon. Usually, an image sensor receives light collected by a lens in a light receiving unit. When the area of the pixel array is increased or the distance from the optical system to the imaging surface is decreased, a phenomenon that the screen becomes darker toward the periphery of the pixel array, that is, shading is seen as shown in FIG. This is because the incident angle of light at the periphery of the array becomes steeper, light is bounced by the wiring layer and gate, and light that does not enter the photoelectric conversion element increases. This is called optical shading. Even if a white object is imaged, the peripheral part looks dark.

  The present invention has been made in view of the above circumstances, and it is a first object of the invention to propose a mechanism capable of setting signal conversion characteristics of unit components in a linear region. In particular, an object of the present invention is to provide a mechanism capable of matching the level of a signal representing a change in physical quantity detected by a detection unit such as a photoelectric conversion element to the operation range of a circuit connected to a subsequent stage.

  Moreover, this invention sets it as the 2nd objective to propose the mechanism which can set the signal conversion capability of a unit component for every place. In particular, an object of the present invention is to provide a mechanism for suppressing optical shading by adjusting the signal conversion capability of a unit component for each location.

  A first semiconductor device according to the present invention includes a detection unit that detects change information according to a change in an incident physical quantity, and a unit signal generation unit that generates a unit signal based on the change information detected by the detection unit. A semiconductor device for detecting a physical quantity distribution that is included in a unit component and in which the unit components are arranged in a predetermined order, in order to set the signal conversion characteristics of the unit component in a linear region in the unit signal generation unit The predetermined operation is added.

  In short, the operation that is not performed in the normal device design is applied to various members constituting the unit component, so that the signal conversion characteristics of the unit component are set in the linear region. .

  The invention described in the dependent claims defines further advantageous specific examples of the first semiconductor device according to the present invention.

  For example, an adjustment electrode member for setting a signal conversion characteristic of a unit component in a linear region may be provided as a predetermined operation, with a target to perform a predetermined operation as a unit signal generation unit.

  In addition, when the unit signal generation unit is configured to include a charge storage unit that stores signal charges as change information representing a change in physical quantity detected by the detection unit, predetermined units for various members constituting the unit component For example, by adjusting the capacitance of the charge storage unit, the signal conversion characteristics of the unit components can be set in the linear region.

  By doing this, the conversion efficiency of the charge storage unit is changed, and as a result, the gain of the source follower constituted by, for example, the amplification transistor in the unit signal generation unit and the load transistor outside the unit signal generation unit is changed, thereby The signal conversion characteristic of the component can be set in the linear region.

  Here, in order to adjust the capacitance of the charge storage unit, a predetermined operation is applied to various members that contribute to the capacitance formation of the charge storage unit, such as diffusion capacitance, overlap capacitance with the gate, or wiring capacitance. realizable.

  For example, this can be realized by making the concentration of impurity diffusion into the charge storage portion different. Alternatively, wiring for adjusting the capacitance may be connected. In the latter case, the wiring may be made in an invalid state in the role of connection with other nodes, that is, may be composed of only the capacitance adjusting electrode member that does not substantially contribute to the connection. Alternatively, it may be configured by a combination of a connection electrode member that contributes exclusively to the connection and a capacitance adjustment electrode member that does not substantially contribute to the connection. In this case, the capacity adjustment electrode member may be formed in a different layer from the connection electrode member, or the capacity adjustment electrode member and the connection electrode member may be formed in the same layer.

  Further, as another method of making the charge storage portions have different capacities, when each charge storage portion has a diffusion layer such as a floating diffusion, this diffusion layer It is also possible to adopt a method in which the areas are different.

  In addition, a predetermined operation for various members constituting the unit component for setting the signal conversion characteristics of the unit component in the linear region is configured, for example, by the unit signal generation unit having a semiconductor element for signal amplification. In this case, it can be realized by adjusting the gate length and gate width of the semiconductor element. In this way, for example, the gain of the source follower constituted by the amplification transistor in the unit signal generation unit and the load transistor outside the unit signal generation unit is changed, thereby setting the signal conversion characteristic of the unit component in the linear region. be able to.

  In addition, a second semiconductor device according to the present invention includes a detection unit that detects change information according to a change in incident physical quantity, and a unit signal generation unit that generates a unit signal based on the change information detected by the detection unit. Are included in the unit component, and the unit component is arranged in a predetermined order for detecting a physical quantity distribution, and each unit component has a signal according to the location dependence of the incident physical quantity. The conversion ability is adjusted.

  The invention described in the dependent claims defines a further advantageous specific example of the second semiconductor device according to the present invention. For example, the mechanism for adjusting the signal conversion capability is not limited as long as the predetermined operations on the various members constituting the unit component are different depending on the location dependence of the incident physical quantity. Various mechanisms in the first semiconductor device according to the invention can be used as they are.

  According to the first semiconductor device of the present invention, the unit signal generator is subjected to a predetermined operation for setting the signal conversion characteristic of the unit component in the linear region. By applying an operation different from normal element formation, the signal conversion capability can be set for each unit component. Therefore, even if the physical quantity change is the same, the unit signal output from each unit component can be adjusted, and the unit signal output from the unit component can be adjusted. . As a result, the signal conversion capability can be adjusted so that the signal amplitude matches the range of the subsequent circuit.

  For example, in the case of a device configuration that includes a charge storage unit, the conversion efficiency can be adjusted by attaching a capacitance adjustment wiring to the charge storage unit, and the addition of this wiring increases the capacitance and lowers the conversion efficiency. Thus, the signal amplitude can be adjusted to the range of the subsequent circuit.

  According to the second semiconductor device of the present invention, the signal conversion capability of each unit component is adjusted according to the location dependence of the incident physical quantity. Since the signal conversion capability can be set according to the location dependence of the incident physical quantity, optical shading can be suppressed.

  Further, in any of the first and second semiconductor devices, changing the signal conversion capability within the unit component is for correcting the signal conversion capability (for example, sensitivity) in an analog manner, and is an output unit. The gradation of the signal is not impaired. Therefore, the signal conversion capability can be corrected in an analog manner within the pixel, and a natural image can be obtained without losing the gradation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS image sensor will be described on the assumption that all pixels are made of NMOS.

  However, this is merely an example, and the target device is not limited to a MOS imaging device. Embodiments described later are applied to all semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix. The same applies.

<Configuration of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device 1 is applied as, for example, an electronic still camera or an FA (Factory Automation) camera that can capture a color image.

  The solid-state imaging device 1 includes an imaging unit in which unit pixels including a light receiving element (not shown) that outputs a signal corresponding to the amount of incident light are arranged in a square lattice of rows and columns (that is, a two-dimensional matrix). A signal output from each unit pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit and other function units are provided for each vertical column. .

  That is, as shown in FIG. 1, the solid-state imaging device 1 includes an imaging unit (pixel unit) 10 in which a plurality of unit pixels 3 (an example of unit constituent elements) are arranged in rows and columns (in a two-dimensional matrix). A so-called area sensor, a drive control unit 7 provided outside the imaging unit 10, and a column processing unit 20 having column signal processing units (indicated as column circuits in the figure) 22 arranged in each vertical column. ing.

  As the drive control unit 7, for example, a horizontal scanning unit 12 and a vertical scanning unit 14 are provided. Further, as another component of the drive control unit 7, a drive signal operation for supplying a control pulse at a predetermined timing to each functional unit of the solid-state imaging device 1 such as the horizontal scanning unit 12, the vertical scanning unit 14, or the column processing unit 20 is provided. A unit (an example of a read address control device) 16 is provided.

  Each element of the drive control unit 7 is integrally formed in a semiconductor region such as single crystal silicon together with the imaging unit 10 using a technique similar to the semiconductor integrated circuit manufacturing technique, and is a solid-state imaging that is an example of a semiconductor system. It is configured as an element (imaging device).

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column of the imaging unit 10. . Although illustration is omitted, the imaging unit 10 is formed with a color separation filter having a predetermined color coding for each pixel. Although not shown, each pixel of the imaging unit 10 is configured by a photoelectric conversion element such as a photodiode and a transistor circuit (see FIG. 2 described later).

  On the signal path between the column processing unit 20 and the horizontal scanning unit 12, a load transistor unit including a load MOS transistor (not shown) having a drain terminal connected to each vertical signal line 18 is arranged (a diagram to be described later). 2), a load control unit (load MOS controller) for driving and controlling each load MOS transistor is provided.

  The unit pixel 3 is connected to a vertical scanning unit 14 via a vertical control line 15 for selecting a vertical column and a column processing unit 20 via a vertical signal line 18. The horizontal scanning unit 12 and the vertical scanning unit 14 are configured to include, for example, a shift register, and start a shift operation (scanning) in response to a drive pulse given from the drive signal operation unit 16. The vertical control line 15 includes various pulse signals for driving the unit pixel 3.

  The horizontal scanning unit 12 defines a horizontal readout column (horizontal address) (selects each column signal processing unit 22 in the column processing unit 20), and a horizontal address setting unit 12a. The horizontal drive unit 12b guides each signal of the column processing unit 20 to the horizontal signal line 28 in accordance with the read address defined in FIG. Although not shown, the horizontal address setting unit 12a includes a shift register or a decoder. The horizontal address setting unit 12a sequentially selects the pixel information from the column signal processing unit 22, and uses the selected pixel information as the horizontal signal line 28. It has a function as a selection means to output to

  The vertical scanning unit 14 defines a vertical readout row (vertical address) and a horizontal readout column (horizontal address) (selects a row of the imaging unit 10), and a vertical address setting unit 14a. A vertical drive unit 14b that drives by supplying a pulse to the control line for the unit pixel 3 on the read address (in the horizontal direction) defined by the address setting unit 14a.

  Although not shown in the figure, the vertical address setting unit 14a has a shutter shift register that controls a row for an electronic shutter in addition to a vertical shift register or a decoder that performs basic control of a row from which a signal is read. At the time of driving for the electronic shutter, the vertical address setting unit 14a selects the row of the unit pixel 3 as in the normal operation, but the photoelectric address is adjusted by adjusting the interval of the shutter row with the readout row selected as usual. The exposure time (accumulation time) for the conversion element is adjusted.

  The vertical shift register or decoder is for selecting each pixel in units of rows when reading out pixel information from the imaging unit 10, and constitutes a signal output row selection unit together with the vertical drive unit 14b of each row. The shutter shift register is for selecting each pixel in units of rows when performing the electronic shutter operation, and constitutes an electronic shutter row selection means together with the vertical drive unit 14b of each row.

  Although not shown, the drive signal operation unit 16 includes a functional block of a timing generator TG (an example of a read address control device) that supplies a clock necessary for the operation of each unit and a pulse signal of a predetermined timing, and an input clock via a terminal 1a. A communication interface functional block that receives data instructing CLK0, an operation mode, and the like, and that outputs data DATA including information of the solid-state imaging device 1 via the terminal 1b. In addition, the horizontal address signal is output to the horizontal address setting unit 12a and the vertical address signal is output to the vertical address setting unit 14a, and each address setting unit 12a, 14a receives it and selects a corresponding row or column.

  The drive signal operation unit 16 may be provided as a separate semiconductor integrated circuit independently of other functional elements such as the imaging unit 10 and the horizontal scanning unit 12. In this case, an imaging device which is an example of a semiconductor system is constructed by the imaging device including the imaging unit 10 and the horizontal scanning unit 12 and the drive signal operation unit 16. This imaging device may be provided as an imaging module in which peripheral signal processing circuits, power supply circuits, and the like are also incorporated.

  The column processing unit 20 as a reading circuit is configured to include a column signal processing unit 22 for each vertical column, and receives signals from pixels for one row and processes the signals. As an example, each column signal processing unit 22 is provided with a signal transfer switch and a storage capacitor. In addition, the column processing unit 20 may have a function of a noise removing means using a CDS (Correlated Double Sampling) process, and the sample pulse SHP and the sample pulse given from the drive signal operation unit 16 may be provided. Based on two sample pulses such as SHD, the difference between the signal level immediately after pixel reset (noise level; 0 level) and the true signal level with respect to voltage mode pixel information input via the vertical signal line 18 By performing the process of removing noise signal components called fixed pattern noise (FPN) and reset noise due to fixed variation for each pixel.

  The column processing unit 20 includes an AGC (Auto Gain Control) circuit or an ADC (Analog Digital Converter) circuit having a signal amplifying function, if necessary, in the subsequent stage of the CDS processing function unit. It is also possible to provide each signal processing unit 22.

  A voltage signal indicating pixel information processed by the column processing unit 20 is read out at a predetermined timing via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning unit 12 and applied to the horizontal signal line 28. The signal is transmitted and input to the output circuit 29 connected to the rear end of the horizontal signal line 28.

  The output circuit 29 amplifies the signal of each pixel output from the imaging unit 10 through the horizontal signal line 28 with an appropriate gain, and then supplies the signal as an imaging signal S0 to an external circuit (not shown) via the output terminal 1c. For example, the output circuit 29 may perform only buffering, or may perform black level adjustment, column variation correction, signal amplification, color-related processing, or the like before that.

  That is, in the column-type solid-state imaging device 1 of this embodiment, the output signal (voltage signal) from the unit pixel 3 is in the order of the vertical signal line 18 → the column processing unit 20 → the horizontal signal line 28 → the output circuit 29. Is output. The drive is such that the pixel output signals for one row are sent in parallel to the column processing unit 20 via the vertical signal line 18, and the signal after CDS processing is serially output via the horizontal signal line 28.

  In addition, as long as driving for each vertical column or horizontal column is possible, each pulse signal is arranged in the horizontal direction or the vertical column direction with respect to the unit pixel 3, that is, driving for applying a pulse signal. The physical wiring method of the clock line is free.

  The external circuit is configured on a different substrate (printed substrate or semiconductor substrate) from the solid-state imaging device in which the imaging unit 10 and the drive control unit 7 are integrally formed in the same semiconductor region. A circuit configuration corresponding to the above is adopted. A solid-state imaging device 1 is configured by a solid-state imaging device (an example of a semiconductor device or a physical information acquisition device) including an imaging unit 10 and a drive control unit 7 and an external circuit. The drive control unit 7 is separated from the imaging unit 10 and the column processing unit 20, and the imaging unit 10 and the column processing unit 20 constitute a solid-state imaging device (an example of a semiconductor device). The solid-state imaging device (an example of a semiconductor device) ) And a separate drive control unit 7 may be configured as a solid-state imaging device (an example of a physical information acquisition device).

  For example, the external circuit includes an A / D (Analog to Digital) conversion unit that converts an analog imaging signal S0 output from the output circuit 29 into digital imaging data D0, and an imaging that is digitized by the A / D conversion unit. A digital signal processor (DSP) that performs digital signal processing based on the data D0.

  The digital signal processing unit has a function of a digital amplifier unit that appropriately amplifies and outputs a digital signal output from the A / D conversion unit, for example. Further, for example, color separation processing is performed to generate image data RGB representing each image of R (red), G (green), and B (blue), and other signal processing is performed on the image data RGB for monitoring. Output image data D2 is generated. Further, the digital signal processing unit is provided with a functional unit that performs signal compression processing for storing imaging data in a recording medium.

  The external circuit also includes a D / A (Digital to Analog) converter that converts the image data D2 digitally processed by the digital signal processor into an analog image signal S1. The image signal S1 output from the D / A converter is sent to a display device such as a liquid crystal monitor. The operator can perform various operations such as switching the imaging mode while viewing the menu and images displayed on the display device.

  In the above description, an example in which the external circuit in charge of the signal processing of the subsequent stage of the solid-state image sensor is performed outside the solid-state image sensor (chip) is shown. Alternatively, some functional elements (for example, the AGC unit 102, the A / D conversion unit 104, the digital amplifier unit, etc.) are configured to be built in the chip, and the imaging data D0 is output from the output terminal 1d. Also good.

  In the solid-state imaging device 1 having such a configuration, the horizontal scanning unit 12 and the vertical scanning unit 14 and the drive signal operation unit 16 that controls them are sequentially selected for each pixel of the imaging unit 10 in a horizontal unit, and the selection is performed. A CMOS image sensor of a type that simultaneously reads out information of one horizontal parallel pixel is configured.

<First Embodiment>
<Circuit configuration example of unit pixel>
FIG. 2 is a diagram for explaining the first embodiment of the present invention, and is a circuit diagram of a configuration example of the unit pixel 3. As shown in the figure, the unit pixel 3 employs a configuration in which a floating diffusion (FDA) having a diffusion layer having a parasitic capacitance as a main part is used as a charge storage unit, and the unit pixel 3 includes four transistors (TRansistor). ) Having a four-transistor pixel configuration (hereinafter referred to as a 4TR configuration).

  As shown in the figure, the unit pixel 3 includes a charge generation unit 32 having both a photoelectric conversion function for converting light into a charge and a charge storage function for storing the charge. Changes in potentials of a read selection transistor 34 as an example of a transfer unit (charge readout unit / transfer gate unit / read gate unit), a reset transistor 36 as an example of a reset gate unit, a vertical selection transistor 40, and a floating diffusion 38 are shown. It has an amplifying transistor 42 having a source follower configuration which is an example of a detecting element to detect.

  Further, as a configuration peculiar to the first embodiment, the unit pixel 3 has a load wiring (dummy wiring) in the input portion of the amplifying transistor 42 that serves to convert the signal charge detected by the charge generating portion 32 into a voltage. 39 is connected. Particularly in the first embodiment, the load wiring 39 does not have a role of circuit connection with other nodes, and the drain of the reset transistor 36 in which the floating diffusion 38 is formed and the input side of the amplifying transistor 42 are connected. It is in a state where it is hung on the wiring to be connected, that is, a state that does not contribute to the connection role with other nodes (inactive state). Hereinafter, such a state is also referred to as a dummy wiring or a floating wiring.

  The amplifying transistor 42 constituting the unit pixel 3 is connected to each vertical signal line 53 (corresponding to the vertical signal line 18 in FIG. 1), and the vertical signal line 53 is a load that forms a constant current source In for each vertical column. A load control signal Load from a load control unit (not shown) is commonly input as a constant bias to the gate terminals of the load MOS transistors 27 and connected to the drains of the MOS transistors 27. The load MOS transistor 27 connected to the main transistor 42 continues to pass a predetermined constant current. In other words, the load MOS transistor 27 has its gate biased at a constant potential and forms a signal output to the vertical signal line 53 by assembling the source follower with the amplification transistor 42 in the selected row.

  The horizontal wiring is common to pixels in the same row, and is driven and controlled by a vertical driving unit 14b of the vertical scanning unit 14 (not shown). For example, a transfer drive buffer 150, a reset drive buffer 152, and a selection drive buffer 154 are accommodated in the vertical drive unit 14b.

  The read selection transistor 34 is driven by the transfer drive buffer 150 via a transfer wiring (read selection line) 55. The reset transistor 36 is driven by the reset driving buffer 152 via the reset wiring 56. The vertical selection transistor 40 is driven by the selection drive buffer 154 via the vertical selection line 52.

  The unit pixel 3 includes a pixel signal generation unit 5 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 38, which is an example of a charge injection unit having functions of an amplification transistor 42 and a charge storage unit. ing. The floating diffusion 38 has a diffusion layer having parasitic capacitance in the main part.

  The reset transistor 36 in the pixel signal generation unit 5, which is an example of a unit signal generation unit that generates a pixel signal as a unit signal, has a source connected to the floating diffusion 38, a drain connected to the power supply VDD, and a gate (reset gate RG). The reset pulse RST is input from the reset drive buffer 152.

  Here, the unit pixel 3 is a pixel having a 4TR configuration that includes a selection transistor inserted in series with the amplification transistor 42 and selects a pixel. Of the amplification transistor 42 and the vertical selection transistor 40, The vertical selection transistor 40 is on the vertical signal line 53 side.

  That is, the amplifying transistor 42 has a drain connected to the power supply VDD (for example, 2.5 V), a source connected to the drain of the vertical selection transistor 40, and a gate connected to the floating diffusion 38. The vertical selection transistor 40 has a gate (in particular, a vertical selection gate SELV) connected to the vertical selection line 52 and a source connected to the vertical signal line 53 via the pixel line 51. A vertical selection signal is applied to the vertical selection line 52 from the selection drive buffer 154.

  Although not shown, the amplification transistor 42 may be of the type in which the amplification transistor 42 is on the vertical signal line 53 side of the amplification transistor 42 and the vertical selection transistor 40.

<Driving method of unit pixel>
FIG. 3 is a timing chart for explaining a method of acquiring the pixel signal (unit signal output from the unit pixel 3) by driving the unit pixel 3 shown in FIG. In the 4TR configuration shown in FIG. 2, the reset transistor 36 resets the floating diffusion 38. Specifically, the floating diffusion 38 is reset by discarding the signal charges (here, electrons) of the floating diffusion to the power supply wiring.

  The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generation unit 32 to a floating diffusion 38 which is an example of a charge storage unit.

  Since the floating diffusion 38 is connected to the gate of the amplifying transistor 42 which is an example of the unit signal generation unit, the amplifying transistor 42 is a signal corresponding to the potential of the floating diffusion 38 (hereinafter also referred to as FD potential) (in this example). Voltage signal) is output to the vertical signal line 53, which is an example of an output signal line, via the pixel line 51 when the vertical selection transistor 40 is on. That is, a large number of pixels are connected to the vertical signal line 53. To select a pixel, the vertical selection transistor 40 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 53, and the signal of the selected pixel is output to the vertical signal line 53.

  Specifically, as shown in the timing chart of FIG. 3, the read pulse (transfer gate pulse) TRG becomes active (high level in this example), drives the read selection transistor 34, and enters the charge generation unit 32. Signal charges generated by photoelectric conversion of light are transferred to a floating diffusion 38 that functions as an accumulation node and read out.

  Here, the signal charge generated by photoelectric conversion of the light incident on the charge generation unit 32 is accumulated in the charge generation unit 32 until the read selection transistor 34 is turned on.

  First, in the horizontal scanning line blanking period, the vertical selection pulse SEL is activated (high level in this example) to turn on the vertical selection transistor 40 (t10), and the amplification transistor 42 charges the floating diffusion 38. Is connected to the output of the amplifying transistor 42 in the readout row and the vertical signal line 53, and the source signal follower circuit is constituted by the vertical signal line 53, the current source In (load MOS transistor 27), and the amplifying transistor 42. Configure. The potential of the vertical signal line 53 follows the potential fluctuation of the floating diffusion 38. As a result, only the potential determined by the gate potential of the amplifying transistor 42 corresponding to the charge amount of the floating diffusion 38 is transmitted to the vertical signal line 53.

  Further, with the start of the horizontal scanning line blanking period, the signal signal Qsig is accumulated in the charge generation unit 32, and the pixel signal generation unit 5 is first reset to the reference voltage, that is, the reset gate pulse RG is activated (main). In the example, the level is set to high level (t11), and the reset transistor 36 is turned on to discharge the dark current integrated value accumulated in the floating diffusion 38. As a result, the floating diffusion 38 is set to the power supply voltage value (Vdd). When the reset gate pulse RG is inactive (low level in this example) (t12), the potential of the floating diffusion 38 slightly drops due to coupling.

  At this time, a sample pulse SHP is output from the drive signal operation unit 16 and supplied to the gate of the shift transistor forming the CDS function unit in the column processing unit 20, and each shift transistor is turned on. That is, the clamp pulse SHD is supplied from the drive signal operation unit 16 and supplied to the gate of the clamp transistor forming the CDS function unit in the column processing unit 20, and each clamp transistor is turned on to detect the reset level Srst ( t14).

  Next, the read selection transistor 34 for the charge generation unit 32 is driven to read the signal component So corresponding to the signal charge Qsig from the charge generation unit 32. That is, the transfer gate pulse TRG is set to the high level (t16), the read selection transistor 34 is turned on, and the signal charge Qsig stored in the charge generation unit 32 is transferred to the floating diffusion 38. The amount of signal charge Qsig transferred to the floating diffusion 38 is detected by the amplifying transistor 42, and a potential corresponding to the amount of charge is generated and transmitted to the vertical signal line 53.

  Thereafter, the clamp pulse SHD is supplied from the drive signal operation unit 16 (t18), the clamp transistor is turned on, and the pixel signal level Ssig corresponding to the signal charge Qsig detected by the charge generation unit 32 is detected.

  Here, the column processing unit 20 takes the difference between the reset level Srst and the pixel signal level Ssig, thereby removing the offset component and detecting the true signal component So. It is possible to remove fixed pattern noise for each pixel.

End the transfer of the signal charges, is sufficient time after passed (in this example low) inactive vertical selection pulse SEL to (t20).

<Pixel manufacturing method and cross-sectional structure example near FD>
FIG. 4 is a diagram showing an example of a cross-sectional structure near the floating diffusion in the unit pixel 3 shown in FIG. FIG. 4 shows a cross section of the reset transistor 36, the floating diffusion 38, and the amplifying transistor 42.

  In manufacturing the structure of the unit pixel 3 shown in FIG. 2, an oxide film mask is patterned on the n-type Si semiconductor by lithography. Further, group III elements are doped from above using thermal diffusion technology. In this case, the doping depth is controlled by time.

  For example, by performing ion implantation (impurity diffusion) into the n-type Si semiconductor substrate 500, diffusion layers (ion implantation regions) 532a, 532b, 532c, which form the respective sources and drains for the reset transistor 36 and the amplifying transistor 42, 532d is formed.

  Further, after forming a gate oxide film (Gate Ox.) 520 as an insulating film, the gate wirings 530a and 530b for the reset transistor 36 and the amplifying transistor 42 are patterned by lithography and dry etching techniques. Also, an element isolation region 514 made of a trench buried film of STI (Shallow Trench Isolation) is formed.

  The impurity doping and thermal diffusion described above are performed according to the purpose before and after the gate wiring is formed. Thereafter, interlayer films 540 and 542 such as a silicon oxide (SiO 2) film and a protective film 544 on the surface are formed.

  In addition, a metal wiring composed of electrical connection holes 550 and 552 and wiring metal films 560 and 562 by metal wiring or the like is formed on the interlayer films 540 and 542, and further a passivation film, that is, a protective film 544 is formed, thereby forming a semiconductor LSI. To form a sensor.

Here, when the connection hole 552 and the wiring metal film 562 are formed, a metal wiring film 564 for the load wiring 39 such as a polysilicon (Poly Si) film is formed at the same time. The metal wiring film 564 functions as a capacitance adjusting electrode member for adjusting the capacitance in the floating diffusion 38 serving as a charge storage portion.

  As shown in FIG. 4, the metal wiring film 564 formed in the protective film 544 (on the interlayer film 542), which is a layer different from the protective film 542, is first formed in the interlayer film 542 (interlayer film) via the connection hole 552b. 540) and the wiring metal film 560b connecting the drain of the reset transistor 36 and the gate of the amplifying transistor 42.

  On the other hand, the wiring metal film 560 b functions as an electrode member that contributes exclusively to the connection between the charge generation unit 32 and the pixel signal generation unit 5, in particular, the diffusion layer 532 b that forms the drain of the reset transistor 36 and the gate electrode 530 b of the amplification transistor 42. To do. The wiring metal film 560b is connected to the diffusion layer 532b through the connection hole 550b and to the gate electrode 530b through the connection hole 550c.

  The difference from the configuration shown in FIG. 18 described in the section of the prior art is in the metal wiring film 564 formed in the protective film 544 (on the interlayer film 542). However, the wiring metal film 560b formed in the interlayer film 542 (on the interlayer film 540) is, like the connection holes 550b and 550c, between the drain of the reset transistor 36 and the gate of the amplifying transistor 42, that is, of the floating diffusion 38. The metal wiring film 564 is not used for connection between the nodes, whereas the diffusion layer and the gate of the amplifying transistor 42 are connected to each other. Are connected to increase.

  When the pixels are reduced, the capacity of the floating diffusion 38 is reduced, the conversion efficiency tends to be increased, and the nonlinear region of the source follower is used. In order to avoid this conversion efficiency problem, it is necessary to adjust the conversion efficiency ([V / e −] = V / Q) of the floating diffusion 38 in accordance with the operation range of the subsequent stage by some method.

  Since the capacitance component of the floating diffusion 38 is determined, for example, from the diffusion capacitance, the overlap capacitance with the gate, or the wiring capacitance, the capacitance component can be adjusted by applying an operation to any of these.

  In the configuration of the first embodiment, the metal wiring film 564 is also connected as a floating wiring hanging from the gate of the amplifying transistor 42, which contributes to the capacitance component of the floating diffusion 38.

  Although the conversion efficiency of the floating diffusion 38 is inversely proportional to the FD capacity, in the configuration of the present embodiment, the area of the floating diffusion 38 can be adjusted by using the metal wiring film 564 by adding the metal wiring film 564. Accordingly, the conversion efficiency can be reduced by increasing the FD capacity. Therefore, the signal conversion characteristics of the pixel signal generation unit 5 constituting the unit pixel 3 can be set in the linear region, and the level of the pixel signal can be matched with the operation range of the circuit connected to the subsequent stage.

  That is, the capacitance (inter-wiring capacitance, etc.) of the wiring is usually very small, but the capacitance of the floating diffusion 38 itself is on the order of a very small number [fF], so that it is within the interlayer film 542 (on the interlayer film 540). By changing the area (width and length) of the metal wiring film 564 connected to the wiring metal film 560b, the capacity of the floating diffusion 38 can be increased by about 10 to 20%, for example.

  As a result, the conversion efficiency ([V / e−]) in the floating diffusion 38 can be easily reduced, and the output range of the pixel signal can be kept within the region where the source follower is linear. That is, the FD conversion efficiency can be adjusted according to the operation range of the subsequent stage.

  Further, this mechanism is to correct the sensitivity in an analog manner in the unit pixel 3 by changing the conversion efficiency by changing the capacitance of the floating diffusion 38 on the gate side of the amplifying transistor 42, and the gradation is lost. Natural images can also be obtained without being lost.

  Further, by forming the metal wiring film 564 functioning as a capacitance adjusting electrode member in a different layer from the wiring metal film 560b functioning as a connection electrode member, the metal wiring film 560b is affected by the wiring metal film 560b and other connection wirings. The area of the wiring metal film 560b can be adjusted without any restrictions (that is, there are few layout restrictions), and the degree of freedom of capacitance adjustment is higher than the configuration of the second embodiment described later.

Second Embodiment
<Circuit configuration example of unit pixel>
FIG. 5 is a diagram for explaining the second embodiment of the present invention, and is a circuit diagram of a configuration example of the unit pixel 3. FIG. 6 is a diagram showing an example of a cross-sectional structure near the floating diffusion in the unit pixel 3 shown in FIG.

  The configuration of the second embodiment is characterized in that the load wiring 39 also has a role of circuit connection with other nodes. That is, in the circuit configuration, as shown in FIG. 5, the drain of the reset transistor 36 and the gate of the amplifying transistor 42 are not directly connected, but a part of the load wiring 39 (39a portion in the figure). ) Is used as connection wiring.

  Further, as shown in FIG. 6, the metal wiring film 564 formed in the protective film 544 (on the interlayer film 542) is first formed in the interlayer film 542 (interlayer film) via the connection hole 552c. 540) and a diffusion metal layer 532b that forms the drain of the reset transistor 36 through a connection hole 550b. Further, the wiring metal film 560d provided in the interlayer film 542 (on the interlayer film 540) is connected through the connection hole 552d, and further connected to the gate electrode 530b of the amplifying transistor 42 through the connection hole 550c.

  In such a configuration of the second embodiment, a part of the metal wiring film 564 (portion 564a in the figure) is used for connection between the nodes, but the other part (564b, 564c in the figure). (2) is provided in order to increase the wiring capacitance on the gate side of the amplifying transistor 42.

  As described above, the metal wiring film 564 is used as the metal wiring film 564a as an electrode member that contributes exclusively to the connection between the charge generation unit 32 and the pixel signal generation unit 5, and as a capacitance adjustment electrode member that does not substantially contribute to the connection. When the metal wiring films 564b and 564c are configured in the same layer, the drain of the reset transistor 36 and the gate of the amplifying transistor 42 cannot be directly connected only in the interlayer film 542 (on the interlayer film 540). In addition, the same effect as in the first embodiment can be enjoyed.

  Therefore, similarly to the configuration of the first embodiment, by adding the metal wiring film 564, the conversion efficiency can be reduced by increasing the FD capacitance, and the output range of the pixel signal can be reduced by the linearity of the source follower. The FD conversion efficiency can be adjusted within a certain area, that is, in accordance with the operation range of the subsequent stage.

  In the first and second embodiments, an example of adjusting the electrode area of the wiring contributing to the floating diffusion 38 when adjusting the area of the floating diffusion 38 has been described. However, the electrode area is adjusted by other methods. You can also For example, this can also be realized by adjusting the length of the wiring metal film 560b provided in the interlayer film 542.

  The adjustment of the wiring length can be realized by adjusting the wiring route (for example, a linear shape or a zigzag shape and a difference in the shape). Alternatively, it can be realized by adjusting the width of the wiring metal film 560b provided in the interlayer film 542. Of course, the area of the floating diffusion 38 can be adjusted by adjusting both the wiring length and the wiring width. It suffices to adjust at least one of the wiring length and the wiring width, and which one is to be adjusted is preferably determined from the ease of device configuration.

  In the case of the method of adjusting the wiring width, at first glance, the wiring metal film 560b seems to be composed of only the connection electrode member, but if it is considered that the electrical signal is transmitted through the shortest route, the connection point The portion on the center line connecting the two (for example, the portion corresponding to the minimum line width in the device formation) functions as a connection electrode member that contributes exclusively to the connection between the detection unit and the unit signal generation unit, and its peripheral part substantially contributes to the connection. It may be considered that it functions as a capacitance adjusting electrode member that does not contribute.

  Further, instead of the method of adjusting the electrode area of the wiring that contributes to the floating diffusion 38, the FD capacitance can be adjusted and the conversion efficiency can be adjusted by adjusting the area of the diffusion layer 532b that is the main part contributing to the formation of the floating diffusion 38. By adjusting the signal conversion characteristic, the signal conversion characteristic can be set in the linear region. This method does not require the formation of a new electrode (metal wiring film 564), and is considered to be an easy method for adjusting the conversion efficiency by changing the FD capacitance.

<FD wiring layout method>
7 to 10 are diagrams for explaining a method of adjusting the wiring configuration of the electrode member that contributes to the capacitance formation of the floating diffusion 38 when adjusting the conversion efficiency by changing the FD capacitance. Here, FIG. 7 is a diagram showing a normal layout example of the FD wiring as a comparative example, and FIGS. 8 to 10 show a layout method of the FD wiring suitable for the first and second embodiments. FIG.

  In a normal wiring configuration, as shown in FIG. 7, a charge generation unit 32 (photoelectric conversion region) having a photoelectric conversion function for converting light into charges and a charge storage function, a read selection transistor 34, and a reset transistor 36. An activation region (for example, 32a, 38a) that forms the vertical selection transistor 40 or the amplification transistor 42 (transfer gate) is provided.

  Then, each gate wiring (transfer gate 34G, reset gate 36G) is made of polysilicon or the like on the individualized regions forming the read selection transistor 34, the reset transistor 36, the vertical selection transistor 40, and the amplification transistor 42 (transfer gate). , The selection gate 40G and the amplification gate 42G) are patterned. Further, a metal wiring 53M that forms a vertical signal line 53 for outputting a pixel signal along one side of the charge generation unit 32 is patterned at a subsequent stage (right side in the drawing) of the selection gate 40G. Each gate electrode is electrically connected to the lower layer through a contact.

  Here, the activation region 38a that forms the floating diffusion (FD) 38 is connected to the amplification gate 203 via a metal wiring (FD wiring 38FD) in a predetermined wiring layer. Usually, the FD wiring 38FD uses a minimum line width limited in terms of process. In addition, the layout is made so as to connect with the shortest possible route while considering the relationship with the peripheral members. Such a layout form is referred to as a “layout that forms a substantially shortest route”. In the layout example shown in FIG. 7, three straight lines are connected at right angles.

  On the other hand, as a layout method of the FD wiring 38FD for realizing the first and second embodiments, for example, as in the first example shown in FIG. By adopting a method of laying out in a hidden line form (patterning) different from the layout “forming the route”), the wiring length and the wiring width (that is, the electrode area) are adjusted so that the signal conversion characteristics fall within the linear region. The capacity of the part can be adjusted.

  In the patterning example shown in FIG. 8, the right-angle portions are connected by oblique wiring, that is, the patterning is performed by changing to a bending method different from the normal one, so the wiring length is shorter than the normal layout shown in FIG. Therefore, in order to provide an extra capacity than the normal layout shown in FIG. 7, the electrode width of the diagonal wiring portion may be made wider (thicker) than the right-angle wiring portion patterned with the minimum line width.

  Further, as in the second example shown in FIG. 9, other than the normal FD wiring 38FD that plays a role of connection between nodes (in this example, between the activation region 38a forming the floating diffusion (FD) 38 and the amplification gate 203). Even if a technique of connecting an extra metal wiring (additional wiring 38ad) to the FD wiring 38FD in the same wiring layer as the layer where the FD wiring 38FD is formed, the signal conversion characteristics are in the linear region. The capacitance of the FD portion can be adjusted by adjusting the electrode area of the FD portion so as to be accommodated.

  This method is the same as the method of providing metal wiring films 564b and 564c as additional wirings in addition to the metal wiring film 564a used for connection between nodes in FIG. This additional wiring can be patterned using a line width different from the normal minimum line width (actually thicker than the minimum line width).

  Alternatively, as in the third example shown in FIG. 10, the whole is a normal wiring route similar to that shown in FIG. 7, that is, it is configured as an electrode member that plays a role of connecting to other nodes as a whole. However, a method of patterning a part or all (that is, at least a part) of the FD wiring 38FD using a line width different from the normal minimum line width (actually making it thicker than the minimum line width). Even if it is adopted, the capacitance of the FD part can be adjusted by adjusting the electrode area of the FD part so that the signal conversion characteristics fall within the linear region.

<Third Embodiment>
FIG. 11 is a diagram for explaining a third embodiment of the present invention, showing a source follower circuit (A) and a small signal equivalent circuit (B) thereof. In FIG. 11, the vertical selection transistor 40 is omitted.

  In the third embodiment, by changing the gate length of the amplifying transistor 42 in the unit pixel 3, the gain Gain of the source follower constituted by the amplifying transistor 42 and the load MOS transistor 27 is changed, and the sensitivity is changed to the pixel. It is characterized in that it is corrected in an analog manner.

  When the mutual conductance of the amplifying transistor 42 is gm, the drain conductance is gd, and the drain conductance of the load MOS transistor 27 is gdL, the gain Gain of the source follower is expressed by Expression (1). From the equation (1), it can be seen that the gain Gain increases as the mutual conductance gm of the amplifying transistor 42 increases.

  Here, the mutual conductance gm is proportional to the ratio (W / L) of the gate width W and the gate length L of the amplifying transistor 42 as shown in the equation (2). For this reason, as the gate length L of the amplifying transistor 42 is shorter, the mutual conductance gm is increased and the gain Gain of the source follower is also increased.

  That is, by changing the gate length L of the amplifying transistor 42 in accordance with the wavelength, the gain Gain of the source follower is changed for each wavelength, that is, the signal conversion capability with respect to the light amount change can be adjusted depending on the wavelength. it can.

  In the solid-state imaging device 1, in general, the sensitivity is not constant for all pixels, and the sensitivity differs for each pixel depending on the wavelength dependency of the photoelectric conversion element and the difference in the characteristics of the color filter. As a result, when a signal from the unit pixel 3 is read, there is a possibility that a region without the linearity of the source follower may be used.

  However, the sensitivity of the amplifying transistor 42 can be adjusted by changing the gate length L of the amplifying transistor 42 as described above. It is possible to avoid using a non-linear region of the source follower for all pixels.

  Further, this mechanism corrects the sensitivity in an analog manner in the unit pixel 3 by changing the gate length L on the gate side of the amplifying transistor 42, so that a natural image can be obtained without impairing the gradation. It can also be obtained.

  Here, the mechanism for correcting the sensitivity by changing the gate length L has been described. However, as can be seen from the equation (2), the gain Gain of the source follower is adjusted by adjusting the gate width W of the amplifying transistor 42. For example, as the gate width W increases, the mutual conductance gm increases and the gain Gain of the source follower also increases.

  Of course, the gain Gain of the source follower can be changed by adjusting both the gate length L and the gate width W. It suffices to adjust at least one of the gate length L and the gate width W, and which one is to be adjusted is preferably determined from the ease of device configuration. For example, in the device design, when the gate width W is changed, the layout of other portions may need to be changed. Such a case is preferably dealt with by changing the gate length L.

<Fourth embodiment>
FIG. 12 is a diagram for explaining a fourth embodiment of the present invention, and is a diagram showing an example of a cross-sectional structure near the floating diffusion in the unit pixel 3 shown in FIG. FIG. 12 shows a cross section of the reset transistor 36, the floating diffusion 38, and the amplifying transistor 42.

  The fourth embodiment is similar to the first or second embodiment in that a configuration that changes the FD conversion efficiency by adjusting the FD capacity is used, but there is a difference in the adjustment method. Specifically, it is characterized in that it is realized by changing the impurity concentration of the floating diffusion 38 instead of adjusting the area of the floating diffusion 38 using the metal wiring film 564.

  As can be seen from the cross-sectional structure near the floating diffusion 38 in the unit pixel 3 shown in FIG. 12, the capacitance component of the floating diffusion 38 is determined from the diffusion capacitance, the overlap capacitance with the gate, the wiring capacitance, and the like. When the signal charge Q accumulated in a photoelectric conversion element such as a photodiode is transferred to the floating diffusion 38 by the read selection transistor 34 which is a transfer gate, it is converted into a signal voltage V corresponding to the signal charge Q and is used for amplification. The signal is input to the gate of the transistor 42 and output from the source follower circuit with the load MOS transistor 27.

  The conversion efficiency (V / Q) in the floating diffusion 38 is inversely proportional to the capacitance C of the floating diffusion 38 from the relational expression Q = CV. That is, the smaller the capacitance C of the floating diffusion 38, the higher the conversion efficiency, and a larger signal voltage can be obtained for the same signal charge amount.

  Since the conversion efficiency can be changed by the capacitance C of the floating diffusion 38, the sensitivity for each pixel can be corrected by adjusting the impurity concentration of the floating diffusion 38 for each pixel.

  Therefore, as shown in FIG. 12, with respect to the constituent members (particularly, the diffusion layer 532b) constituting the floating diffusion 38, the diffusion density of impurities is adjusted for each pixel to increase the FD capacitance, so that the first or second As in the configuration of the embodiment, the FD conversion efficiency can be reduced, and the output range of the pixel signal is set within the region where the source follower is linear, that is, the FD conversion efficiency is adjusted according to the operation range of the subsequent stage. be able to.

  This mechanism also corrects the sensitivity in an analog manner within the unit pixel 3 by changing the conversion efficiency by changing the capacitance of the floating diffusion 38 on the gate side of the amplifying transistor 42, and the gradation is lost. Natural images can also be obtained without being lost.

<Fifth Embodiment>
FIGS. 13 and 14 are diagrams illustrating an output state with respect to a sensor incident light amount, for explaining a fifth embodiment of the present invention. Here, FIG. 13 is a diagram for explaining an output state with respect to the light amount of the central portion and the peripheral portion (corner pixel) in the imaging unit 10. FIG. 14 is a diagram for explaining an output state with respect to the light amount of the central portion and the peripheral portion (corner pixel) in the imaging unit 10 after the fifth embodiment is applied.

  In the fifth embodiment, by using the configuration described in the first to fourth embodiments, the signal conversion capability of the unit pixel 3 that is a unit component is set for each pixel position (that is, place) in the imaging area. It is characterized in that the signal conversion capability is adjusted according to the location dependency of the incident physical quantity by adjusting and setting.

  As a specific example, here, the configuration for adjusting the FD capacity described in the first or second embodiment is used to suppress optical shading, which is an example of the location dependence of a physical quantity. That is, for the optical shading described in the section of the prior art in which the sensitivity decreases as the distance from the center of the pixel portion increases toward the peripheral portion, the optical shading is connected to the diffusion layer of the floating diffusion 38 described in the first or second embodiment. By adjusting the area of the metal wiring film 564 as the second metal wiring according to the optical shading and changing the FD conversion efficiency for each pixel position, the sensitivity of the entire imaging area (imaging unit 10) is made uniform, Try to suppress optical shading.

  For example, as shown in FIG. 13, light is greatly kicked in the corner pixels with respect to the central pixel, so that the amount of light hitting the light receiving portion is reduced and optical sensitivity is lowered. In contrast, as described in the first or second embodiment, the metal wiring film 564 is connected to the floating diffusion 38 to increase the wiring capacitance.

  At this time, the area of the metal wiring film 564 in the protective film 544 (on the interlayer film 542) that reduces the conversion efficiency is reduced from the central portion (array central portion) to the peripheral portion (array peripheral portion) in the imaging unit 10. Accordingly, as shown in FIG. 14, the FD conversion efficiency can be increased around the array.

  FIG. 14 shows an example in which the FD conversion efficiency of peripheral pixels is doubled in the center of the array. In this case, the sensitivity to the sensor incident light is uniform between the array central portion and the array peripheral portion. In this way, by adjusting the capacitance of the floating diffusion 38 part using the metal wiring film 564 and changing the area thereof, it is possible to suppress the phenomenon that the periphery becomes dark when a uniform white image is taken. .

  Note that, by reducing the capacity and increasing the conversion efficiency, the saturation output level of the pixel signal output from the unit pixel 3 in the peripheral part of the imaging unit 10 is changed to that of the pixel signal output from the unit pixel 3 in the central part. Doubles the saturation output level. In this state, when a high-level subject is imaged as a whole in which the central part is saturated, the peripheral part becomes whiter than the central part and becomes unnatural.

  For this reason, with respect to the pixel signal output from the unit pixel 3 in the peripheral part of the imaging unit 10, the pixel in the central part is not used as an effective signal part without using a part larger than the saturation output level of the pixel signal in the central part. Use the saturated output level of the signal instead. In this way, the excessive output level in the peripheral part can be clipped at the same saturation output level as in the central part, and even when a high-level subject is imaged as a whole, the central part is saturated as a whole. Can be made uniform white.

  In the fifth embodiment, when adjusting the area of the floating diffusion 38 according to the optical shading, an example is shown in which the electrode area of the wiring contributing to the floating diffusion 38 is adjusted in a direction that cancels the optical shading. By other methods, the electrode area can be adjusted in a direction to cancel the optical shading according to the optical shading.

  For example, this can also be realized by adjusting the length of the wiring metal film 560b provided in the interlayer film 542. The adjustment of the wiring length can be realized by adjusting the wiring route (for example, a linear shape or a zigzag shape and a difference in the shape). Alternatively, it can be realized by adjusting the width of the wiring metal film 560b provided in the interlayer film 542. Of course, the area of the floating diffusion 38 can be adjusted by adjusting both the wiring length and the wiring width. It suffices to adjust at least one of the wiring length and the wiring width, and which one is to be adjusted is preferably determined from the ease of device configuration.

<Conceptual diagram of FD area adjustment>
FIG. 15 is a conceptual diagram for explaining the concept of adjusting the area of the floating diffusion 38 according to optical shading. The incident light with respect to the distance from the center of the sensor and the load wiring 39 (dummy connected to the floating diffusion 38) It is a figure which shows the relationship of the area of the metal wiring film 564 which comprises wiring.

  Since there is a capacity hanging from the original floating diffusion 38, in order to align the sensitivity (optical + electrical) of the peripheral part (sensor end) of the imaging unit 10 with the central part, a metal wiring film 564 forming a dummy wiring is provided. It is necessary to increase the difference in capacitance formed by the above. However, if there is a layout restriction, it must be done within that range.

<Example of FD area adjustment>
FIG. 16 is a diagram for explaining a specific example of adjusting the area of the floating diffusion 38 in accordance with optical shading, and is an image diagram of the metal wiring film 564 connected to the floating diffusion 38 at each sensor location.

  As the distance from the center of the imaging unit 10 having the highest optical sensitivity increases, the area of the metal wiring film 564 forming the dummy wiring should be reduced. In the figure, the electrode area is set in four stages, but it is more preferable if the number of stages is further increased.

  As a result, the conversion efficiency can be increased by decreasing the capacitance formed by the metal wiring film 564 as the distance from the center portion, and conversely, the conversion efficiency can be decreased by increasing the capacitance as it approaches the center portion. Therefore, correction opposite in phase to optical shading can be performed, that is, the electrode area of the metal wiring film 564 can be adjusted in a direction to cancel the optical shading. However, the area for correction is limited due to layout restrictions and the capacity range of the floating diffusion 38 that is desired to be used.

  Although the figure shows an example in which the electrode area is set in multiple stages (4 stages in the figure) according to the optical shading, it is only necessary to suppress the optical shading as much as possible. May be set in two steps: a wide electrode and a peripheral electrode that is narrow.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above embodiment, as a specific method for setting the signal conversion characteristics of the unit components in the linear region, the wiring is connected and the wiring width and length are adjusted to adjust the capacitance of the charge storage unit. Or adjusting the impurity concentration in the charge storage unit, adjusting the area of the diffusion layer, or adjusting the gate length or gate width of the semiconductor element. As long as the method is not a method of applying an operation to the above, other methods can be adopted.

  In short, what is necessary is to set the signal conversion characteristics of the unit component in the linear region by actively operating various members constituting the unit component in the unit component. Various methods may be adopted. This is because the method described in the above embodiment is merely one example.

  Further, in the description of the above-described embodiment, the physical quantity (light) generated by the charge generation unit can be changed by positively operating various members constituting the pixel signal generation unit in the unit component. The example in which the signal conversion capability of the pixel signal output from the pixel signal generation unit 5 with respect to the corresponding signal charge is adjusted and thereby the signal conversion characteristic of the unit component is set in the linear region has been described. May be any one within the unit pixel 3.

  Any operation method can be adopted as long as it is not a method of performing an operation on a physical quantity (for example, light amount) incident on the detection unit, and is not limited to the constituent members of the pixel signal generation unit 5, for example, on the charge generation unit 32. You may implement | achieve by adding predetermined operation. This is because even if the physical quantity change incident on the detection unit is the same, the conversion efficiency of the unit signal generation unit is the same by making the size of the detection information detected by the detection unit different. This is because the size of the unit signal output from each of the unit signal generation units, that is, the unit components can be set in the linear region of the source follower.

1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a configuration example of a unit pixel according to the first embodiment. 3 is a timing chart for explaining a method for driving a unit pixel shown in FIG. 2 to acquire a pixel signal. FIG. 3 is a diagram illustrating a cross-sectional structure example near a floating diffusion in the unit pixel illustrated in FIG. 2. It is a circuit diagram of a configuration example of a unit pixel according to the second embodiment. FIG. 6 is a diagram illustrating a cross-sectional structure example in the vicinity of the floating diffusion in the unit pixel illustrated in FIG. 5. It is a figure explaining the method of adjusting the wiring form of the electrode member (FD wiring) which contributes to FD capacity | capacitance formation (normal layout example). It is a figure explaining the method of adjusting the wiring form of the electrode member which contributes to FD capacity | capacitance formation (1st example of embodiment). It is a figure explaining the method of adjusting the wiring form of the electrode member which contributes to FD capacity | capacitance formation (2nd example of embodiment). It is a figure explaining the method of adjusting the wiring form of the electrode member which contributes to FD capacity | capacitance formation (3rd example of embodiment). It is a figure which shows the source follower circuit comprised by the transistor for amplification and load MOS transistor, and its small signal equivalent circuit. It is a figure which shows the cross-sectional structure example of the floating diffusion vicinity in the unit pixel which concerns on 4th Embodiment. It is a figure explaining the mode of the output with respect to the light quantity of the center part and peripheral part (corner pixel) in an imaging part. It is a figure explaining the mode of the output with respect to the light quantity of the center part and peripheral part (corner pixel) in the image pick-up part after applying 5th Embodiment. It is a conceptual diagram explaining the idea at the time of adjusting the area of a floating diffusion according to optical shading. It is a figure explaining the specific example which adjusts the area of a floating diffusion according to optical shading. It is a figure explaining the relationship of the electric potential in the vertical signal line with respect to FD electric potential. It is a figure which shows the cross-section structural example of the floating diffusion vicinity in a pixel. It is a figure explaining a shading phenomenon.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 5 ... Pixel signal generation part, 3 ... Unit pixel, 7 ... Drive control part, 10 ... Imaging part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 15 ... Vertical control line, 16 ... Drive Signal operation unit, 18 ... vertical signal line, 20 ... column processing unit, 22 ... column signal processing unit, 27 ... load MOS transistor, 28 ... horizontal signal line, 29 ... output circuit, 32 ... charge generation unit, 34 ... read selection Transistor 36 ... reset transistor 38 ... floating diffusion 39 load wiring 40 vertical selection transistor 42 amplification transistor 532 diffusion layer 540 542 interlayer film 544 protective film 550 552 ... Connection hole, 564 ... Metal wiring film

Claims (13)

A charge generation unit that generates a signal charge in response to received light;
A unit signal generation unit that generates a unit signal based on the signal charge generated by the charge generation unit in a unit component,
A semiconductor device for light detection in which the unit components are arranged in a predetermined order,
The unit signal generation unit has at least one charge storage wiring layer for storing the signal charge in an electrically floating state,
The charge storage wiring layer is
A main connection wiring part that contributes to the connection between the semiconductor element that generates the unit signal in the unit signal generation part and the charge generation part;
A wiring portion that does not contribute to the connection;
Have
An adjustment capacitor that sets a signal conversion characteristic of the unit component in a linear region is formed by the wiring portion that does not contribute to the connection. A charge generation unit that generates a signal charge in response to received light;
A unit signal generation unit that generates a unit signal based on the signal charge generated by the charge generation unit in a unit component,
A semiconductor device for light detection in which the unit components are arranged in a predetermined order,
The unit signal generation unit has at least one charge storage wiring layer for storing the signal charge in an electrically floating state,
The charge storage wiring layer is
A main connection wiring portion that contributes to a connection between the semiconductor element that generates the unit signal in the unit signal generation unit and the charge generation unit;
A portion having a larger line width than the minimum line width of the main connection wiring portion, and an additional wiring portion for assisting the connection;
Have
An adjustment capacitor that sets a signal conversion characteristic of the unit component in a linear region is formed by the additional wiring portion. A charge generation unit that generates a signal charge in response to received light;
A unit signal generation unit that generates a unit signal based on the signal charge generated by the charge generation unit in a unit component,
A semiconductor device for light detection in which the unit components are arranged in a predetermined order,
The unit signal generation unit has at least one charge storage wiring layer for storing the signal charge in an electrically floating state,
The charge storage wiring layer is
Two main connection wiring portions arranged on the respective sides of the semiconductor element that generates the unit signal in the unit signal generation unit and the charge generation unit and spaced apart from each other;
An additional wiring part connected between the two main connection wiring parts so as to bypass the wiring at a distance longer than the separation distance between the two main connection wiring parts;
Have
An adjustment capacitor that sets a signal conversion characteristic of the unit component in a linear region is formed by the additional wiring portion. The semiconductor device according to claim 1, wherein the adjustment capacitor is formed as a part of a pattern of the charge storage wiring layer. The adjustment capacitor is formed by the wiring capacitance added from the case of a single layer by forming the charge storage wiring layer from a plurality of layers and forming the charge storage wiring layer as a plurality of layers. Semiconductor device. The adjustment capacitor is formed by a wiring capacitance added from the case of a single layer by forming the charge storage wiring layer from a plurality of layers and forming the charge storage wiring layer as a plurality of layers. Semiconductor device. The semiconductor device according to claim 6, wherein the charge storage wiring layer is arranged separately in two parts on the same layer, and the two parts are connected via another charge storage wiring layer on the upper layer. The charge storage wiring layer is
The wiring of the said unit signal generating unit and the front Symbol electrostatic load generator as the main connection wiring portion for electrically connecting,
Connected to the wiring for the formation of the adjustment capacitor, there is no connection location other than the connection location with the wiring, there is no role of circuit connection, load wiring as a wiring portion that does not contribute to the connection,
The semiconductor device according to claim 1, comprising: Before SL electrostatic load generator includes a semiconductor impurity regions,
The impurity concentration of the semiconductor impurity region and the adjustment capacitance of the charge storage wiring layer are set so that the signal conversion characteristic of the unit component is a linear region. A semiconductor device according to 1. The signal conversion capability of each of the unit components is adjusted by changing the value of the adjustment capacitance depending on the location where light is incident within the arrangement of the unit components. The semiconductor device according to any one of the above. The unit signal generation unit is configured to include a semiconductor element for signal amplification,
The semiconductor device according to claim 10, wherein a value of at least one of a gate length and a gate width of the semiconductor element changes in the arrangement of the unit components depending on a place where the light is incident. The unit signal generator is configured with a semiconductor impurity regions for accumulating the signal charges generated in the previous SL electrostatic load generator,
The semiconductor device according to claim 10, wherein a capacitance value of the semiconductor impurity region changes within the arrangement of the unit components depending on a place where the light is incident. The semiconductor device according to claim 12, wherein an impurity concentration of the semiconductor impurity region changes within the arrangement of the unit components depending on a place where the light is incident.