JP4830732B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a terminal insulating region that extends around a cell area in which a semiconductor structure that functions as a semiconductor device is formed.

2. Description of the Related Art A technique for developing a semiconductor structure that functions as a semiconductor device on a semiconductor substrate in which a body region is stacked on the surface of a drift region has been developed. For example, a technology for realizing a MOS, IGBT, diode, or the like using a drift region and a body region has been developed.
In this type of semiconductor device, by forming a terminal insulating region that goes around the cell area outside the range (cell area) in which a semiconductor structure that functions as a MOS, IGBT, diode, or the like is formed, It is known that the breakdown voltage can be increased. Usually, at least double termination trenches extending around the cell area are formed, and each termination trench is filled with a termination insulating region. Each termination trench penetrates the body region from the surface of the semiconductor substrate and reaches the drift region. Therefore, each termination insulating region also penetrates the body region and reaches the drift region. Each terminal insulating region has a closed loop shape that goes around the cell area. For this reason, the body regions located inside and outside the innermost terminal insulating region are insulated from each other.

An example of the above is disclosed in Patent Document 1. 7 is a plan view of the semiconductor device 500 of Patent Document 1, and FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. To be precise, FIG. 7 is a sectional view taken along line VII-VII in FIG. However, in FIG. 7, the hatching with respect to the drain region 512 is omitted.
The semiconductor device 500 is manufactured by using a semiconductor substrate 502 having an outer periphery 504. The semiconductor substrate 502 is formed from an n ⁺ drain region 511, an n ⁻ drift region 512, and a p ⁻ body from the back surface side to the front surface side. The regions 541 are stacked in this order.
Triple termination trenches 563-1 to 563-3 extending along the outer periphery 504 inside the outer periphery 504 of the semiconductor substrate 502 are formed. Each of the termination trenches 563-1 to 563-3 is filled with termination insulating regions 573-1 to 573-3. Each of the termination trenches 563-1 to 563-3 penetrates the body region 541 from the surface 501 of the semiconductor substrate 502 and reaches the drift region 512, and each of the termination insulating regions 573-1 to 573-3 is also the body region 541. And reaches the drift region 512. The terminal insulating regions 573-1 to 573-3 have a closed loop shape that makes a circuit along the outer periphery 504 of the semiconductor substrate 502. The body region 541a located inside the innermost terminal insulating region 573-1 and the body region 541b located outside are insulated. The body region 541b located inside the intermediate terminal insulating region 573-2 and the body region 541c located outside are also insulated.
In the inner range (cell area 505) of the innermost termination insulating region 573-1, a plurality (6 as an example in the figure) that penetrates the body region 541 from the surface 501 of the semiconductor substrate 502 and reaches the drift region 512. The main trench 513 is formed. At least a wall surface of each main trench 513 is covered with a main insulating region 523. A gate electrode 522 is embedded in each main trench 513 in a state where it is insulated from the semiconductor substrate 502 by the main insulating region 523. Each gate electrode 522 passes through the body region 541 and reaches the drift region 512. Each main trench 513 extends deeper than each gate electrode 522, and is filled with the main insulating region 523 at a depth where the gate electrode 522 does not exist.
An n ⁺ source region 531 is formed at a position adjacent to the main trench 513 on the surface 501 of the semiconductor substrate 502. A p ⁺ body contact region 532 is formed on the surface 501 of the body region 541a of the cell area 505.
A source electrode 533 is formed on the surfaces of the n ⁺ source region 531 and the p ⁺ body contact region 532, and the source electrode 533 is connected to the source wiring S. The gate electrode 522 is connected to the gate wiring G. The n ⁺ drain region 511 is connected to the drain wiring D. The drain wiring D is connected to a positive potential, and the source wiring S is grounded.
The semiconductor device 500 can control a current flowing between the source wiring S and the drain wiring D by controlling a voltage applied to the gate wiring G, and operates as a transistor.
The semiconductor device 500 is divided into a cell area 505 in which a semiconductor structure that operates as a transistor is formed, and a termination area 507 in which termination insulating regions 573-1 to 573-3 surrounding the cell area 505 are formed. .
A dummy gate electrode 524 is embedded in the innermost terminal insulating region 573-1. The dummy gate electrode 524 has the same material and the same shape as the gate electrode 522 formed in the cell area 505.

According to the semiconductor device 500, when the gate voltage is off, the depletion layer spreads widely toward the p ⁻ body region 541 and the drift region 512 in both the cell area 505 and the termination area 507, thereby increasing the breakdown voltage of the semiconductor device 500. be able to.
JP 2006-128507 A

However, in the semiconductor device 500 of Patent Document 1, the body region 541b located outside the innermost terminal insulating region 573-1 is not connected to any electrode and is insulated from the surroundings (this state) This is called a floating state), and the potential fluctuates unstablely.
For this reason, in the semiconductor device 500, when the gate voltage is off, the potential difference between the body region 541b located outside the innermost termination insulating region 573-1 and the dummy gate electrode 524 becomes large, thereby insulating the two. A high voltage may be applied to the terminal insulating region 573-1. In particular, in the portion indicated by the circle M in FIG. 8, since the electric field concentration is likely to occur at the corner portion of the dummy gate electrode 524, the insulating film 573-1 may be broken.
In the case of a semiconductor device that uses a ring-shaped terminal insulating region to ensure a withstand voltage, the insulating film is destroyed because the body region located outside the ring-shaped terminal insulating region forming the closed loop is in a floating state. Sometimes.

  In order to solve this problem, it is important to connect the body region located outside the ring-shaped terminal insulating region forming the closed loop to the source electrode S. However, since the surface of the semiconductor substrate in the termination area is usually covered with an interlayer insulating film thicker than the cell area, the contact for connecting the body region located outside the ring-shaped termination insulating region to the source electrode S is often used. It is difficult to form a hole. Further, usually, the interval between the termination trenches in the termination area is often shorter than the interval between the main trenches in the cell area, and it is difficult to form a contact region between the termination trenches.

  In the present invention, since the body region located outside the ring-shaped terminal insulating region forming the closed loop is in a floating state, a countermeasure against an event that the insulating film is broken due to a high potential is taken. In the present invention, the potential of the body region located outside the termination insulating region is prevented from unstablely changing.

The semiconductor device of the present invention surrounds a semiconductor substrate in which a body region of the first conductivity type is laminated on the surface of the drift region of the second conductivity type, and a cell area in which a semiconductor structure that functions as a semiconductor device is built. And at least double termination trenches extending from the surface of the semiconductor substrate to the drift region through the body region, and termination insulating regions filling each termination trench. At least the innermost terminal insulating region is cut at at least one point in a loop that goes around the outside of the cell area. Thereby, conduction between the body regions located inside and outside the innermost terminal insulating region is ensured.
In the case of this semiconductor device, in the portion where the termination insulating region is cut, a body region is provided to connect the inner body region and the outer body region of the innermost termination insulating region, and at least the innermost termination insulation is secured. The body region located outside the region is electrically connected to the body region located inside the region.
In general, the body region located inside the innermost termination insulating region (that is, the body region located in the cell area) is not in a floating state, and is stable in potential (otherwise the operation of the semiconductor device) Becomes unstable). For example, in the case illustrated in FIG. 7, the body region 541a located in the cell area 505 is grounded via the source electrode S and is fixed to the GND voltage. The same applies to the IGBT, and the body region located in the cell area is grounded via the source electrode and is fixed to the GND voltage. In the case of a diode, the body region located in the cell area is connected to the anode electrode or the cathode electrode and is not in a floating state.
If at least the body region located outside the innermost termination insulating region is electrically connected to the body region located inside the semiconductor region, it is possible to prevent an excessive voltage from acting on the innermost termination insulating region. The withstand voltage can be improved.

In one specific form of the present invention, the following structure is formed on the semiconductor substrate (that is, the cell area) inside the innermost terminal insulating region.
A main trench is formed through the body region from the surface of the semiconductor substrate to reach the drift region. At least the wall surface of the main trench is covered with the main insulating region. A gate electrode is accommodated inside the main trench in a state insulated from the semiconductor substrate by the main insulating region. The gate electrode penetrates the body region from the surface of the semiconductor substrate and reaches the drift region. A source region of the second conductivity type is formed at a position adjacent to the main trench on the surface of the semiconductor substrate. A body contact region containing a high concentration of the first conductivity type impurity is formed on the surface of the body region.
The source region and the body contact region formed in the cell area of the semiconductor substrate are connected to the source electrode.

In the aforementioned semiconductor device, a semiconductor structure formed in the cell area to the transistor operation.
In this case, the body region outside the innermost termination insulating region is electrically connected to the body region in the cell area through the cut of the termination insulating region, and the body region in the cell area is fixed to the potential of the source electrode. ing. Therefore, when the transistor is turned off, the potential of the body region located outside the innermost termination insulating region does not fluctuate unstably. An excessive voltage is not applied to the innermost terminal insulating region, and the breakdown voltage of the semiconductor device can be improved.
Further, in the above semiconductor device, the innermost terminal insulating region is cut at a position extending in parallel with the main trench formed in the cell area.
In this case, there is substantially no reduction in breakdown voltage that can occur by cutting the terminal insulating region. When the main trench extends in one direction in the cell area, the semiconductor device is likely to be destroyed in the vicinity of the outer periphery extending in the direction orthogonal to the outer periphery of the semiconductor substrate extending in parallel to the cell trench. If the termination insulating region extends seamlessly on the outer periphery orthogonal to the main trench, the withstand voltage improvement effect by the termination insulating region can be obtained. If the termination insulating region is cut at a position extending in parallel with the main trench, it is possible to prevent a reduction in the breakdown voltage improvement effect caused by cutting the termination insulating region from becoming a practical problem.

When a semiconductor structure that operates as a transistor is formed in the cell area using a trench gate electrode, a conductor made of the same material as the trench gate electrode is buried in the innermost terminal insulating region to the same depth as the trench gate electrode. The dummy trench gate electrode is preferably maintained at the same potential as other trench gate electrodes.
By providing the dummy trench gate electrode, the depletion layer can be widely expanded toward both the body region and the drift region in both the cell area and the termination area, and the breakdown voltage of the semiconductor device can be increased. On the other hand, the insulating film that insulates the dummy trench gate electrode from the body region is likely to be thin, and the insulating film is easily destroyed.
The present invention in which the inner body region and the outer body region of the termination insulating region are made conductive by cutting the termination insulating region functions particularly effectively when a dummy trench gate electrode is used. The breakdown of the thin insulating film that insulates the dummy trench gate electrode and the body region in the termination area can be prevented.

When cutting the terminal insulating region, it is preferable to cut so that a body region having a width of 1.1 μm or less remains.
If the break is 1.1 μm or less, a decrease in breakdown voltage that can be caused by cutting the terminal insulating region does not become a practical problem.

It is preferable that an impurity of the first conductivity type is implanted into the walls facing each other across the cut portion of the termination trench constituting the termination insulating region. That is, since the second conductivity type drift region is exposed on the walls facing each other across the cut portion of the termination trench, it is preferable that the first conductivity type impurity is implanted therein.
Also in this case, it is possible to prevent a decrease in the withstand voltage improvement effect that can be caused by cutting the terminal insulating region from becoming a practical problem.

The main features of the embodiments described below are first organized.
(Feature 1) The body region is p-type. If the present invention is not carried out, the p-type body region in the termination area will be in a floating state.
(Characteristic 2) After forming a terminal trench cut in part, a process of injecting impurities obliquely is performed, and p-type impurities are injected into the walls facing each other across the cut portion.

Hereinafter, an example of a semiconductor device embodying the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of a semiconductor device 100 according to the first embodiment, and FIG. 2 is a sectional view taken along line II-II in FIG. 1 is a cross-sectional view taken along line II-II in FIG. However, in FIG. 1, hatching for the drain region 112 is omitted.
The semiconductor device 100 is manufactured by using a semiconductor substrate 102 having an outer periphery 104. The semiconductor substrate 102 is formed from the back surface side to the front surface side by an n ⁺ drain region 111, an n ⁻ drift region 112, and a p ⁻ body. The regions 141 are stacked in this order.
Triple termination trenches 163-1 to 163-3 extending along the outer periphery 104 inside the outer periphery 104 of the semiconductor substrate 102 are formed. Each termination trench 163-1 to 163-3 is filled with termination insulating regions 173-1 to 173-3. Each termination trench 163-1 to 163-3 penetrates body region 141 from surface 101 of semiconductor substrate 102 to reach drift region 112, and each termination insulating region 173-1 to 173-3 is also body region 141. And reaches the drift region 112. The outer terminal insulating region 173-3 and the intermediate terminal insulating region 173-2 have a closed loop shape that makes a circuit along the outer periphery 104 of the semiconductor substrate 102. The innermost terminal insulating region 173-1 also extends along the outer periphery 104 of the semiconductor substrate 102. However, the cuts 199 and 199 are left at two places and are not closed loops. The body region 141a located inside the innermost terminal insulating region 173-1 and the body region 141b located outside are electrically connected to each other by cuts 199 and 199. Since the intermediate terminal insulating region 173-2 has a closed loop shape, the body region 141b located inside and the body region 141c located outside are insulated.
A p-type region 153 is formed along the bottom surfaces of ˜173-3 of termination insulating region 173-1. The p-type region 153 is a floating region insulated from the surroundings, and is formed so as to surround the lower end of the termination insulating region 173. The cross section of the p-type region 153 has a substantially circular shape with a radius of 0.6 μm centered on the bottom of the termination trench.

Six main trenches 113 that penetrate from the surface 101 of the semiconductor substrate 102 to the drift region 112 through the body region 141 are formed in the inner region (cell area 105) of the innermost termination insulating region 173-1. Has been. At least a wall surface of each main trench 113 is covered with a main insulating region 123. In each main trench 113, a gate electrode 122 is embedded in a state in which the main trench 113 is insulated from the semiconductor substrate 102 by the main insulating region 123. Each gate electrode 122 passes through the body region 141 and reaches the drift region 112. Each main trench 113 extends deeper than each gate electrode 122, and is filled with the main insulating region 123 at a depth where the gate electrode 122 does not exist.
A p-type region 151 is formed along the bottom surface of the main insulating region 123. The p-type region 151 is a floating region insulated from the surroundings, and is formed so as to surround the lower end of the main insulating region 123. The cross section of the p-type region 151 has a substantially circular shape with a radius of 0.6 μm centered on the bottom of the main trench.

A dummy gate electrode 124 is embedded in the innermost terminal insulating region 173-1. The dummy gate electrode 124 has the same material and the same shape as the gate electrode 122 formed in the cell area. The other termination trenches 162-2 and 162-3 are filled only with the termination insulating regions 173-2 and 173-2.
An n ⁺ source region 131 is formed at a position adjacent to the main trench 113 on the surface 101 of the semiconductor substrate 102. A p ⁺ body contact region 132 is formed on the surface 101 of the body region 141 a of the cell region 105.
A source electrode 133 is formed on the surfaces of the n ⁺ source region 131 and the p ⁺ body contact region 132, and the source electrode 133 is connected to the source line S. The gate electrode 122 is connected to the gate wiring G. The n ⁺ drain region 111 is connected to the drain wiring D. The drain wiring D is connected to a positive potential, and the source wire S is used while being grounded.
The semiconductor device 100 is divided into a cell area 105 in which a semiconductor structure that operates as a transistor is formed, and a termination area 107 in which termination insulating regions 173-1 to 173-3 surrounding the cell area 195 are formed. Yes.
The drift region 112 has an impurity concentration of 1.5 to 2.5 × 10 ¹⁶ / cm ³ , the body region 141 has an impurity concentration of 1.0 to 2.0 × 10 ¹⁷ / cm ³ , and the floating region 151. , 153 has an impurity concentration of 1.0 to 2.0 × 10 ¹⁷ / cm ³ . The concentration of the drain region 111, the source region 131, and the body contact region 132 is higher than that, and ohmic characteristics are secured between the drain region 111, the source region 131, and the body contact region 132.

  The main trench 113 and the termination trench 163 have the same depth. The body region 141 has a thickness of 1.0 μm, and the main trench 113 and the termination trench 163 have a depth of 2.5 μm. The pitch between the main trenches 113 (the distance between the centers of adjacent main trenches) is uniform at 2.5 μm. On the other hand, the pitch between the termination trenches 163 is uniform at 2.0 μm and is narrower than the pitch between the main trenches 113. The pitch between the outermost main trench 113 and the innermost termination trench 163-1 is 2.5 μm. Here, the pitch between the main trenches 113, the pitch between the outermost main trench 113 and the innermost termination trench 163-1, the pitch between the termination trenches 163, and the like are not limited to the above values. Generally, it is often set in a range of 2 to 3 μm.

  Although the structure of the semiconductor device 100 has been described with reference to FIG. 2, each component has a substantially uniform configuration along the extending direction of the main trench 113 or the termination trench 163. In addition, only one semiconductor device 100 is not necessarily formed on one semiconductor substrate. A plurality of semiconductor devices 100 may be formed on one semiconductor substrate. Alternatively, the semiconductor device 100 and other semiconductor devices may be formed together on one semiconductor substrate. The termination region 107 in this case is a range that surrounds the cell area 105 that forms the semiconductor device 100, and is not necessarily a range that extends along the outer periphery of the semiconductor substrate.

  Two cut portions 199 formed in the innermost terminal insulating region 173-1 are formed at a substantially central position of a portion extending in parallel with the main trench 113. Hereinafter, the cut portion 199 of the innermost terminal insulating region 173-1 will be described with reference to FIG. 3 is a cross-sectional view taken along line III-III of the semiconductor device 100 of FIG. The two cutting parts 199 have the same configuration and dimensions. The cutting part 199 is configured by the semiconductor substrate 102 interposed between both end faces 154a and 154b of the termination insulating region 173-1. Both end surfaces 154a and 154b of the terminal insulating region 173-1 are opposed to each other with the cut portion 199 interposed therebetween.

The distance G between the wall surface 154a that defines one end surface of the terminal insulating region 173-1 and the wall surface 154b that defines the other end surface is 1.1 μm or less.
The wall surfaces 154a and 154b are doped with p-type impurities. The impurities are implanted into the wall surfaces 154a and 154b by an oblique impurity implantation method. In the impurity implantation region 152, the resistance is low, and the body region 141a located inside the innermost termination insulating region 173-1 and the body region 141b located outside are maintained at the same potential.
The impurity concentration and thickness d of the impurity implantation region 152 are determined in consideration of the breakdown voltage of the semiconductor device 100. In order to maintain the breakdown voltage of the semiconductor device 100, it is ideal that the impurity implantation region 152 is completely depleted when the semiconductor device 100 is off. On the other hand, in order to maintain body regions 141a and 141b located inside and outside termination insulating region 173-1 at the same potential, the impurity concentration is preferably high. From the simulation, it has been found that if the peak concentration of the impurity is about 0.7 × 10 ¹⁶ / cm ³ and the thickness d is 0.3 μm, both breakdown voltage and conductivity can be achieved. Note that the periphery of the bottom surface of the termination insulating region 173-1 is covered with a floating region 153.

  The operation of the semiconductor device 100 according to the embodiment will be described below. The semiconductor device 100 is used in a state where the source electrode wiring S is grounded and maintained at the GND potential, and a positive voltage is applied to the drain wiring D. When a positive voltage is applied to the gate electrode 122, the body region 141a is inverted in a region facing the gate electrode 122, a channel is formed, and the source region 131 and the drain region 111 are electrically connected. Unless a positive voltage is applied to the gate electrode 122, no current flows between the source region 131 and the drain region 111. The semiconductor device 100 performs a transistor operation.

  When a positive voltage is not applied to gate electrode 122, a depletion layer extends from PN junction surface between drift region 112 and body region 141 toward drift region 112 and body region 141. When the tips of the depletion layers reach the floating regions 151 and 153, the drift region 112 from the PN junction surface with the body region 141 to the floating regions 151 and 153 is depleted. Further, since a positive voltage is applied to the drain wiring D, a depletion layer extends in the drift region 112 from the PN junction surface between the floating regions 151 and 153 and the drift region 112 toward the drain region 111. The electric field intensity has a peak at two locations, that is, the PN junction surface of the body region 141 and the drift region 112 and the PN junction surfaces of the floating regions 151 and 153 and the drift region 112. Since the peak of the electric field strength is dispersed and formed at two places, the peak of the maximum electric field strength can be reduced. Thereby, a high breakdown voltage can be achieved.

Further, the semiconductor device 100 of the present embodiment has the following characteristics because the main insulating region 123 is filled in the deep portion of the main trench 113. Since the floating region 151 is formed, for example, by injecting impurities into the bottom of the main trench 113, the bottom of the main trench 113 is damaged to some extent. When the main insulating region 123 is filled in the deep portion of the main trench 113, the influence of damage generated on the bottom surface of the main trench 113 can be avoided, and the reliability of the semiconductor device 100 can be prevented from being lowered.
Further, as compared with the case where the deep part of the main trench 113 is not filled with the main insulating region 123, the gate electrode 122 becomes smaller, the gate-drain capacitance Cgd becomes smaller, and the switching speed becomes faster.

  In the termination area 107 of the semiconductor device 100, neither the source region 131 nor the gate electrode 122 is formed, and no current flows. A termination insulating region 173 filled in the termination trench 163 functions as a guard ring for the cell area 105. When the semiconductor device 100 is off, electric field concentration tends to occur in the peripheral portion of the cell area 105. When the termination insulating region 173 surrounds the cell area 105, a depletion layer formed in the drift region 112 extends widely to the termination area 107, and electric field concentration is reduced. The electric field concentration is more effectively mitigated by the floating region 153. The breakdown voltage of the semiconductor device 100 can be increased without increasing the size of the termination area 107. Note that the number of the terminal insulating regions 173 is not limited to three. That is, the number of the terminal insulating regions 173 may be two (the minimum number) as long as the withstand voltage can be maintained. Further, if the withstand voltage cannot be maintained with three, it may be three or more.

The provision of the dummy trench gate electrode 124 in the innermost termination insulating region 173-1 has the following characteristics. That is, since the structure of the innermost termination insulating region 173-1 is the same as the structure of the main trench 123, the depletion layer extends widely even in the vicinity of the termination insulating region 173-1. Therefore, the depletion layer formed in the cell area 105 can be extended to the termination area 107 in the termination insulating region 173-1.
In the termination area 107, the pitch between the termination insulating regions 173 is set smaller than the pitch between the main insulation regions 123. When the semiconductor device 100 is off, the connection of the depletion layer in the termination area 107 can be promoted, and the breakdown voltage of the termination region can be increased.

In the semiconductor device 100 of the present embodiment, the breakdown voltage of the semiconductor device 100 is improved by cutting the innermost terminal insulating region 173-1.
Since the terminal insulating region 173-1 is cut, the inner body region 141a (the portion between the terminal insulating region 173-1 and the main insulating region 123) inside the innermost terminal insulating region 173-1 and the outer The body region 141b (the portion between the termination insulating region 173-1 and the termination insulating region 173-2) is electrically connected by the cut portion 199. Since the inner body region 141a is grounded through the body contact region 132, it is maintained at the GND potential. Accordingly, the outer body region 141b is also generally maintained at the GND potential. When the semiconductor device 100 is off, the potential of the outer body region 141b does not fluctuate in an unstable manner, and a high voltage is not applied to the termination insulating region 173-1.

  In the semiconductor device 100, the cut portion 199 is formed at a portion extending in parallel with the main trench 113. This also prevents the termination insulating region 173-1 from functioning as a guard ring and reducing the effect of maintaining the breakdown voltage. Specifically, when the semiconductor device 100 is off, a strong electric field concentration is likely to occur in the vicinity of a side extending perpendicularly to the main trench 113 (a side extending in the horizontal direction in FIG. 1). On the other hand, strong electric field concentration hardly occurs in the vicinity of the side extending in parallel with the main trench 113 (the side extending in the vertical direction on the left and right in FIG. 1). In the semiconductor device 100, since the cut portion 199 is formed in a portion where it is difficult to generate strong electric field concentration, it is suppressed that the effect as a guard ring is reduced by cutting the terminal insulating region 173-1. .

  Further, the two cut portions 199 are formed at substantially the center of the terminal insulating region 173-1 extending in the vertical direction on the left and right in FIG. Therefore, the cutting part 199 is formed at a position away from the side extending in the left-right direction in FIG. Furthermore, the potential of the body region 141b between the termination insulating region 173-1 and the termination insulating region 173-2 is easily maintained uniformly in the circumferential direction. Thereby, the withstand voltage characteristic with respect to the reverse voltage of the termination insulating region 173-1 can be maintained uniformly.

  When the specific resistance of the drain region 112 is 0.1 to 0.5 Ω · cm, the length G of the cut portion 199 (distance between both end surfaces 154a and 154b of the termination insulating region 173-1) is 1.1 μm or less. Preferably there is. In this case, it is confirmed by simulation that depletion layers extending from both end faces 154a and 154b of the termination insulating region 173-1 are connected when the semiconductor device 100 is off. Thereby, the termination insulating region 173-1 is cut, so that the effect as a guard ring is hardly lowered. In particular, when the length of the cut portion 199 is 1.1 μm, the electrical resistance of the cut portion 199 is sufficiently small, so that the termination insulating region 173-1 can sufficiently obtain a withstand voltage characteristic against a reverse voltage. .

Hereinafter, the effect of the gate semiconductor 100 of the embodiment will be verified with reference to FIGS. FIG. 4 is a diagram showing a range where a depletion layer expands when a reverse voltage of 70 V is applied to the semiconductor device, and FIG. 4A is a diagram showing a case of a conventional semiconductor device 500 as shown in FIG. ) Is a diagram showing a case of the semiconductor device 100 of the example. The coordinate Z in FIG. 4 indicates the depth (μm) from the surface of the semiconductor substrate, the hatched region is a portion where the depletion layer extends, and the white portion is a portion where the depletion layer does not spread.
FIG. 5 is a graph showing the potential distribution along the line CC in FIG. 4 when a reverse voltage of 70 V is applied. FIG. 5A shows the potential distribution of the conventional semiconductor device 500 as shown in FIG. FIG. 6B is a diagram illustrating a potential distribution of the semiconductor device 100 according to the embodiment. In FIG. 5, the coordinate Y indicates the potential (V), and the coordinate Z indicates the depth (μm) corresponding to the Z axis in FIG. 4 and 5 are the results of simulation.

In the case of the conventional semiconductor device 500, when the semiconductor device 500 is off, as shown in FIG. 4A, the body between the innermost terminal insulating region 573-1 and the outer terminal insulating region 573-2 is provided. Since the region 541b is insulated from the surroundings, electrons in the body region 541b are difficult to escape, and the depletion layer does not expand sufficiently. For this reason, the depletion layer cannot sufficiently spread even in the drift region 512 immediately below the body region 541b (note the circle N). Since the potential can be held only in the depleted region, the electric field in the depleted region is concentrated.
Further, as shown in FIG. 5A, the potential distribution along the line C-C indicates that the body region 541b between the innermost terminal insulating region 573-1 and the outer terminal insulating region 573-2 floats. Since this is a state, the potential cannot fall to the GND potential. The electric potential is 50 V at the depth indicated by the circle M. At this time, since the potential of the dummy trench gate electrode 524 is the GND potential, in the circle M (see also FIG. 8), the thin end that insulates the corner portion of the dummy trench gate electrode 524 and the body region 541b. A reverse voltage of about 50 V is applied to the insulating region 573-1. This reverse voltage can destroy the thin termination insulating region 573-1.

On the other hand, in the case of the semiconductor device 100 of the embodiment, when the semiconductor device 100 is off, as shown in FIG. 4B, the innermost terminal insulating region 173-1 and the outer terminal insulating region 173-2 are separated. In the intermediate body region 141b, the depletion layer can sufficiently spread. Therefore, the depletion layer can be sufficiently expanded even in the drift region 112 immediately below the body region 141b (note the circle N).
Further, as shown in FIG. 5B, the potential distribution along the line C-C shows that the innermost terminal insulating region 173-1 and the outer terminal insulating region 173- 3 when the semiconductor device 100 is off. In the body region 141b between 2, the potential can drop to a value close to the GND potential. As a result, the potential at the depth of the circle M (see also FIG. 8) drops to about 30V. In this case, the reverse voltage applied to the thin termination insulating region 173-1 that insulates the corner portion of the dummy trench gate electrode 124 from the body region 141b is reduced to about 30 volts. For this reason, the possibility that the terminal insulating region 173-1 is destroyed by the reverse voltage is low.

Although the semiconductor device embodying the present invention has been described above, the semiconductor device of the present invention is not limited to the specific configuration described above. In particular, the effects of the present invention can be exhibited even if the number, the forming position, the length G, and the like of the cutting portions 199 are not limited as in the embodiment. For example, as shown in FIG. 6, the cutting part 199 may be formed at a position along a side extending perpendicular to the main trench.
For each semiconductor region, the P-type and N-type may be interchanged. In addition, the insulating region is not limited to the oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.). The semiconductor device of the embodiment can also be applied to a conductivity modulation type power IGBT.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

It is a top view which shows the semiconductor device of the Example of this invention. It is sectional drawing of the II-II line of FIG. It is sectional drawing of the III-III line | wire of FIG. It is a figure which shows the depletion layer of a semiconductor device, (a) is a figure which shows the conventional semiconductor device, (b) is a figure which shows the semiconductor device of an Example. It is a graph which shows the electric potential distribution of the thickness direction of a semiconductor device, (a) is a figure which shows the conventional semiconductor device, (b) is a figure which shows the semiconductor device of an Example. It is a top view which shows the semiconductor device of the modification of this invention. It is a top view of the conventional semiconductor device. It is sectional drawing of the VIII-VIII line of FIG.

Explanation of symbols

100: Semiconductor device 101: Surface 102: Semiconductor substrate 104: Perimeter 105: Cell area 107: Termination area 111: Drain region 112: Drift region 122: Trench gate electrode 124: Dummy trench gate electrode 131: Source region 132: Body contact region 133: Source electrode 141: Body region D: Drain wiring S: Source wiring G: Gate wiring 113: Main trench 123: Main insulation region 151: Floating region 152: Impurity implantation region 153: Floating region 163: Termination trench 173: Termination insulation Area 199: cutting part

Claims (4)

A semiconductor substrate in which a body region of the first conductivity type is stacked on the surface of the drift region of the second conductivity type;
At least double termination trenches extending around a cell area in which a semiconductor structure functioning as a semiconductor device is built, and reaching the drift region from the surface of the semiconductor substrate through the body region;
Comprising a termination insulating region filling each termination trench;
At least the innermost terminal insulating region is cut at at least one point in a loop that goes around the outside of the cell area,
Conduction are ensured in the body region between the positions inside and outside the innermost end insulating region of the,
In the semiconductor substrate inside the innermost termination insulating region,
A main trench that reaches the drift region through the body region from the surface of the semiconductor substrate;
A main insulating region covering at least the wall surface of the main trench;
A gate electrode which is housed in the main trench in a state insulated from the semiconductor substrate by the main insulating region, and penetrates the body region from the surface of the semiconductor substrate to the drift region;
A source region of a second conductivity type formed at a position adjacent to the main trench on the surface of the semiconductor substrate;
A body contact region formed on the surface of the body region and containing a first conductivity type impurity at a high concentration;
A semiconductor structure is formed that includes a source electrode that is electrically connected to the source region and the body contact region.
The semiconductor device according to claim 1, wherein the innermost terminal insulating region is cut at a position extending in parallel with a main trench formed inside the terminal insulating region . The innermost end insulating region of the conductor of the same material as the gate electrode, the semiconductor device according to claim 1, characterized in that embedded to the same depth as the gate electrode. 3. The semiconductor device according to claim 1, wherein the innermost terminal insulating region is cut leaving a body region having a width of 1.1 [mu] m or less. The wall facing across the cut portion of the terminal trench constituting the innermost end insulating region of the, or of a semiconductor device according to claim 1 to 3 in which the impurity of the first conductivity type is characterized in that it is injected .

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