JP4818342B2 - Frequency error estimation device - Google Patents

Description

  The present invention relates to a frequency error estimation apparatus for accurately estimating a frequency error value used for frequency error compensation in a digital communication system such as radio communication in order to prevent deterioration of received signal characteristics due to a frequency error included in the received signal. It is.

  FIG. 4 shows a configuration of a conventional frequency error estimation apparatus that estimates a frequency error included in a received signal (see Non-Patent Document 1). According to FIG. 4, the frequency error estimation apparatus includes an N symbol delay circuit 31, a phase rotation amount detection circuit 32, and a smoothing filter 33.

  Next, a signal flow in the frequency error estimation apparatus will be described. The frequency error estimation apparatus receives an unmodulated signal obtained by removing a modulation component such as QPSK from the received signal. The phase rotation amount detection circuit 32 outputs a phase rotation amount per N symbols based on the input signal of the frequency error estimation device and a signal obtained by delaying the input signal by N symbols by the N symbol delay circuit 31. The smoothing filter 33 outputs a phase rotation amount per symbol, that is, a frequency error estimated value, based on the phase rotation amount per N symbols that is the output of the phase rotation amount detection circuit 32.

  FIG. 5 is a vector representation of the amount of phase rotation per N symbols in the frequency error estimation circuit of FIG. When the normalized frequency error Δf at the symbol rate exists in the received signal, the amount of phase rotation in the N symbol period is 2πNΔf. Thus, since the phase rotation amount is proportional to N and the frequency error, the phase rotation amount detection circuit 32 detects the phase rotation amount, and the smoothing filter 33 smoothes the noise to obtain a frequency error output. Considering the influence of noise, the frequency error output can be expressed as 2π (NΔf) + e (where e is a noise component). If N is set to be large, only the component proportional to the frequency error increases, so that there is an advantage that the influence of noise is relatively reduced and the frequency error estimation accuracy is improved. However, there is a problem that the range of frequency error that can be estimated when N is set large is narrowed.

  FIG. 6 shows a case where N is set large in the frequency error estimation circuit of FIG. 4, the range of frequency errors that can be estimated is narrowed, and the frequency error cannot be detected normally. When 2πNΔf> π, the actually detected amount of phase rotation is erroneously detected as −2π (1-NΔf) with the phase rotated in the minus direction. Similarly, the phase rotation amount cannot be accurately detected when 2πNΔf <−π. Therefore, the detectable phase rotation amount is −π ≦ 2πNΔf ≦ π, and the range of the frequency error Δf that can be estimated is −1 / (2N) ≦ Δf ≦ 1 / (2N). That is, the detection range becomes narrower in inverse proportion to N.

  FIG. 7 shows a frequency error estimation device that combines two frequency error estimation circuits having different values of N in FIG. 4 to realize highly accurate frequency error estimation without narrowing the frequency error estimation range (Patent Document 1). ). The frequency error estimation device includes a first frequency error estimation circuit in which N = m (m is a natural number), a second frequency error estimation circuit in which N = n (n is a natural number) and m <n, and A frequency error estimated value correcting circuit is provided that outputs a highly accurate frequency error estimated value based on the output of the first frequency error estimating circuit and the output of the second frequency error estimating circuit.

  The first frequency error estimation circuit includes an m symbol delay circuit 41, a phase rotation amount detection circuit 42, and a smoothing filter 43. The second frequency error estimation circuit includes an n symbol delay circuit 44, a phase rotation amount detection circuit 45, and a smoothing filter 46. The frequency error estimated value correction circuit includes multiplier circuits 47, 49, and 51, adder circuits 48 and 52, and a rounding circuit 50.

  Next, a signal flow in the frequency error estimation apparatus will be described. An unmodulated signal obtained by removing the modulation component from the received signal is input to the frequency error estimating apparatus. The phase rotation amount detection circuit 42 outputs a phase rotation amount per m symbols based on an input signal of the frequency error estimation device and a signal obtained by delaying the input signal by m symbols by the m symbol delay circuit 41. The smoothing filter 43 limits the band of the output of the phase rotation amount detection circuit 42 and reduces the influence of noise. The phase rotation amount detection circuit 45 outputs a phase rotation amount per n symbols based on an input signal of the frequency error estimation device and a signal obtained by delaying the input signal by n symbols delay circuit 44 by n symbols. The smoothing filter 46 limits the band of the output of the phase rotation amount detection circuit 45 to reduce the influence of noise. The multiplication circuit 47 multiplies the output of the smoothing filter 43 by n / m and outputs a value corresponding to the phase rotation amount for n symbols. The adder circuit 48 takes the difference between the output of the multiplier circuit 47 and the output of the smoothing filter 46 and outputs a deficiency from the original m-symbol phase rotation amount in the output of the smoothing filter 46. The multiplier circuit 49, the rounding circuit 50, and the multiplier circuit 51 use the fact that the output of the adder circuit 48 is originally an integer multiple of 2π to remove the influence of noise and the like included in the output of the adder circuit 48. The adder circuit 52 adds the output of the multiplier circuit 51 to the output of the smoothing filter 46, and outputs the original phase rotation amount for n symbols. The multiplier circuit 53 multiplies the output of the adder circuit 52 by 1 / (2π × n), and outputs a phase rotation amount per symbol, that is, a frequency error estimated value.

  Since m <n, the second frequency error estimation circuit can estimate the frequency error with higher accuracy than the first frequency error estimation circuit, but the estimated frequency range is narrow. When the received signal contains a frequency error that is outside the estimable range of the second frequency error estimation circuit, the phase rotation amount y for n symbols detected by the second frequency error estimation circuit is the phase rotation that should be detected originally. It is different from the amount. This is because the original phase rotation amount is 2πk + y (k is an integer), but the second frequency error estimation circuit cannot detect the phase rotation amount 2πk.

  Considering the above, the phase rotation amount for one symbol is (y + 2πk) / n. Since k is unknown, the amount of phase rotation for one symbol cannot be determined, and the frequency error cannot be estimated. Therefore, the frequency error estimated value correcting circuit determines k based on the phase rotation amount x for m symbols detected by the first frequency error estimating circuit whose frequency error to be estimated is within the estimable range. A value obtained by multiplying x by n / m corresponds to a phase rotation amount for n symbols. Therefore, the following formula is established.

x × n / m = y + 2πk
Therefore, k = (x × n / my) / 2π, but (x × n / my) / 2π does not become an integer due to the influence of noise, so k is (x × n / my). ) / 2 is the integer value closest to 2π. Since the frequency error estimated value correction circuit corrects y based on k, a highly accurate frequency error estimated value is obtained (see Patent Document 1).

Japanese Patent Laid-Open No. 2004-200939 H. Furukawa, K. Matsuyama, T. Sato, T. Takenaka and Y. Takeda, “Aπ / 4-Shifted DQPSK Demodulator for a Personal Mobile Communications System”, IEEE PIMRC 92, pp.618-622

  In the frequency error estimation apparatus of FIG. 7, in order to estimate a frequency exceeding the frequency that can be estimated by the second frequency error estimation circuit, the second frequency error estimation circuit uses the estimated value of the first frequency error estimation circuit that has a wide estimable range. To compensate for the frequency error estimate of. However, since the output of the smoothing filter 43 is multiplied by n / m by the multiplication circuit 47, the influence of noise received by the output of the smoothing filter 43 is increased. For this reason, as the noise included in the received signal increases, an error occurs in the output of the rounding circuit 50, and the correction value for the output of the smoothing filter 46, which is the output of the multiplication circuit 51, deteriorates. As a result, there is a problem that the estimated frequency error value of the apparatus deteriorates.

  Therefore, an object of the present invention is to provide a frequency error device that can estimate a frequency error with high accuracy regardless of the influence of noise.

In order to achieve the above object, a frequency error estimation device according to the present invention has a frequency error detection circuit with a variable frequency error detection range and a detection value of the frequency error detection circuit as inputs, and performs a smoothing process. A first smoothing filter circuit that outputs an error estimation value; and an adjustment circuit that adjusts a frequency error detection range of the frequency error detection circuit and a filter bandwidth of the first smoothing filter circuit; The adjustment circuit sets an effective region included in the frequency error detection range, determines whether the frequency error detection value is within the effective region, and the frequency error detection value exceeds the effective region. when in the center frequency of the effective area is reset to the frequency error detection value, wherein a frequency error detection value is the effective area, and the time re-setting is given the effective area If the not occur, along with narrowing the filter bandwidth prior Symbol first smoothing filter circuit, re-setting the center frequency of the effective region in the frequency error detection value, the filter band of the first smoothing filter circuit When the width reaches a preset lower limit value, the width of the frequency error detection range and the effective area are narrowed, the filter bandwidth of the first smoothing filter circuit is initialized, and the frequency error detection is performed again. It is determined whether or not the value is within the effective area, and the subsequent processing is repeated .

The adjustment circuit narrows the width of the frequency error detection range and the filter bandwidth of the first smoothing filter circuit when the width of the frequency error detection range reaches a preset lower limit value. It is also preferable to stop the operation.

Further, the frequency error detection circuit estimates a frequency error from a phase rotation amount in a specific estimation section of the received signal, and changes a length of the estimation section, thereby making the width of the frequency error detection range variable. It is also preferable.

  The circuit further includes a circuit that demodulates the received signal and a second smoothing filter circuit that smoothes the non-modulated signal, and the frequency error detection circuit outputs an output of the second smoothing filter circuit. It is also preferable to detect the frequency error based on the above.

  The frequency error estimation apparatus of the present invention sequentially switches the frequency error estimation range according to the convergence state of the frequency error estimation value, thereby realizing high-precision and high-speed frequency error estimation. Since it is not necessary to correct the estimated value with low accuracy, the frequency error can be estimated with high accuracy without increasing noise. Further, when the frequency error estimated value converges to some extent, the passband width of the smoothing filter circuit is also narrowed in steps, thereby reducing the fluctuation of the frequency error estimated value and further reducing the influence of noise. Furthermore, since the convergence state can be estimated with a simple circuit that does not require a multiplication circuit or the like, the circuit scale can be simplified as compared with the prior art.

  The best mode for carrying out the present invention will be described in detail below with reference to the drawings.

  Next, FIG. 1 shows a configuration diagram of the frequency error estimation apparatus according to the embodiment of the present invention. According to FIG. 1, the frequency error estimation device includes a multiplier circuit 1, a variable oscillation circuit 2, a non-modulation circuit 3, a smoothing filter circuit 4, an m symbol delay circuit 5, a phase rotation amount detection circuit 6, and a bandwidth variable smoothing. A filter circuit 7 and an adjustment circuit 10 are provided. The bandwidth variable smoothing filter circuit 7 includes a variable loop gain 8 and an integration circuit 9. Note that the value of m in the m symbol delay circuit 5 (m is a natural number) and the value of the variable loop gain 8 in the variable bandwidth smoothing filter circuit 7 can be changed by the output of the adjustment circuit 10.

  Next, a signal flow in the frequency error estimation apparatus will be described. The frequency error estimation apparatus receives a baseband received signal. The variable oscillation circuit 2 outputs a frequency error compensation signal based on the estimated frequency error value output from the integration circuit 9. The multiplier circuit 1 compensates for a frequency error contained in the baseband received signal.

  However, if the estimated frequency error value does not match the frequency error value of the received signal, the output of the multiplier circuit 1 includes a residual frequency error. Therefore, the apparatus detects the residual frequency error and updates the frequency error estimated value so that the residual frequency error becomes zero.

  The non-modulation circuit 3 detects a known pattern included in the output of the multiplication circuit 1, and inversely modulates the known pattern included in the output of the reception circuit 1 and the known pattern generated in the non-modulation circuit. , The modulation component such as QPSK is removed from the output of the receiving circuit 1 to make no modulation. The smoothing filter circuit 4 outputs a value obtained by smoothing the output of the non-modulation circuit 3 based on the output of the adjustment circuit 10. The phase rotation amount detection circuit 6 calculates the amount of phase rotation caused by the residual frequency error between m symbols based on the output of the smoothing filter circuit 4 and a signal obtained by delaying the output by m symbol delay circuit 5 by m symbols. To do. The integrating circuit 9 updates the frequency error estimated value by successively integrating the output of the phase rotation amount detecting circuit 6 based on the value adjusted by the variable loop gain 8. The adjustment circuit 10 adjusts the value of m of the m symbol delay circuit 5 and adjusts the value of the variable loop gain 8 based on the flowchart shown in FIG.

  The adjustment circuit 10 can change the frequency error estimation range and the frequency error estimation accuracy by sequentially increasing the value of m of the phase rotation amount detection circuit 11 for m symbols based on the output of the variable bandwidth smoothing filter circuit 7. . Note that the value of m is minimized at the start of circuit operation, and the region [−B, B] included in the frequency error estimable range at that time is set as an effective region. That is, B is a value smaller than 1 / (2 m).

  When the frequency error estimated value is outside the effective region, the center frequency that is the center of the effective region is set as the frequency error estimated value. Therefore, the effective area is [frequency error estimated value−B, frequency error estimated value + B].

  When the frequency error estimated value is within the effective region and the center frequency of the effective region is not changed during the preset time T, the variable loop gain 8 is decreased and the effective region is set to [frequency error estimated value. -B, frequency error estimate + B]. Decreasing the variable loop gain 8 is equivalent to reducing the pass bandwidth of the variable bandwidth smoothing filter circuit 7 because the loop bandwidth of the closed loop is narrowed. Further, when the value of the variable loop gain 8 is a preset lower limit value, m is increased, B is decreased, and the value of the variable loop gain 8 is initialized.

  By increasing m, the frequency error estimation range is narrowed, and as a result, the frequency error estimation accuracy is increased. When the above operation is repeated and m reaches a preset upper limit value, the adjustment circuit 10 stops updating the value of m and the value of the variable loop gain 8.

  The circuit in FIG. 1 determines the convergence state of the frequency error estimated value based on the change frequency of the effective region. In other words, since the change in the frequency error estimated value becomes smaller as the convergence is approached, the time for staying in the effective region in which the frequency error estimated value is set becomes longer. The flow chart of FIG. 2 determines the convergence state by measuring the time remaining in the effective region, and when the frequency error estimated value has converged to some extent, the value of the variable loop gain 8 is lowered stepwise to estimate the frequency error estimated value. To reduce the influence of noise. The estimated frequency error value thus obtained approaches the true value of the frequency error of the input signal because the influence of noise is considerably reduced. Therefore, even if the value of m is switched, the circuit of FIG. 1 can prevent the estimation target frequency error from being outside the estimable range, and does not require a plurality of multiplication circuits as shown in FIG. Compared to technology, the circuit scale can be simplified.

  The phase rotation amount detection circuit 11 for m symbols in FIG. 1 may use the phase rotation amount detection circuit 12 for a symbols, the phase rotation amount detection circuit 15 for b symbols, and the selector 18 shown in FIG. The phase rotation amount detection circuit 12 for a symbol is composed of an a symbol delay circuit 13 and a phase rotation amount detection circuit 14, and the phase rotation amount detection circuit 15 for b symbols is a b symbol delay circuit 16 and a phase rotation amount detection circuit. 17. The configuration of FIG. 3 corresponds to a case where the value of m of the m symbol delay circuit 5 in FIG. 1 is switched only once. The selector 18 selects and outputs either the phase rotation amount detection circuit 12 for a symbols or the phase rotation amount detection circuit 15 for b symbols based on the output of the adjustment circuit 10.

  The above algorithm enables high-speed initial pull-in and noise reduction in the convergence state.

  Moreover, all the embodiments described above are illustrative of the present invention and are not intended to limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

It is a block diagram of the frequency error estimation apparatus by this invention. It is a flowchart which shows the process in the adjustment circuit 10 shown in FIG. It is another form of the phase rotation amount detection circuit 11 for m symbols shown in FIG. It is a figure which shows the conventional frequency error estimation apparatus. It is a figure which shows the range of the phase rotation amount which can be detected in the frequency error estimation apparatus shown in FIG. FIG. 5 is a diagram showing a case where the frequency error estimation circuit shown in FIG. 4 erroneously detects a phase rotation amount. It is a figure which shows the conventional frequency error estimation apparatus which prevents the misdetection of FIG. 4 and estimates a frequency error with high precision.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multiplication circuit 2 Variable oscillation circuit 3 Unmodulation circuit 4 Smoothing filter circuit 5 m symbol delay circuit 6 Phase rotation amount detection circuit 7 Bandwidth variable smoothing filter circuit 8 Variable loop gain 9 Integration circuit 10 Adjustment circuit 11 m symbols worth Phase rotation amount detection circuit 12 a symbol phase rotation amount detection circuit 13 a symbol delay circuit 14 phase rotation amount detection circuit 15 b symbol phase rotation amount detection circuit 16 b symbol delay circuit 17 phase rotation amount detection circuit 18 selector 31 N symbol delay circuit 32, 42, 45 Phase rotation amount detection circuit 33, 43, 46 Smoothing filter 41 m symbol delay circuit 44 n symbol delay circuit 47, 49, 51, 53 Multiplication circuit 48, 52 Addition circuit 50 Rounding circuit

Claims (4)

A frequency error detection circuit having a variable frequency error detection range;
A first smoothing filter circuit which receives a detection value of the frequency error detection circuit as input, performs a smoothing process, and outputs it as a frequency error estimation value;
An adjustment circuit for adjusting a frequency error detection range of the frequency error detection circuit and a filter bandwidth of the first smoothing filter circuit;
With
The adjustment circuit includes:
Set an effective area included in the frequency error detection range,
Determining whether the frequency error detection value is within the effective region;
When the frequency error detection value exceeds the effective area, the center frequency of the effective area is reset to the frequency error detection value,
Wherein a frequency error detection value is the effective area, and if the re-setting of the effective area does not occur within a predetermined time, with narrow the filter bandwidth prior Symbol first smoothing filter circuit, the effective area Reset the center frequency of the above to the frequency error detection value,
When the filter bandwidth of the first smoothing filter circuit reaches a preset lower limit value, the width of the frequency error detection range and the effective region are narrowed, and the filter band of the first smoothing filter circuit Initialize the width,
The frequency error estimation apparatus again determines whether or not the frequency error detection value is within the effective region, and repeats the subsequent processing . The adjustment circuit includes:
When the width of the frequency error detection range reaches a preset lower limit value, the narrowing of the width of the frequency error detection range and the filter bandwidth of the first smoothing filter circuit is stopped. The frequency error estimation apparatus according to claim 1. The frequency error detection circuit is
Estimate the frequency error from the amount of phase rotation in a specific estimation section of the received signal,
The frequency error estimation apparatus according to claim 1 or 2, wherein a width of the frequency error detection range is made variable by changing a length of the estimation section.   A circuit for demodulating the received signal; and a second smoothing filter circuit for smoothing the unmodulated signal, wherein the frequency error detection circuit is based on the output of the second smoothing filter circuit. The frequency error estimation device according to any one of claims 1 to 3, wherein a frequency error is detected.

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