JP4815005B2 - Delay locked loop circuit - Google Patents

Description

  The present invention relates to a delay locked loop circuit.

  The delay locked loop circuit (DLL) is used to detect an optimum strobe point of a clock for a data signal during memory access or the like. For example, the delay locked loop circuit detects 1/2 phase of the reference clock signal at a single data rate (SDR), and detects 1/4 phase or 3/4 phase of the reference clock signal at a double data rate (DDR). . In general, in a memory or the like, a delay locked loop circuit is used for timing sequence control of a word line or a sense amplifier.

  FIG. 16 shows a configuration of a conventional delay locked loop circuit. The delay circuit 100 includes four delay elements 101 connected in series, receives the reference clock signal CLKr, and outputs a delayed clock signal CLKd delayed by one cycle. The phase comparator 102 compares the phases of the reference clock signal CLKr and the delayed clock signal CLKd, and outputs signals UP and DN according to the comparison result. A charge pump circuit (including a loop filter) 103 controls the delay circuit 100 based on the signals UP and DN. The delay locked loop circuit having the above configuration is stable when the phase of the delayed clock signal CLKd is delayed by one cycle from the phase of the reference clock signal CLKr, and at this time, the delay of the delayed clock signal CLKd is locked (for example, Patent Documents). 1).

  In the delay locked loop circuit configured as described above, a clock signal with a ¼ phase (90 °) delay is output from the first delay element 101 in the delay circuit 100. Further, a clock signal delayed by 3/4 phase (270 °) is output from the delay element 101 at the third stage.

Japanese Patent Application Laid-Open No. 2000-82954

  The conventional delay locked loop circuit has a problem that it is difficult to improve the accuracy of the ¼ phase and the ¾ phase because the drive capability and load capacity of the reference clock signal CLKr and the delay element 101 are different.

  Further, in the conventional delay locked loop circuit, the delayed clock signal is generated as a clock signal that is 1/4 phase or 3/4 phase delayed from the reference clock signal, regardless of the duty ratio of the reference clock signal. For this reason, for example, when the duty ratio of the reference clock signal is smaller than 25%, the rising or rising of the 1/4 phase delayed clock signal does not occur during the on-duty of the reference clock signal. become unable. As described above, the conventional delay locked loop circuit may not be able to cope with the reference clock signal whose duty ratio is not 50%.

  Further, in the conventional delay locked loop circuit, in principle, signals UP and DN having extremely short pulse widths are output even after the delay of the delayed clock signal CLKd is locked. Therefore, steady jitter exists in the conventional delay locked loop circuit. In order to suppress the steady jitter, it is conceivable to reduce the delay gain. However, if the delay gain is reduced, the response speed until the delay is locked, that is, the locking time is delayed. Further, it is conceivable to suppress steady jitter by increasing the capacity of the loop filter and increasing the filter time constant, but in this case, the circuit scale becomes large.

  In view of the above problems, an object of the present invention is to realize a delay-locked loop circuit that can generate a highly accurate delayed clock signal regardless of the duty ratio of the reference clock signal in principle without steady jitter.

  The means taken by the present invention to solve the above-described problem is a delay locked loop circuit that delays from a first change from a first logic level to a second logic level of a reference clock signal. A delay element for generating a delayed clock signal that changes from a logic level to a second logic level; a first change in the reference clock signal; and from the second logic level of the reference clock signal to the first logic level. A signal generation circuit for generating first and second signals that change complementarily in accordance with a second change of the delay clock signal and a change of the delayed clock signal, and the reference clock signal according to the first and second signals From the first change of the delay clock signal to the change of the delayed clock signal, the first operation which is one of the push operation and the pull operation is performed, and the reference clock is changed from the change of the delayed clock signal. A charge pump circuit that performs a second operation that is the other of a push operation and a pull operation until a second change of the signal, and a loop filter that integrates the output of the charge pump circuit and outputs an analog signal Shall be. Here, the delay element, based on the output of the loop filter, delay amount from the first change of the reference clock signal to the change of the delayed clock signal, that is, the delay of one edge of the delayed clock signal Control the amount.

  According to the present invention, the signal generation circuit generates the first change of the reference clock signal from the first logic level to the second logic level and vice versa, and the delay element controls the delay by the delay element. First and second signals that change complementarily in response to the change of the delayed clock signal from the first logic level to the second logic level are generated, and the charge pump circuit is generated according to the first and second signals. Performs a push-pull operation, its output is smoothed by a loop filter, and delay control of the delay clock signal is performed by a delay element based on the smoothed output. Here, the change of the delayed clock signal is generated with a delay by an amount controlled by the delay element from the first change of the reference clock signal. Therefore, in the delay locked loop circuit according to the present invention, the delay locking point is the only place delayed by a predetermined amount from the first change of the reference clock signal, and the reference clock signal is independent of the duty ratio of the reference clock signal. A delayed clock signal is generated that rises or falls during on-duty or off-duty of the clock signal. Further, in principle, the delay locked loop circuit according to the present invention does not output a pulse that causes jitter of the delayed clock signal in a steady state. Therefore, it is not necessary to increase the filter time constant for the purpose of suppressing jitter, and the loop filter can be downsized and the entire delay locked loop circuit can be downsized.

  Specifically, the delay element is connected in series, and has a gate connected to the first and second transistors of opposite polarities receiving the reference clock signal, and is connected between these transistors, and the gate is connected to the loop filter. A first circuit having a third transistor for receiving an output, wherein a voltage at a predetermined node between the first transistor and the second transistor is an output signal; and an output signal of the first circuit And a second circuit for shaping the waveform.

  According to the present invention, the voltage of the output signal of the first circuit changes according to the change of the reference clock signal, and the delay associated with this change changes according to the channel formed in the third transistor. Here, since the channel formation state changes according to the output of the loop filter, the delay amount of the output signal of the first circuit based on the output of the loop filter can be controlled. Although the waveform of the output signal of the first circuit becomes dull with the delay, the waveform is shaped by the second circuit and ringing is also suppressed. Thus, the signal output from the second circuit can be used as a delayed clock signal. Further, since the delay amount can be controlled by adjusting the gate voltage of the third transistor, an extremely wide lock-in range is achieved.

  As described above, according to the present invention, there is no steady jitter in principle, and a highly accurate delayed clock signal is generated regardless of the duty ratio of the reference clock signal. For this reason, it is not necessary to provide a loop filter having a large time constant, and the circuit scale of the delay locked loop circuit is reduced.

1 is a configuration diagram of a delay locked loop circuit according to a first embodiment of the present invention. It is a block diagram of a delay element. It is a timing chart of a delay element. 3 is a timing chart of the delay locked loop circuit according to the first embodiment of the present invention. It is a block diagram of the delay locked loop circuit which concerns on a 1st reference example. 5 is a timing chart of the delay locked loop circuit according to the first reference example. It is a block diagram of the delay locked loop circuit which concerns on a 2nd reference example. 6 is a timing chart of a delay locked loop circuit according to a second reference example. It is a block diagram of the delay locked loop circuit which concerns on a 3rd reference example. 12 is a timing chart of a delay locked loop circuit according to a third reference example. 10 is a modification of the charge pump circuit and the loop filter shown in FIG. 9. It is a block diagram of the delay locked loop circuit based on a 4th reference example. 14 is a timing chart of a delay locked loop circuit according to a fourth reference example. It is a block diagram of the delay element at the time of comprising as a differential circuit. FIG. 10 is a configuration diagram of a delay locked loop circuit according to a fifth reference example. It is a block diagram of the conventional delay clock loop circuit.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a delay locked loop circuit according to a first embodiment of the present invention. The delay locked loop circuit according to the present embodiment includes a delay element 10, a signal generation circuit 20, a charge pump circuit 30, and a loop filter 40. Delay element 10 receives reference clock signal CLKr and outputs delayed clock signal CLKd. The delay amount of the delayed clock signal CLKd is controlled by the control voltage Vc output from the loop filter 40. The signal generation circuit 20 outputs a logical product of the reference clock signal CLKr and the inverted version of the delayed clock signal CLKd as a signal UP, and outputs a logical product of the reference clock signal CLKr and the delayed clock signal CLKd as a signal DN. The charge pump circuit 30 includes a current source 301, a switch 302 that controls energization / interruption of the current I1 supplied by the current source 301 according to the signal UP, a current source 303, and energization / interruption of the current I2 supplied by the current source 303. The switch 304 is controlled according to the signal DN. When the signal UP is at the Hi level, the current I1 is output to the outside (push operation), and when the signal DN is at the Hi level, the current I2 is drawn from the outside (pull operation). The loop filter 40 includes a capacitor 401, receives the output of the charge pump circuit 30, integrates it, and generates a control voltage Vc.

  FIG. 2 shows the configuration of the delay element 10. In the delay element 10, the inverting circuit 11 receives the input signal IN of the delay element 10, logically inverts this, and outputs a signal INV. Specifically, the inverting circuit 11 includes a PMOS transistor 111 and an NMOS transistor 112 connected in series, an NMOS transistor 113 connected between these two transistors, and an NMOS transistor 114 connected in parallel to the transistor 113. I have. A signal IN is supplied to the gates of the transistors 111 and 112, and a signal INV is output from a connection point between the transistors 111 and 113. Further, the control voltage Vc output from the loop filter 40 is applied to the gate of the transistor 113, and a predetermined voltage is applied to the gate of the transistor 114. On the other hand, the waveform shaping circuit 12 shapes the waveform of the signal INV and generates the output signal OUT of the delay element 10. Specifically, the waveform shaping circuit 12 receives the signal INV, outputs the signal OUT, the inverter 121, the drain and the gate are connected to the input terminal and the output terminal of the inverter 121, respectively, and the source has a predetermined voltage, for example, An NMOS transistor 122 to which a ground voltage is applied is provided.

  In the inverting circuit 11, when the signal IN is at the Lo level, the transistors 111 and 112 serving as switches are in a conductive state and a non-conductive state, respectively, and the output destination of the inverting circuit 11 is supplied with electric charges from the power supply node. Become a level. On the other hand, when the signal IN is at the Hi level, the transistors 111 and 112 are in a non-conducting state and a conducting state, respectively, the charge supplied to the output destination is extracted to the ground node, and the signal INV is at the Lo level.

  FIG. 3 shows a timing chart of the delay element 10. When the signal IN falls, the signal INV immediately changes from the Lo level to the Hi level. On the other hand, even if the signal IN rises, the signal INV does not immediately change from the Hi level to the Lo level but changes relatively smoothly. This is because the transistors 113 and 114 limit the extraction of charge to the ground node. The signal INV having a blunt waveform is shaped by the waveform shaping circuit 12 and output as a signal OUT having steep rising and falling edges. In addition, the waveform shaping circuit 12 has an effect of suppressing ringing generated in the signal INV.

  As described above, as a result of limiting the charge extraction to the ground node by the transistors 113 and 114, the rising of the signal OUT occurs with some delay after the signal IN rises. Here, by appropriately adjusting the control voltage Vc, the state of the channel formed in the transistor 113 is changed, and the rate of change of the signal INV from the Hi level to the Lo level is changed. As a result, the delay of the signal OUT is changed. The amount is adjusted. Note that the transistor 114 operates as a current source that draws a certain amount of current. That is, there is a minimum value restriction regarding the charge extraction to the ground node. Without this restriction, when the current flowing through the transistor 113 is relatively small, the delay amount of the delayed clock signal CLKd may change significantly and the oscillation may occur because the control voltage Vc changes only slightly. Because there is.

  FIG. 4 is a timing chart of the delay locked loop circuit according to the present embodiment. The reference clock signal CLKr and the delayed clock signal CLKd correspond to the signals IN and OUT shown in FIG. 3, respectively. The signal UP becomes Hi level during the period from the rise of the reference clock signal CLKr to the rise of the delayed clock signal CLKd. The signal DN is at the Hi level during the period from the rising edge of the delayed clock signal CLKd to the falling edge of the reference clock signal CLKr. That is, the signals UP and DN are at the Hi level during the first half and the second half of the on-duty of the reference clock signal CLKr with the rising edge of the delayed clock signal CLKd as a boundary. In the timing chart shown in FIG. 4, the current flowing from the charge pump circuit 30 toward the outside (push current) and the current flowing from the outside toward the charge pump circuit 30 (pull current) are superimposed on the signals UP and DN. Is displayed with parallel diagonal lines along with its size.

  When the reference clock signal CLKr rises, the signal UP becomes Hi level, the current I1 is supplied from the charge pump circuit 30 to the loop filter 40, and the control voltage Vc gradually increases. When the control voltage Vc is relatively low, the delay amount of the delayed clock signal CLKd is relatively large. Conversely, when the control voltage Vc is relatively high, the delay amount of the delayed clock signal CLKd is relatively small. Therefore, the increase in the control voltage Vc works in the direction of decreasing the delay amount of the delayed clock signal CLKd, and the delayed clock signal CLKd rises when a certain amount of time has elapsed after the reference clock signal CLKr rises. As a result, the signal DN becomes Hi level, the current I2 is drawn from the loop filter 40 to the charge pump circuit 30, and the control voltage Vc gradually decreases to return to the original level.

  In the delay locked loop circuit according to the present embodiment, the rising edge of the delayed clock signal CLKd occurs when the on-duty of the reference clock signal CLKr is internally divided by a certain ratio. This ratio depends on the relationship between the currents I1 and I2. Determined. That is, in the delay locked loop circuit according to the present embodiment, the feedback system acts so that the charge amount related to the push operation and the pull operation by the charge pump circuit 30 is balanced, and the ratio of the Hi period between the signal UP and the signal DN is The system becomes stable when the reciprocal ratio between the currents I1 and I2 is reached. Therefore, by appropriately setting the magnitudes of the currents I1 and I2, it is possible to adjust the delay clock signal CLKd to rise when the on-duty of the reference clock signal CLKr is internally divided by a desired ratio.

  In particular, when the currents I1 and I2 are set to be equal, the rising edge of the delayed clock signal CLKd occurs at a point that is exactly half the on-duty of the reference clock signal CLKr. In other words, regardless of whether the duty ratio of the reference clock signal CLKr is 50%, it is possible to obtain the delayed clock signal CLKd that rises at a time point that is half the on-duty of the reference clock signal CLKr.

  In addition, in the conventional delay locked loop circuit, it is ideal that the signals UP and DN are not output in a steady state, but in principle, a very short pulse is actually output, which causes a steady jitter. On the other hand, in the delay locked loop circuit according to the present embodiment, in the steady state, the signals UP and DN are always output so that the charge amounts related to the push operation and the pull operation by the charge pump circuit 30 are balanced. As a result, the control voltage Vc repeats gradually increasing and decreasing as shown in FIG. 4, but the delay amount of the delay element 10 is determined by the voltage locus of the gradually increasing portion. Therefore, in the delay locked loop circuit according to the present embodiment, the cause of steady jitter does not occur in principle, and an output with excellent jitter characteristics, that is, a delayed clock signal can be obtained.

  As described above, according to the present embodiment, there is no steady jitter in principle, and a highly accurate delayed clock signal can be generated regardless of the duty ratio of the reference clock signal.

  Note that the delay locked loop circuit may be configured to operate with a logic opposite to that described above.

(First reference example)
FIG. 5 shows a configuration of the delay locked loop circuit according to the first reference example. The delay locked loop circuit according to this reference example includes a signal generation circuit 20 having a configuration different from that of the first embodiment. The signal generation circuit 20 according to this reference example outputs the logical product of the reference clock signal CLKr and the inverted version of the delayed clock signal CLKd as the signal UP and the reference clock signal CLKr as the signal DN. Hereinafter, only the difference between the delay locked loop circuit according to the first embodiment and the delay locked loop circuit according to the first embodiment will be described.

  FIG. 6 is a timing chart of the delay locked loop circuit according to this reference example. The signal UP becomes Hi level during the period from the rise of the reference clock signal CLKr to the rise of the delayed clock signal CLKd. The signal DN is the same as the reference clock signal CLKr. In the timing chart shown in FIG. 6, the current flowing from the charge pump circuit 30 to the outside (push current) and the current flowing from the outside to the charge pump circuit 30 (pull current) are superimposed on the signals UP and DN. Is displayed with parallel diagonal lines along with its size.

  When the reference clock signal CLKr rises, the signals UP and DN become Hi level, the switches 302 and 304 in the charge pump circuit 30 are closed, and the difference current between the current I1 and the current I2 is supplied from the charge pump circuit 30 to the loop filter 40. The control voltage Vc increases gradually. The delayed clock signal CLKd rises when a certain amount of time has elapsed since the reference clock signal CLKr rises. As a result, only the signal UP becomes the Lo level, only the switch 302 is opened, the current I2 is drawn from the loop filter 40 to the charge pump circuit 30, and the control voltage Vc gradually decreases and returns to the original level. Therefore, by appropriately setting the magnitudes of the currents I1 and I2, it is possible to adjust the delay clock signal CLKd to rise when the on-duty of the reference clock signal CLKr is internally divided by a desired ratio.

  In particular, when the current I1 is set to a magnitude corresponding to twice the current I2, the magnitude of the current supplied when both the switches 302 and 304 in the charge pump circuit 30 are closed, and only the switch 304 is The magnitude of the current drawn when it is closed becomes equal, and the rising of the delayed clock signal CLKd occurs at a point just half the on-duty of the reference clock signal CLKr.

  As described above, according to the present reference example, the configuration of the signal generation circuit 20 is facilitated as compared with the first embodiment, and the circuit scale of the entire delay locked loop circuit is reduced.

(Second reference example)
FIG. 7 shows a configuration of a delay locked loop circuit according to a second reference example. The delay locked loop circuit according to this reference example includes a charge pump circuit 30 having a configuration different from that of the first reference example. The charge pump circuit 30 according to the present reference example further includes a current source 305 and a switch 306 that controls energization / cutoff of the current I3 supplied from the current source 305 according to the signal UP to the charge pump circuit 30 according to the first reference example. , A current source 307, and a switch 308 that controls energization / cutoff of the current I4 supplied by the current source 307 in accordance with the signal DN. Only differences from the first reference example will be described below.

  FIG. 8 is a timing chart of the delay locked loop circuit according to this reference example. In the timing chart shown in FIG. 8, the current (push current) flowing from the charge pump circuit 30 to the outside and the current flowing from the outside to the charge pump circuit 30 (pull current) are superimposed on the signals UP and DN. Is displayed with parallel diagonal lines along with its size.

  When the reference clock signal CLKr rises, the signals UP and DN become Hi level, the switches 302 and 304 in the charge pump circuit 30 are closed, and the difference current between the current I1 and the current I2 is supplied from the charge pump circuit 30 to the loop filter 40. The control voltage Vc increases gradually. The delayed clock signal CLKd rises when a certain amount of time has elapsed since the reference clock signal CLKr rises. As a result, only the signal UP becomes the Lo level, the switch 302 is opened, instead the switch 306 is closed, the total current of the currents I2 and I3 is drawn from the loop filter 40 to the charge pump circuit 30, and the control voltage Vc is Decrease and return to the original level. When the reference clock signal CLKr falls, the signal DN becomes Lo level, the switch 304 is opened, instead the switch 308 is closed, and the difference current between the current I3 and the current I4 is supplied to the loop filter 40. Here, when the current I3 and the current I4 are equal, the push current and the pull current cancel each other, and the push-pull operation of the charge pump circuit 30 apparently stops while the reference clock signal CLKr is at the Lo level.

  Also in the delay locked loop circuit according to this reference example, by appropriately setting the magnitudes of the currents I1 to I4, the delay clock signal CLKd rises when the on-duty of the reference clock signal CLKr is internally divided at a desired ratio. Can be adjusted. In particular, when the magnitudes of the currents I2 to I4 are all equal and the current I1 is set to be a magnitude corresponding to three times the magnitude of the currents I2 to I4, the switches 302 and 304 in the charge pump circuit 30 are The magnitude of the current supplied to the loop filter 40 when it is closed is equal to the magnitude of the current drawn from the loop filter 40 when the switches 304 and 306 are closed, and the rising edge of the delayed clock signal CLKd indicates the reference clock signal. Occurs at exactly half the on-duty ratio of CLKr.

  As described above, according to the present reference example, the configuration of the signal generation circuit 20 is facilitated as compared with the first embodiment, and the circuit scale of the entire delay locked loop circuit is reduced.

(Third reference example)
FIG. 9 shows a configuration of a delay locked loop circuit according to a third reference example. The delay locked loop circuit according to this reference example includes a charge pump circuit 30 having a configuration different from those of the first and second reference examples. The charge pump circuit 30 according to this reference example further includes a current source 309 that supplies a current I5 having the same polarity as the current source 301 to the charge pump circuit 30 according to the second reference example. That is, in the charge pump circuit 30 according to this reference example, the current I5 is constantly supplied from the current source 309 regardless of the states of the signals UP and DN. Only differences from the second reference example will be described below.

  FIG. 10 is a timing chart of the delay locked loop circuit according to this reference example. In the timing chart shown in FIG. 10, a current (push current) that flows from the charge pump circuit 30 to the outside and a current (pull current) that flows from the outside to the charge pump circuit 30 are superimposed on the signals UP and DN. Is displayed with parallel diagonal lines along with its size.

  When the reference clock signal CLKr rises, the signals UP and DN become Hi level, the switches 302 and 304 in the charge pump circuit 30 are closed, and the total current of the current I1 and the current I5 and the current I2 are passed from the charge pump circuit 30 to the loop filter 40. And the control voltage Vc gradually increases. The delayed clock signal CLKd rises when a certain amount of time has elapsed since the reference clock signal CLKr rises. As a result, only the signal UP becomes the Lo level, the switch 302 is opened, and the switch 306 is closed instead. The difference current between the current I2 and the current I3 and the current I5 is obtained from the loop filter 40 to the charge pump circuit 30. The control voltage Vc gradually decreases and returns to the original level. When the reference clock signal CLKr falls, the signal DN becomes Lo level, the switch 304 is opened, and the switch 308 is closed instead, and the loop filter 40 receives the sum of the current I4 and the current I5 and the current I3. A differential current is supplied. Here, when the total current of the current I4 and the current I5 is equal to the current I3, the push current and the pull current are canceled out, and the push-pull operation of the charge pump circuit 30 is performed while the reference clock signal CLKr is at the Lo level. Apparently stops.

  Also in the delay locked loop circuit according to this reference example, by appropriately setting the magnitudes of the currents I1 to I5, the delay clock signal CLKd rises when the on-duty of the reference clock signal CLKr is internally divided at a desired ratio. Can be adjusted. In particular, the currents I1 and I3 are equal in magnitude, the currents I2, I4 and I5 are equal in magnitude, and the currents I1 and I3 are equal to twice the magnitude of the currents I2, I4 and I5. When the switches 302 and 304 in the charge pump circuit 30 are closed, the magnitude of the current supplied to the loop filter 40 and the current drawn from the loop filter 40 when the switches 304 and 306 are closed are set. The rising edges of the delayed clock signal CLKd occur at exactly half the on-duty of the reference clock signal CLKr.

  As described above, according to the present reference example, the configuration of the signal generation circuit 20 is facilitated as compared with the first embodiment, and the circuit scale of the entire delay locked loop circuit is reduced.

  By the way, in the charge pump circuit 30 according to the present reference example, the current of the same magnitude continuously flows while changing its direction according to the signals UP and DN, so that the switching control of current supply / cutoff is no longer necessary. A circuit configuration as shown in FIG. 11 is possible. That is, the charge pump circuit 30 includes a resistor 311 (resistance value R1) that receives an inversion of the signal UP (hereinafter referred to as “signal / UP”), a resistor 312 that receives the signal DN (resistance value R2), and one end that is a resistor. The resistor 313 (resistance value R3) is connected to the connection point of 311 and 312 and the ground voltage Vss is applied to the other end. The loop filter 40 includes a capacitor 401 and a capacitor 401 in the negative feedback portion. Is connected, the inverting input terminal is connected to the connection point of the resistors 311 to 313 in the charge pump circuit 30, and the operational amplifier 402 is provided with the voltage Va at the non-inverting input terminal.

In FIG. 11, when the Hi level voltage of the signals / UP and DN is the power supply voltage Vdd and the Lo level voltage is the ground voltage Vss (= 0), when the reference clock signal CLKr rises, the signals / UP and DN are respectively grounded. The voltage Vss and the power supply voltage Vdd are obtained. Where:
R2 = R3 = 2R1 = R and Va = (Vdd−Vss) / 2 = Vdd / 2
When the resistance values of the resistors 311 to 313 and the voltage Va are set so as to satisfy the above, when the signals / UP and DN become the ground voltage Vss and the power supply voltage Vdd, respectively, the input terminal of the signal / UP from the resistor 311 In addition, a current having a magnitude of Vdd / R starts to flow, and a current having a magnitude of Vdd / 2 / R flows from the input end of the signal DN to the resistor 312. In addition, a current having a magnitude of Vdd / 2 / R flows from the connection point of the resistors 311 to 313 to the ground node. Therefore, according to Kirchhoff's law, current Vdd / R flows from the output side of the operational amplifier 402 to the connection point of the resistors 311 to 313 via the capacitor 401. As a result, the control voltage Vc gradually increases.

  Then, when a certain amount of time has elapsed since the rising of the reference clock signal CLKr, the delayed clock signal CLKd rises, the signal / UP becomes the power supply voltage Vdd, and the magnitude of the signal / UP from the input terminal to the resistor 311 becomes Vdd. / R current flows in. Therefore, according to Kirchhoff's law, a current Vdd / R flows from the connection point of the resistors 311 to 313 to the output side of the operational amplifier 402 via the capacitor 401. As a result, the control voltage Vc gradually decreases and returns to the original level.

  Thereafter, when the reference clock signal CLKr falls, the signal DN becomes the ground voltage Vss (= 0), and a current having a magnitude of Vdd / 2 / R flows from the resistor 312 to the input terminal of the signal DN. Therefore, the current flowing into the resistor 311 from the input end of the signal / UP flows out through the resistors 312 and 313 and does not flow into the loop filter 40. That is, the push-pull operation of the charge pump circuit 30 apparently stops while the reference clock signal CLKr is at the Lo level.

  As described above, the delay locked loop circuit including the charge pump circuit 30 and the loop filter 40 illustrated in FIG. 11 operates in the same manner as the delay locked loop circuit according to the present reference example illustrated in FIG. In addition, since the switch shown in FIG. 11 does not use a switch, current accuracy is not deteriorated due to switching noise, and operation at a lower voltage than the delay locked loop circuit shown in FIG. 9 is possible. .

(Fourth reference example)
FIG. 12 shows a configuration of a delay locked loop circuit according to a fourth reference example. The delay locked loop circuit according to the present reference example is configured by combining any two of the first embodiment and the delay locked loop circuit according to each reference example, and the first delay locked loop circuit is , The delay element 10r, the signal generation circuit 20r, the charge pump circuit 30r, and the loop filter 40r. The second delay locked loop circuit includes the delay element 10f, the signal generation circuit 20f, the charge pump circuit 30f, and the loop filter 40f. I have. The first and second delay locked loop circuits output delayed clock signals CLKdr and CLKdf whose logic levels change with delay from the rising and falling edges of the reference clock signal CLKr, respectively. The specific configurations of the first and second delay locked loop circuits are as described in the first embodiment and the respective reference examples. The delay locked loop circuit according to this reference example includes a clock generation circuit 50. Hereinafter, only the characteristic part of this reference example will be described.

  The clock generation circuit 50 generates a delayed clock signal CLKd from the delayed clock signals CLKdr and CLKdf. FIG. 13 is a timing chart of the delay locked loop circuit according to this reference example. There are various methods for generating the delayed clock signal CLKd. For example, as shown in FIG. 13, the delayed clock signal CLKd rises when the delayed clock signal CLKdr rises and falls when the delayed clock signal CLKdf rises. You can do it.

In particular, by configuring the first and second delay locked loop circuits such that the delayed clock signals CLKdr and CLKdf rise at exactly half the on-duty and off-duty of the reference clock signal CLKr, respectively, the delayed clock signal CLKd Rises at exactly half the on-duty of the reference clock signal CLKr and falls at exactly half the off-duty. Here, when the period of the reference clock signal CLKr is T and the duty ratio is α, the on-duty time of the delayed clock signal CLKd is
αT / 2 + (1-α) T / 2 = T / 2
Thus, the cycle is exactly half (T / 2) of the reference clock signal CLKr. That is, the duty ratio of the delayed clock signal CLKd is 50% regardless of the duty ratio of the reference clock signal CLKr.

  As described above, according to the present reference example, the delayed clock signal CLKd whose logic level changes with a 1/4 phase (90 °) delay and a 3/4 phase (270 °) delay from the reference clock signal CLKr is generated. Further, the duty ratio of the reference clock signal CLKr is corrected.

Furthermore, in this reference example, if the delay element 10r and the delay element 10f are configured by a differential circuit, the configuration is stronger against noise. Specifically, the differential circuit shown in FIG. 14 can be used. A delay element 10A shown in FIG. 14 includes inverting circuits 11a and 11b similar to the inverting circuit 11 shown in FIG. 2, and a waveform shaping circuit 12A having a differential amplifier. Inverting circuits 11a and 11b, respectively, signals IN ⁺ and IN as a differential input signal ^- receiving a. The waveform shaping circuit 12A receives the outputs of the inverting circuits 11a and 11b, shapes the waveform, and outputs signals OUT ⁺ and OUT ⁻ . When applying a differential circuit shown in FIG. 14 in the delay locked loop circuit shown in FIG. 12, a reference clock signal CLKr as the signal IN ^+, the signal IN ^- enter the inverted signal of the reference clock signal CLKr as, signal OUT ⁺ and OUT ⁻ may correspond to the delayed clock signals CLKdr and CLKdf, respectively. Thus, by configuring the delay element with a differential circuit, in-phase noise generated in a power supply or the like is canceled, and a highly accurate delayed clock signal can be generated.

(Fifth reference example)
FIG. 15 shows a configuration of a delay locked loop circuit according to a fifth reference example. The delay locked loop circuit according to this reference example is different from the first and second delay locked loop circuits in the delay locked loop circuit according to the fourth reference example in that the reference clock signal CLKr and its inverse (hereinafter referred to as the opposite phase relationship) are used. , Expressed as “reference clock signal / CLKr”).

  The first and second delay locked loop circuits respectively output delayed clock signals CLKdr and CLKdf whose logic levels change with a delay from the rising (or falling) of the reference clock signals CLKr and / CLKr. That is, the second delay locked loop circuit substantially outputs the delayed clock signal CLKdf whose logic level changes after being delayed from the falling edge (or rising edge) of the reference clock signal CLKr. The delayed clock signal CLKd generated by is similar to that in the fourth reference example.

  In this reference example, the polarities of the first and second delay locked loop circuits can be made the same. Accordingly, since the same circuit can be used as the first and second delay locked loop circuits, circuit design is facilitated.

  In the fourth and fifth reference examples, a new delayed clock signal CLKd is generated from the delayed clock signals CLKdr and CLKdf generated by the delay elements 10r and 10f, respectively, but the present invention is not limited to this. It is not something. The delayed clock signal CLKd is a signal generated based on the delayed clock signals CLKdr and CLKdf in addition to the delayed clock signals CLKdr and CLKdf, and has a predetermined phase from the rising (or falling) of the reference clock signals CLKr and / CLKr. A signal whose logic level changes with a delay, for example, a signal UP or a signal DN generated by each of the signal generation circuits 20r and 20f may be used.

  Similarly, the output clock signal of the delay locked loop circuit according to the first embodiment and each reference example is not limited to the delayed clock signal CLKd generated by the delay element 10, for example, the signal generated by the signal generation circuit 20. In the case of UP or the first embodiment, the signal DN may be used. Since the signal UP is a waveform of the delayed clock signal CLKd, it is preferable to use the signal UP as the output of the delay locked loop circuit.

  Further, as shown in FIG. 4 and other timing charts, during the on-duty (or off-duty) of the reference clock signal CLKr, a change in the control voltage Vc that once increases (or decreases) and then returns to the original level is: According to the rising and falling edges of the reference clock signal CLKr and the rising edge of the delayed clock signal CLKd (or the falling edge when the delayed clock signal CLKd falls behind either the rising edge or the falling edge of the reference clock signal CLKr) This can be realized based on the signals UP and DN that change in a complementary manner. Therefore, various circuit configurations can be realized in addition to the signal generation circuit 20 and the charge pump circuit 30 described in the first embodiment and each reference example. For example, in the timing chart of FIG. 6, the configuration of the signal generation circuit 20 and the charge pump circuit 30 is changed so that the signal UP becomes the logic level Hi between the rise of the delay clock signal CLKd and the fall of the reference clock signal CLKr. Even so, there is no difference in the effect of the present invention.

  Since the delay locked loop circuit according to the present invention generates a delayed clock signal with high accuracy and no steady jitter regardless of the duty ratio of the reference clock signal, the delay locked loop circuit is particularly useful for a DDR (double data rate) standard interface. is there.

10, 10A, 10r, 10f Delay elements 11, 11a, 11b Inversion circuit (first circuit)
12, 12A Waveform shaping circuit (second circuit)
20, 20r, 20f Signal generation circuits 30, 30r, 30f Charge pump circuits 40, 40r, 40f Loop filter 50 Clock generation circuit 111 Transistor (first transistor)
112 transistor (second transistor)
113 transistor (third transistor)
114 transistor (current source)
121 Inverter 122 Transistor 301 Current source (first current source)
302 switch (first switch)
303 Current source (second current source)
304 switch (second switch)
305 Current source (third current source)
306 switch (third switch)
307 Current source (fourth current source)
308 switch (fourth switch)
309 Current source (fifth current source)
311 Resistance (first resistance)
312 Resistance (second resistance)
313 resistor (third resistor)
401 Capacitance 402 Operational Amplifier

Claims (6)

A delay element that delays from a first change from a first logic level to a second logic level of the reference clock signal to generate a delayed clock signal that changes from the first logic level to the second logic level;
Complementarily changes in response to a first change in the reference clock signal, a second change in the reference clock signal from the second logic level to the first logic level, and a change in the delayed clock signal. A signal generation circuit for generating first and second signals;
In accordance with the first and second signals, during the period from the first change of the reference clock signal to the change of the delayed clock signal, a first operation that is one of a push operation and a pull operation is performed, and the delay A charge pump circuit that performs a second operation, which is the other of a push operation and a pull operation, from a change in a clock signal to a second change in the reference clock signal;
A loop filter that integrates the output of the charge pump circuit and outputs an analog signal;
In the delay locked loop circuit, the delay element controls a delay amount from a first change of the reference clock signal to a change of the delay clock signal based on an output of the loop filter.
The delay element is
First and second transistors having opposite polarities connected in series and receiving the reference clock signal at the gate, and a third transistor connected between these transistors and receiving the output of the loop filter at the gate A first circuit having a voltage at a predetermined node between the first transistor and the second transistor as an output signal;
A delay locked loop circuit comprising: a second circuit that shapes a waveform of an output signal of the first circuit. The delay locked loop circuit of claim 1, wherein
The delay locked loop circuit, wherein the loop filter controls the third transistor with an output having a blunt waveform. The delay locked loop circuit of claim 1, wherein
One of the rising edge and the falling edge of the output signal of the first circuit changes gently with respect to the other. The delay locked loop circuit according to claim 3,
The second circuit generates the delayed clock signal having a sharp edge by shaping the waveform of one of the rising edge and the falling edge of the output signal of the first circuit that changes gently. A delay locked loop circuit. A delay element that outputs a delayed clock signal delayed by receiving a reference clock signal;
A signal generation circuit that individually inputs the reference clock signal and the delayed clock signal to generate and output a first signal and a second signal having different phases;
A charge pump circuit that outputs a current obtained by applying the first signal and the second signal individually and performing a push-pull operation;
A loop filter that outputs a signal obtained by integrating the output signal of the charge pump circuit;
An output terminal for outputting the delayed clock signal,
A delay-locked loop circuit, wherein a delay amount of one of rising and falling edges of the delayed clock signal is controlled by an output signal of the loop filter. The delay locked loop circuit of claim 5,
The delay element includes an inverting circuit that outputs a signal obtained by logically inverting an input signal, and a waveform shaping circuit that outputs a signal obtained by shaping the output signal of the inverting circuit.
A delay-locked loop circuit, wherein the output signal of the loop filter limits the charge transfer to the ground terminal in the inverting circuit.

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