JP4814754B2 - Communication device - Google Patents

Description

  The present invention relates to a communication device.

  In the spread spectrum communication apparatus, spread modulation is performed using a spread code on the transmission side, and the spread modulated signal is transmitted. On the other hand, on the receiving side, despreading is performed using the same reference spreading code as the spreading code. On the receiving side, it is necessary to perform despreading using the same spreading code at the same timing as the spreading code used on the transmitting side. For this reason, on the receiving side, it is necessary to establish the synchronization of the timing of the spreading code in the initial synchronization.

  In the following Patent Document 1, the data of the received baseband signal is shifted in the matched filter, the correlation value is obtained based on the shifted data and the reference code, and the control device refers to the matched filter in the first stage. The timing at which the correlation value obtained when the code is the short code for establishing synchronization is maximized is taken, and in the second stage, the short code for group identification that maximizes the correlation value while switching the group identification short code by the matched filter In the third stage, only the long codes belonging to the group specified by the group identification short code having the maximum correlation value are obtained.

  Also, in Patent Document 2 below, the reception timing detection circuit of the CDMA receiver sets an A / D converter that obtains a digital reception signal and a cross-correlation between the digital reception signal and a known signal sequence at predetermined intervals in advance. A sequence correlator obtained within a specified delay range, an interpolation filter for re-sampling the output signal at a frequency faster than the sampling frequency of the A / D converter, and power for obtaining the power of the re-sampled cross-correlation signal A calculation unit, an averaging unit that averages the cross-correlation signal power over a plurality of periods, and a peak detection unit that obtains a peak of the averaged cross-correlation signal power and determines an optimum reception timing.

Japanese Patent Laid-Open No. 11-340874 Japanese Patent Laid-Open No. 10-32523

  An object of the present invention is to provide a communication apparatus that can detect the peak of the correlation value of a spread spectrum modulated signal and a spread code with high accuracy.

According to one aspect of the present invention, a signal subjected to spread spectrum modulation using a spread code is input, a correlator that calculates a correlation value of the input signal and the spread code in symbol units, and a peak of the correlation value is detected. A first peak detector that performs an operation for integrating a plurality of symbols by inverting the sign of the correlation value when the peak is detected according to a slot pattern, and detecting the peak of the integrated correlation value And a second peak detector. A communication device is provided.

  By integrating the correlation values for a plurality of symbols and detecting the peak, the peak of the correlation value of the spread spectrum modulated signal and the spread code can be detected with high accuracy. As a result, the frequency can be controlled and synchronized with high accuracy.

(First embodiment)
FIG. 4 is a block diagram showing a configuration example of the receiving unit of the spread spectrum direct communication apparatus according to the first embodiment of the present invention, specifically, a configuration example of an automatic frequency control circuit (Automatic Frequency Controller) of the oscillator 409. Indicates.

  This communication apparatus receives a reception signal from a transmission unit of another communication apparatus, and generates a signal SS converted from a high frequency signal to an intermediate frequency signal. The received signal (input signal) SS is a signal that has been subjected to spread spectrum modulation using a spreading code. The quadrature demodulation circuit (mixer) 401 multiplies the received signal SS and the signal oscillated by the voltage controlled oscillator (VCO) 409, and outputs a baseband spread spectrum signal including an I signal and a Q signal. The low-pass filter 402 cuts off harmonic components and aliasing noise (folding noise) of the baseband spread spectrum signal, and passes other components. The analog / digital converter 403 samples the output signal of the low-pass filter 402 at a predetermined clock frequency, converts it from analog to digital, and outputs a digital received spread spectrum signal. The correlator 404 receives this digital received spread spectrum signal, calculates a correlation value with a spread code prepared in advance, and outputs it. The correlator 404 is a matched filter (MF). The peak detector 405 detects the power peak (maximum value) of this correlation value. The sweep controller 406 controls the sweep counter 407 in accordance with the peak detection result. The sweep counter 407 sequentially increments within a certain range until the above peak is detected, and stops counting when the above peak is detected. The digital / analog converter 408 converts the count value of the counter 407 from digital to analog and outputs the analog voltage to the voltage controlled oscillator 409. The voltage controlled oscillator 409 oscillates a signal having a frequency corresponding to the analog voltage. Demodulation circuit 410 performs spread spectrum demodulation (despreading) on the output signal of analog / digital converter 403 based on the spread code, and outputs demodulated data.

  In the spread spectrum communication apparatus, spread modulation is performed using a spread code on the transmission side, and the spread modulated signal is transmitted. On the other hand, on the receiving side, despreading is performed using the same reference spreading code as the spreading code. On the receiving side, it is necessary to perform despreading using the same spreading code at the same timing as the spreading code used on the transmitting side. For this reason, on the receiving side, it is necessary to establish the synchronization of the timing of the spreading code in the initial synchronization. That is, in the initial synchronization, it is necessary to control the oscillation frequency of the oscillator 409 so that the timing of the spreading code can be synchronized.

  FIG. 5 is a diagram illustrating frequency characteristics of power of correlation values. The horizontal axis represents the oscillation frequency freq of the oscillator 409. The vertical axis represents the power PWR of the correlation value output from the correlator 404. The power PWR of the correlation value indicates the sum of the square of the correlation value of the I signal output from the correlator 404 and the square of the correlation value of the Q signal.

  For example, when the counter 407 sequentially increases within a certain range and sweeps the frequency freq of the oscillator 409, the correlation value power PWR as shown in FIG. 5 is detected. When the frequency freq is changed, a peak of the correlation value power PWR occurs at the synchronization frequency fc. In the initial synchronization, the received signal SS includes a spreading code. The correlation value power PWR peaks at a frequency fc in which the spread code included in the received signal SS is synchronized with the spread code prepared in advance by the communication apparatus. The peak detector 405 detects the peak of the power PWR of this correlation value. When the peak of the power PWR is detected, the counter 407 stops the sweep count, assuming that the initial pull-in is completed at the oscillation frequency fc of the oscillator 409. As a result, the oscillation frequency of the oscillator 409 is fixed to the synchronization frequency fc. Thereafter, the demodulation circuit 410 performs spread spectrum demodulation on the output signal of the analog / digital converter 403 based on the spread code, and outputs demodulated data.

  Since the correlation value power PWR is almost flat near the synchronization center frequency fc, the peak detection of the power PWR for the detection of the center frequency fc may cause some error, and the system cannot tolerate this error. In such cases, problems arise.

  The purpose of this embodiment is to detect the peak of the power PWR with high accuracy. For that purpose, a steep characteristic may be obtained in the vicinity of the synchronization center frequency fc in the frequency characteristic of FIG.

  FIG. 6 is a diagram illustrating a configuration example of a transmission frame in spread spectrum communication. In order to establish a radio link, the common pilot channel CPICH having the largest received power (the peak power of the correlation value after despreading) is transmitted, and the receiving unit of the communication apparatus performs frequency control by detecting the peak of the correlation value of this pilot channel. I do.

  In the transmission frame, for example, 15 symbols SYM constitute one slot SL, and unique slot patterns SP0 to SP14 having excellent self and cross-correlation characteristics are provided for slot SL boundary discrimination. The fifteen symbols SYM have a spreading code SC and slot patterns SP0 to SP14. One symbol SYM has 256 chips. The slot patterns SP0 to SP14 are 15-bit patterns of “100110101111000”, for example. Hereinafter, each of the slot patterns SP0 to SP14 or their generic name is referred to as a slot pattern SP.

  The spreading factor SF represents the ratio of the spreading code rate (chip rate) to the transmission data rate (bit rate). The spreading factor SF is variable. Increasing the spreading factor SF complicates the spread spectrum demodulation process of the demodulation circuit 105 and decreases the bit rate.

  For example, when spreading factor SF is 256, one data can be transmitted for one symbol SYM on channel CPICH. When the spreading factor SF is 64, four data can be transmitted for one symbol SYM on the channel CCPCH. When spreading factor SF is 8, 32 data can be transmitted per symbol SYM on channel DPDCH.

  FIG. 1 is a diagram illustrating a configuration example of the correlator 404 and the peak detector 405 of FIG. The selector 103 selects the peak detection signal S139 output from the symbol calculator 101 or the peak detection signal S147 output from the slot calculator 102, and outputs the peak detection signal S148 to the sweep controller 406.

  The I signal INI and the Q signal INQ are signals input from the analog / digital converter 403. The shift register 111I sequentially receives and shifts the I signal INI and stores it. The shift register 111Q sequentially receives the Q signal INQ, shifts and stores it. The shift registers 111I and 111Q store signal data for one symbol SYM. One symbol SYM has 256 chips CP. Since the analog / digital converter 403 converts from analog to digital by four times oversampling, one chip CP has four data.

  The register 112I extracts I signal data of every fourth register in the shift register 111I, sequentially stores 256-bit I signal data, and outputs 256-bit I signal data S131I. The register 112Q extracts the Q signal data of every fourth register in the shift register 111Q, and sequentially stores the 256-bit Q signal data.

  The register 114I stores a 256-bit spreading code SC of the I signal in advance, and outputs a 256-bit spreading code S132I. The register 114Q stores a 256-bit spread code SC of the Q signal in advance.

  The multiplier 113I multiplies the 256-bit I signal data S131I and the 256-bit spread code S132I for each bit, and outputs a 256-bit correlation value S133I. When synchronization is established, the data S131I and the spread code S132I are the same. For each bit, the multiplier 113I outputs “+1” when the data S131I and 132I match, and outputs “−1” when they do not match. In the two's complement expression, “+1” is represented by 0 and “−1” is represented by 1.

  Similarly, the multiplier 113Q multiplies the 256-bit Q signal data of the register 112Q and the 256-bit spreading code of the register 114Q for each bit, and outputs a 256-bit correlation value.

  The integrator (adder) 115I integrates (adds) 256 correlation values S133I and outputs a correlation value S134I of the symbol SYM. Correlation value S134I is “+256” if all 256-bit spreading codes match, and “−256” if all do not match.

  Here, for each symbol SYM, the transmission unit of another communication apparatus transmits the spread code as it is if the slot pattern SP is 0, and inverts and transmits the spread code if the slot pattern SP is 1.

  Therefore, when synchronization is established, the correlation value S134I is “+256” when the slot pattern SP is 0, and “−256” when the slot pattern SP is 1. When the synchronization is not established, the correlation value S134I is a value close to “0”.

  Similarly, integrator (adder) 115Q integrates (adds) the correlation values output from 256 multipliers 113Q, and outputs correlation value S134Q of symbol SYM.

  The multiplier 116I outputs a correlation value S135I obtained by squaring the correlation value S134I of the I signal. The multiplier 116Q outputs a correlation value S135Q obtained by squaring the correlation value S134Q of the Q signal. Adder 117 adds correlation values S135I and S135Q, and outputs correlation value power S136. The power S136 corresponds to the power PWR of the correlation value on the vertical axis in FIG.

  The peak detector 118 detects the peak (maximum value) of the power S136 and outputs peak detection signals S137 and S139.

  When the peak detection signal S137 is input, the holding circuit 121 holds the correlation value S134I of the I signal and the correlation value S134Q of the Q signal, and outputs the held correlation value S138I of the I signal and the correlation value S138Q of the Q signal. To do.

  The shift register 122I sequentially inputs and shifts the correlation value S138I of the symbol SYM for the I signal and stores it. The shift register 122Q sequentially inputs and shifts the correlation value S138Q of the symbol SYM for the Q signal and stores it. The shift registers 122I and 122Q store correlation values for one slot SL. One slot SL has 15 symbols SYM. The shift register 122I outputs a correlation value S141I of 15 symbols.

  Similarly, the shift register 122Q sequentially inputs, shifts and stores the correlation value S138Q of the symbol SYM for the Q signal, and outputs the correlation value of 15 symbols.

  The register 124 stores 15-bit slot patterns SP0 to SP14 in advance, and outputs the stored 15-bit slot pattern S142.

  The multiplier 123I multiplies the 15 correlation values S141I and the 15-bit slot pattern S142, and outputs a correlation value S143I. That is, for each symbol SYM, the multiplier 123I outputs the correlation value S141I as the correlation value S143I as it is when the slot pattern S142 is 0, and the correlation value S143I by inverting the sign of the correlation value S141I when the slot pattern S142 is 1. Output as. Accordingly, when synchronization is established, when the slot pattern SP is 0, the correlation value S141I becomes “+256”, and the correlation value S143I also becomes “+256”. On the other hand, when the slot pattern SP is 1, the correlation value S141I is “−256” and the correlation value S143I is “+256”.

  Similarly, the multiplier 123Q multiplies the 15 correlation values of the shift register 122Q and the 15-bit slot pattern S142, and outputs a correlation value.

  The integrator (adder) 125I integrates (adds) 15 correlation values S143I and outputs a correlation value S144I of the slot SL. Similarly, the integrator (adder) 125Q integrates (adds) the 15 correlation values output from the multiplier 123Q, and outputs a correlation value S144Q of the slot SL.

  The multiplier 126I outputs a correlation value S145I obtained by squaring the correlation value S144I of the I signal. The multiplier 126Q outputs a correlation value S145Q obtained by squaring the correlation value S144Q of the Q signal. The adder 127 adds the correlation values S145I and S145Q, and outputs the correlation value power S146. The power S146 corresponds to the power PWR of the correlation value on the vertical axis in FIG.

  The peak detector 128 detects the peak (maximum value) of the power S146 and outputs a peak detection signal S147.

  As described above, the symbol calculator 101 detects the peak of the power S136 of the correlation value in symbol SYM units, and outputs the peak detection signal S139. On the other hand, the slot calculator 102 detects the peak of the power S146 of the correlation value for each slot SL, and outputs a peak detection signal S147. The selector 103 can selectively output the peak detection signal S139 or S147.

  Since the spreading factor SF is 256, the symbol calculator 101 detects a peak once in one symbol SYM (256 chips CP) and outputs a peak detection signal S139. The slot calculator 102 receives the correlation values of the 15 symbols SYM from the symbol calculator 101, detects the power peak of the correlation value using the slot pattern SP, and outputs a peak detection signal S147. The error that occurs when frequency control is performed using the peak detection signal S147 is reduced to 1/15 compared to the error that occurs when frequency control is performed using the peak detection signal S139, enabling highly accurate frequency control. To do.

  FIG. 2 is a diagram illustrating the frequency characteristic of the power of the correlation value when the peak detection signal S139 of the symbol calculator 101 or the peak detection signal S147 of the slot calculator 102 is used.

  A frequency characteristic 201 indicates a characteristic when frequency control is performed using the peak detection signal S139 of the symbol calculator 101, the horizontal axis indicates the oscillation frequency freq of the oscillator 409, and the vertical axis indicates the power S136 of the symbol correlation value. (PWR) is shown.

  The frequency characteristic 202 indicates the characteristic when frequency control is performed using the peak detection signal S147 of the slot calculator 102, the horizontal axis indicates the oscillation frequency freq of the oscillator 409, and the vertical axis indicates the power S146 of the correlation value of the slot. (PWR) is shown. In the above description, the case where one slot SL is composed of 15 symbols SYM has been described as an example. However, the frequency characteristic 202 represents the characteristic when one slot SL is composed of 16 symbols SYM.

  The frequency characteristic 202 is steeper in the vicinity of the synchronization frequency fc than the frequency characteristic 201. Therefore, when the frequency control is performed using the slot peak detection signal S147, the peak can be detected and the frequency can be controlled with higher accuracy than the frequency control using the symbol peak detection signal S139. it can. Thereby, the frequency control error can be reduced.

(Second Embodiment)
FIG. 3 corresponds to FIG. 1 and is a diagram illustrating a configuration example of the correlator 404 and the peak detector 405 of FIG. 4 according to the second embodiment of the present invention. In the present embodiment (FIG. 3), a threshold determination unit 301 is added to the first embodiment (FIG. 1). Hereinafter, differences of the present embodiment (FIG. 3) from the first embodiment (FIG. 1) will be described.

  The threshold value determination unit 301 outputs an initialization signal RS when the power S136 of the correlation value when the peak detector 118 detects a peak is smaller than the threshold value TH. When receiving the initialization signal RS, the shift registers 122I and 122Q initialize the stored contents to zero. Thereby, the peak detection is performed again.

  According to the present embodiment, the slot calculator 102 can detect the peak detector only when the power of the correlation value (absolute value of the correlation value) S136 when the peak is detected by the peak detector 118 is larger than the threshold value TH. The correlation values S134I and S134Q when the peak is detected at 118 are inverted with respect to the sign of the slot pattern SP and integrated for a plurality of symbols.

  For example, there is a possibility that the peak value of the power S146 of the correlation value due to the slot pattern SP becomes extremely small due to an instantaneous interruption of the received radio wave. In that case, it is possible to prevent erroneous discrimination of the synchronization frequency by resetting the shift registers 122I and 122Q as in the embodiment.

  As described above, the communication apparatuses according to the first and second embodiments receive the signals INI and INQ that have been subjected to spread spectrum modulation using the spread codes, and obtain the correlation values of the input signals INI and INQ and the spread codes SC in units of symbols. Correlators 113I, 113Q, 115I, and 115Q to be calculated; a first peak detector 118 that detects a peak of the correlation value; and a correlation value when the peak is detected is inverted according to a slot pattern SP. Then, it is characterized by having arithmetic units 123I, 123Q, 125I, 125Q for integrating a plurality of symbols, and a second peak detector 128 for detecting the peak of the integrated correlation value.

  According to the first and second embodiments, the correlation value of a plurality of symbols is integrated to detect the peak, thereby detecting the peak of the correlation value of the spread spectrum modulated signal and the spread code with high accuracy. Can do. As a result, the frequency can be controlled and synchronized with high accuracy.

  Further, a communication apparatus having the symbol calculator 101 and the slot calculator 102 can perform highly accurate frequency control without significantly changing the configuration as compared with a communication apparatus having only the symbol calculator 101.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure which shows the structural example of the correlator and the peak detector by the 1st Embodiment of this invention. It is a figure which shows the frequency characteristic of the electric power of a correlation value at the time of using the peak detection signal of a symbol calculator, or the peak detection signal of a slot calculator. It is a figure which shows the structural example of the correlator and the peak detector by the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the receiving part of a spectrum direct spread communication apparatus. It is a figure which shows the frequency characteristic of the electric power of a correlation value. It is a figure which shows the structural example of the transmission frame in spread spectrum communication.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Symbol calculator 102 Slot calculator 103 Selector 118,128 Peak detector 121 Holding circuit 301 Threshold judgment unit 401 Quadrature demodulation circuit 402 Low pass filter 403 Analog / digital converter 404 Correlator 405 Peak detector 406 Sweep controller 407 Sweep counter 408 Digital / analog converter 409 Voltage controlled oscillator 410 Demodulator circuit

Claims (5)

A correlator for inputting a signal subjected to spread spectrum modulation by a spreading code and calculating a correlation value between the inputted signal and the spreading code in units of symbols;
A first peak detector for detecting a peak of the correlation value;
An arithmetic unit that integrates a plurality of symbols by inverting the sign of the correlation value when the peak is detected according to the slot pattern;
And a second peak detector for detecting a peak of the integrated correlation value.   The computing unit reverses the sign of the correlation value when the peak is detected according to the slot pattern only when the absolute value of the correlation value when the peak is detected is larger than a threshold value, The communication apparatus according to claim 1, wherein the integration is performed for the symbol. The correlator receives the I signal and the Q signal as the input signal, calculates the correlation value of the correlation value and the Q signal of said I signal,
The first peak detector detects a power peak of the correlation value of the I signal and the correlation value of the Q signal;
The computing unit integrates the correlation value of the I signal and the correlation value of the Q signal,
3. The communication apparatus according to claim 1, wherein the second peak detector detects a power peak of the integrated correlation value of the I signal and the integrated correlation value of the Q signal.   The communication device according to claim 1, further comprising a selector that selectively outputs a detection signal of the first peak detector or a detection signal of the second peak detector. And an oscillator that oscillates a signal having a frequency corresponding to a detection signal of the second peak detector;
A quadrature demodulation circuit that quadrature-demodulates a signal subjected to spread spectrum modulation based on a signal oscillated by the oscillator;
The communication apparatus according to claim 1, wherein the correlator inputs the quadrature demodulated signal.

Images