JP4809173B2 - Multilayer ceramic capacitor - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor, in particular, relates to a multilayer ceramic con den support high capacity having a condenser body and the ceramic dielectric layers and internal electrode layers made thin is configured by alternately stacking.

In recent years, with the miniaturization and high functionality of electronic components, multilayer ceramic capacitors are required to be small in size and high in capacity, and accordingly, dielectric layers and internal electrode layers have been made thinner and multi-layered. For example, according to the following Patent Document 1, it is described that a dielectric powder having a particle size of 0.01 to 0.3 μm is used to form a dielectric layer having a thickness of 1.5 μm or less.
Japanese Patent Laid-Open No. 11-45617

  However, in a multilayer ceramic capacitor in which the dielectric layer and internal electrode layer are thin and highly laminated, the coverage ratio of the internal electrode layer to the dielectric layer is reduced due to deformation during lamination, and the capacitance decreases and its variation. In addition, there is a problem that a short circuit occurs because the surface roughness of the internal electrode layer increases due to deformation during lamination.

Accordingly the present invention, the dielectric layer and the internal electrode layer thin layer, even if high laminated, and an object thereof is to provide a multilayer ceramic con den service that can reduce the occurrence of increased and short reduction and variation in capacitance .

The multilayer ceramic capacitor of the present invention is a multilayer ceramic capacitor having an external electrode on an end face of a capacitor body in which dielectric layers and internal electrode layers are alternately stacked, and is provided per unit area of a peripheral portion of the internal electrode layer. vacancy number rather less than the pore number per unit area of the central portion excluding the peripheral portion, and an average pore area per unit area of the peripheral portion c, the unit of the central portion excluding the peripheral edge portion When the average hole area per area is d, the hole area ratio is 1.2 ≦ d / c ≦ 2.0 .

In the multilayer ceramic capacitor of the present invention, the number of holes per unit area in the peripheral portion excluding the connection end of the internal electrode layer with the external electrode is the number of holes per unit area in the central portion excluding the peripheral portion of the internal electrode layer. And the average pore area per unit area of the peripheral portion is c, and the average pore area per unit area of the central portion excluding the peripheral portion is d, the pore area ratio is 1.2 ≦ Since d / c ≦ 2.0 , defects are easily generated in the multilayer ceramic capacitor, and defects around the internal electrode layer having a large electric field effect are reduced. Even when stacked, it is possible to reduce the decrease in capacitance, increase in dispersion, and occurrence of short circuits.

  Hereinafter, the multilayer ceramic capacitor of the present invention will be described. FIG. 1 is a schematic sectional view showing a multilayer ceramic capacitor of the present invention.

  The capacitor body 1 constituting the multilayer ceramic capacitor of the present invention is composed of a multilayer body 7 in which a plurality of dielectric layers 5 are laminated, and an internal electrode layer 9 is a dielectric body inside the multilayer body 7. The layers 5 are alternately formed in the stacking direction, and are alternately drawn out in the stacking direction of the dielectric layers 5 to the first end surface 7 a and the second end surface 7 b facing the stack 7. The first external electrode 3a and the second external electrode 3b are connected to the connection ends 9a and 9b of the first end surface 7a and the second end surface 7b of the multilayer body 7, respectively.

  FIG. 2 is a plan view of the internal electrode layer in the multilayer ceramic capacitor of the present invention.

  As shown in FIG. 2, the internal electrode layer 9 includes a side of the connection end 9a connected to the first external electrode 3a on the first end surface 7a of the multilayer body 7, and a non-connection end on the opposite side of the connection end 7a. It has 9b sides.

In the multilayer ceramic capacitor of the present invention, the number of holes 13 per unit area in the peripheral portion 9c excluding the connection end 9a of the internal electrode layer 9 with the first external electrode 3a or the second external electrode 3b is unit area of the central portion 9d rather less than the number of holes 13 per unit area of the central portion 9d, and the average pore area per unit area of the peripheral edge portion 9c except c, and periphery 9c except for the peripheral portion 9c When the average hole area per hit is d, the hole area ratio is 1.2 ≦ d / c ≦ 2.0 .

In the present invention, the number of holes 13 per unit area in the peripheral portion 9c except thus external electrodes 3a of the internal electrode layer 9, the connection end 9a of the 3b is a central except a peripheral portion 9c of the internal electrode layer 9 The average hole area per unit area of the central part 9d excluding the peripheral part 9c is c and the average hole area per unit area of the peripheral part 9c is smaller than the number of holes 13 per unit area of the part 9d. When d, the area ratio of the holes is 1.2 ≦ d / c ≦ 2.0, so that even if the dielectric layer 5 and the internal electrode layer 9 are thin and highly stacked, the capacitance Reduction, increase in variation, and occurrence of short circuit can be reduced.

In the present invention, the number of holes 13 per unit area in the peripheral edge portion 9 c excluding the connection end 9 a of the internal electrode layer 9 with the external electrodes 3 a and 3 b is equal to that of the central portion 9 d excluding the peripheral edge portion 9 c of the internal electrode layer 9. the smaller range than the number of holes 13 per unit area, unit area numbers a and part of the central portion 9d of the inner electrode layer 9 of the peripheral edge portion 9c of the portion of the unit area those other Ri of the holes 13 equivalents the number b of Rino holes 13 Ru der satisfy the relation of 1.2 ≦ b / a ≦ 5.

  On the other hand, when the b / a ratio is smaller than 1.2, the number of holes 13 per unit area in the peripheral portion 9c and the central portion 9d of the internal electrode layer 9 is approximately the same, and the capacitance is reduced. Increase in variation and occurrence of short circuit are likely to occur.

  On the other hand, when the b / a ratio is larger than 5, the number of the holes 13 in the central portion 9d is too large in the first place, so that only a low capacitance can be obtained.

In the present invention, the width W of the peripheral edge portion 7c is preferably 5 to 15% of the width of the internal electrode layer 9 in the same direction as the width W of the peripheral edge portion 7c. The width of the internal electrode layer 9 in the same direction as the width W of the peripheral edge portion 7c is the direction indicated by the arrow in FIG. 2, for example, and in this case, the width W of the peripheral edge portion 7c is the internal electrode layer 9 in FIG. Corresponding to both the length L and the width W ₀ of the internal electrode layer 9.

In other words, the width W of the peripheral edge portion 7c is the internal electrode in a direction perpendicular to the distance L between the connection end 7a and the non-connection end 7b of the internal electrode layer 9 and the direction of the connection end 7a and the non-connection end 7b. A region of 8 to 15% of the interval W ₀ between the end portions of the layer 9 is desirable.

The width W of the peripheral edge portion 7c is the distance L between the connection end 7a and the non-connection end 7b of the internal electrode layer 9 or the direction of the internal electrode layer 9 in the direction perpendicular to the direction of the connection end 7a and the non-connection end 7b. When the distance W ₀ between the end portions is 8% or more, a region having a high film density can be increased in the peripheral portion 7c of the internal electrode layer 9 which is a region where the holes 13 are likely to be generated, and the capacitance is decreased. There is an advantage that variation can be reduced.

On the other hand, the width W of the peripheral edge portion 7c is the internal electrode layer in the direction perpendicular to the distance L between the connection end 7a and the non-connection end 7b of the internal electrode layer 9 or the direction of the connection end 7a and the non-connection end 7b. If it is less than 15% of the distance W ₀ between the ends of the 9, in the internal electrode layer 9, the ratio of ceramic powder between the large central portion 9d dielectric layer area is increased in the laminating direction of 5 the holes 13 As a result, the adhesiveness (connection strength) between the dielectric layers 5 can be increased, and there is an advantage that delamination and cracks can be suppressed.

  Here, the thickness of the internal electrode layer 9 is in the range of 1 to 2 μm and is preferably thinner than the thickness of the dielectric layer 5. There exists an advantage that the void | hole 13 can be suppressed as the thickness of the internal electrode layer 9 is 1 micrometer or more. When the thickness of the internal electrode layer 9 is 2 μm or less, there is an advantage that cracks and delamination can be suppressed.

  The dielectric layer 5 constituting the multilayer ceramic capacitor of the present invention preferably has a thickness in the range of 0.5 to 2.5 μm. When the thickness of the dielectric layer 5 is 0.5 μm or more, there is an advantage that high insulating properties can be obtained.

  On the other hand, when the thickness of the dielectric layer 5 is 2 μm or less, there is an advantage that an increase in capacitance due to the thinning can be expected.

The crystal particles 5a constituting the dielectric layer 5 are preferably composed mainly of at least BaTiO ₃ .

  Next, a method for producing the multilayer ceramic capacitor of the present invention will be described. FIG. 3 is a process diagram for manufacturing the multilayer ceramic capacitor of the present invention.

  First, a ceramic slurry is obtained by dispersing a barium titanate-based dielectric powder and an additive such as glass powder in a dispersion medium containing a binder.

  Next, the obtained slurry is formed into a sheet using a known coater, such as a doctor blade, to obtain a dielectric green sheet 31 that becomes the dielectric layer 5 after firing.

  The thickness of the dielectric green sheet is preferably in the range of 0.8 to 4 μm. The average particle size of the dielectric powder constituting the dielectric green sheet 31 is more preferably 0.1 μm or more in terms of high dielectric constant and 0.25 μm or less in terms of high insulation.

  Next, an internal electrode pattern 33 is formed on the dielectric green sheet 31. The conductive paste used in this printing uses a base metal powder which is Ni, Cu or an alloy powder thereof in that it can be fired simultaneously with a dielectric powder mainly composed of barium titanate used for the dielectric green sheet 31. Is preferred.

Internal electrode patterns 33 in the derivative collector green sheet on 31 is formed as follows (Figure 3 (b)).

Figure 4 (a) (b) are schematic views showing a method of forming the internal electrode pattern.

As shown in a plan view in FIG. 4A, a rectangular pattern 33a is formed on the surface of the dielectric green sheet 31 using a conductive paste containing a large amount of ceramic powder, and then around the rectangular pattern 33a. that form a small Ryo含 no frame pattern 33b ceramic powder than the rectangular pattern 33a. In this case, it is desirable that the rectangular pattern 33a and the frame pattern 33b have substantially the same thickness.

  The thickness of the internal electrode pattern 33 is preferably 1 to 2 μm. When the thickness of the internal electrode pattern 33 is 1 μm or more, there is an advantage that the voids 13 generated at the time of printing, laminating or after firing can be reduced.

  When the thickness of the internal electrode pattern 33 is 3 μm or less, there is an advantage that a step with the internal electrode pattern 33 on the dielectric green sheet 31 can be reduced.

Here, it is preferable that the width W _g1 of the frame pattern 33b is 2.5 to 8% of the long dimension interval L _g of the rectangular pattern 33a and 5 to 15% of the short dimension interval W _g2 . In this case, the width W _g1 of the frame pattern 33b is the direction corresponding to the direction and the part-length direction of the spacing W _g2 direction spacing L _g elongate direction of the rectangular pattern 33a.

  The amount of ceramic powder contained in the rectangular pattern 33a is preferably 25 to 40% by mass when the amount of metal powder is 100% by mass, while the amount of ceramic powder contained in the frame pattern 33b is the amount of metal powder. The content is preferably 5 to 20% by mass when the content is 100% by mass.

  In the present invention, it is desirable that the average particle size of the ceramic powder included in the frame pattern 33b is smaller than the average particle size of the ceramic powder included in the rectangular pattern 33a.

The average particle size of the ceramic powder having an average particle diameter of the base metal powder for forming the internal electrode pattern 33 is contained 0.2 to 0.4 [mu] m, in a rectangular pattern 33a is 0.3～0.35Myuemu, Furthermore, the average particle size of the ceramic powder contained in the frame pattern 33b is preferably 0.2 to 0.25 μm.

  Next, a plurality of dielectric green sheets 31 on which the internal electrode pattern 33 is formed are stacked to form a stacked body 35 (FIGS. 3C-1 and 3C-2). 3C-1 shows a surface parallel to the side margin side, and FIG. 3C-2 shows a surface parallel to the end margin side.

  Next, the laminate 35 is cut into a lattice shape to form a capacitor molded body 37 in which the end portions of the internal electrode pattern 33 are exposed (FIG. 3D), and then fired in a reducing atmosphere to perform the capacitor The main body 1 is formed.

  Next, as shown in FIG. 1, an external electrode paste is attached and baked on the end surface from which the internal electrode layer 9 of the capacitor body 1 is led out to obtain a multilayer ceramic capacitor having external electrodes 3a and 3b attached thereto.

  A multilayer ceramic capacitor was produced as follows. A barium titanate powder having a particle size of 0.3 μm was prepared as a raw material, an additive for controlling dielectric properties and a sintering aid were added thereto, and wet-mixed with zirconia balls using a mixed solvent.

  Next, a polyvinyl butyral resin and a mixed solvent of toluene and alcohol were added to the mixed powder, and wet mixing was similarly performed using zirconia balls to prepare a ceramic slurry. A dielectric green sheet having a thickness of 3 μm was prepared by a doctor blade method.

Next, a plurality of rectangular internal electrode patterns mainly composed of Ni were formed on the upper surface of the dielectric green sheet. As shown in FIGS. 3B and 3C, the internal electrode pattern was formed by dividing it into a rectangular pattern 33a and a frame pattern 33b. In this case, the width W of the peripheral edge is the ratio to the distance L between the connection end and the non-connection end of the internal electrode layer, and the end of the internal electrode layer in the direction perpendicular to the direction of the connection end and the non-connection end ratio interval W ₀ between was formed to be the same. In addition, the width W of the peripheral portion is a ratio of the pattern at the time of printing the internal electrode pattern.

The conductor paste used for the internal electrode pattern was Ni powder having an average particle size of 0.3 μm.

  The average particle size and amount of ceramic powder contained in the rectangular pattern and frame pattern constituting the internal electrode pattern, and the ratio of the width of the frame pattern were adjusted to the values shown in Table 1.

Next, 360 dielectric green sheets on which internal electrode patterns were printed were laminated, and 20 dielectric green sheets each having a thickness of 10 μm, on which the internal electrode patterns were not printed, were laminated on the upper and lower surfaces using a press machine. The capacitor body molded body was formed by batch lamination under conditions of a temperature of 60 ° C., a pressure of 10 ⁷ Pa, and a time of 10 minutes, and cut into predetermined dimensions.

Next, the obtained capacitor body molded body was debindered at 300 ° C./h in the air at a temperature rising rate of 10 ° C./h, and the temperature rising rate from 500 ° C. was 300 ° C./h. The capacitor body was fabricated by firing at 1170 ° C. (oxygen partial pressure 10 ⁻⁶ Pa) for 2 hours at a rate, followed by reoxidation treatment at 1000 ° C. for 4 hours in a nitrogen atmosphere. The size of the capacitor body was 2 × 1 × 1 mm ³ and the thickness of the dielectric layer was 2 μm.

  Next, the fired capacitor body was barrel-polished, and then an external electrode paste containing Cu powder and glass was applied to both ends of the capacitor body and baked at 850 ° C. to form external electrodes. Thereafter, using an electrolytic barrel machine, Ni plating and Sn plating were sequentially performed on the surface of the external electrode to produce a multilayer ceramic capacitor.

  Next, the following evaluation was performed on these multilayer ceramic capacitors.

After cutting the multilayer ceramic capacitor in parallel with the internal electrode layer, the internal structure was observed with a scanning electron microscope, and the hole number ratio and hole area ratio of the internal electrode layer were calculated by image processing. The number of vacancies in the internal electrode layer and the area of the vacancies were obtained by calculating the cumulative vacancy area with respect to the total area in the range of 100 μm ² . The number of samples was five, and the evaluated internal electrode layers were two points for each sample, and were obtained by averaging. Note that the pores found in the internal electrode layer were counted for those having a maximum diameter of 0.5 μm or more.

  The capacitance was measured with n = 20 under the measurement conditions of a frequency of 1.0 kHz, a measurement voltage of 0.5 Vrms, and 25 ° C. The capacity variation (CV) value was calculated as (standard deviation) / (average value) × 100.

In the thermal shock test, the temperature difference from room temperature was 340 ° C. using a solder bath. The number of samples evaluated was 100 for each sample.

  As is clear from Table 1, sample No. When the amount of ceramic powder in the peripheral portion and the central portion of the internal electrode layer was the same as in 1 and 2, the capacitance was small, the variation was large, and the short-circuit rate was large.

In contrast, the surface of the dielectric green sheet, an internal electrode pattern, to form a rectangular pattern containing many ceramic powder, then a small amount of a ceramic powder than rectangular shape pattern around the long square shape pattern The number of holes per unit area of the peripheral part in the internal electrode layer is smaller than the number of holes per unit area of the central part excluding the peripheral part and is Average pore area per unit area
c, where d is the average hole area per unit area in the central part excluding the peripheral part , the short ratio is 5 in the sample satisfying the relation that the hole area ratio is 1.2 ≦ d / c ≦ 2.0. %, The capacitance can be 8.5 μF, which is 85% or more of the set target value, and the CV value is also 5. It was as small as 0 % or less.

It is a schematic sectional drawing which shows the multilayer ceramic capacitor of this invention. It is a top view of the internal electrode layer in the inside of the multilayer ceramic capacitor of this invention. It is process drawing for manufacturing the multilayer ceramic capacitor of this invention. (A) is a step of forming a rectangular pattern on the surface of the dielectric green sheet, and (b) is a step of forming a frame pattern 33b around the rectangular pattern.

Explanation of symbols

1 .. Capacitor body 3a. First external electrode 3b. Second external electrode 5. Dielectric layer 7. Laminate 7a. First end surface 7b. Second end surface 9. Internal electrode layer 9a. Connection end 9b. Non-connection end 9c, peripheral edge portion 9d, central portion 13, hole 31, dielectric green sheet 33, internal electrode pattern 33a, rectangular pattern 33b, frame pattern 35, laminate 37, capacitor molded body

Claims (1)

A multilayer ceramic capacitor having an external electrode on an end surface of a capacitor body in which dielectric layers and internal electrode layers are alternately stacked, wherein the number of holes per unit area of the peripheral portion of the internal electrode layer rather less than the pore number per unit area of the central portion excluding, and an average pore area of c per unit area of the peripheral portion, the average pore area per unit area of the central portion excluding the peripheral edge portion A multilayer ceramic capacitor, wherein an area ratio of holes is 1.2 ≦ d / c ≦ 2.0, where d is d .

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