JP4877094B2 - Semiconductor device, semiconductor memory device, and semiconductor memory cell - Google Patents

Description

  The present invention relates to a semiconductor device having a function of holding or storing data, and more particularly to a semiconductor memory device and a semiconductor memory cell capable of holding data continuously while a power supply voltage is applied.

Static RAM (Random Access Memory) has the disadvantage that the number of elements constituting the memory cell is large. However, as long as the power supply voltage is applied, data is continuously stored without requiring a refresh operation. There is an advantage that a write / read operation can be performed. In general, a memory cell of a static RAM forms a flip-flop circuit by a pair of complementary metal oxide semiconductor (CMOS) inverters. More specifically, between the supply voltage terminal of the PMOS (P-channel MOS) transistor and the NMOS (N-channel MOS) power supply voltage terminal and the ground potential V _SS of the transistor and connected in series with the CMOS inverter power supply voltage V _DD comprising Are connected in parallel to each other, and each inverter input terminal and inverter output terminal are connected to each other's inverter output terminal and inverter input terminal by stroking or cross-coupled to each other, and 1 having a pair of data storage nodes Two bistable circuits or flip-flop circuits are formed.

In general, in this type of memory cell, a pair of data storage nodes as described above are connected to a pair of complementary bit lines via a pair of transfer gate transistors controlled on and off via a word line. Has been. When data is written to the memory cell, both bit lines are driven or precharged to two kinds of complementary (opposite logic levels) potentials according to the logical value of the write data to simultaneously transfer both transfer gate transistors. The voltage signals on both bit lines are turned on and input (written) to both data storage nodes via both transfer gate transistors. When reading stored data from the memory cell, turn on both transfer gate transistors at the same time and output the voltage of both data storage nodes to both bit lines via both transfer gate transistors. The read data is generated by binary detection of the voltage signal. In order to maintain the stored data in the memory cell, both transfer gate transistors may be turned off. However, the power supply voltage V _DD must be applied continuously, and if the application of the power supply voltage V _DD is stopped, the data for the data storage node that holds the H level voltage in the memory cell The supply of the holding current is stopped, and the stored data is lost.

  Some multi-port type static RAMs can simultaneously write or read two or more data in one cycle, and can simultaneously write and read in one cycle.

  Static RAMs composed of CMOS circuits as described above are often used in products and systems with low current consumption during operation and standby and with a small number of parts such as portable devices. However, in recent CMOS processes, the leakage current of MOS transistors increases with miniaturization and high speed, and it has become apparent that high speed and low power consumption cannot be achieved at the same time. On the other hand, in an actual product, for example, an application that simultaneously requires high-speed operation and low power consumption, such as handling a moving image on a mobile phone terminal, is increasing. That is, there is a need for a low power technology that satisfies both the limitations of the CMOS process and the demands of actual products.

  The present invention has been made in view of the above problems, and a semiconductor device, a semiconductor memory, and a semiconductor memory cell that achieve low power consumption by greatly reducing current consumption for data retention and standby current consumption. The purpose is to provide.

  In order to achieve the above object, the semiconductor memory cell of the present invention has a first and a second for electrically holding 1-bit data in the form of two kinds of voltages having opposite logic levels. A latch circuit including a data storage node and at least one MOS transistor; a switch circuit including at least one MOS transistor for connecting or separating the latch circuit to a peripheral circuit of the latch circuit; and the switch A transfer gate including a MOS transistor that is connected in series to the circuit and that selects the latch circuit in response to an activation signal supplied in response to an address signal, and is supplied to the peripheral circuit. A second power supply voltage independent of the first power supply voltage is supplied to the latch circuit, and the second power supply voltage for the peripheral circuit is The switch circuit is turned on / off in conjunction with the on / off of the power supply voltage of the transistor, and the MOS transistor included in the latch circuit and the switch circuit has a leakage current higher than that of the MOS transistor included in the peripheral circuit and the transfer gate. The switch circuit is configured by a small low-leakage MOS transistor, and when the supply of the first power supply voltage to the peripheral circuit is in an off state, the off state of the switch circuit is maintained.

  The semiconductor device of the present invention includes a latch circuit including at least one MOS transistor for electrically holding 1-bit data in the form of a voltage, and at least one MOS for exchanging data with the latch circuit. A peripheral circuit including a transistor, a switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the peripheral circuit, and connected in series to the switch circuit, in response to an address signal A transfer gate including a MOS transistor for selecting the latch circuit in response to a supplied activation signal; a first power supply voltage supply unit for supplying a first power supply voltage to the peripheral circuit; and the latch circuit A second power supply voltage supply section for supplying a second power supply voltage to the second power supply voltage supply section; A first control unit for independently controlling on / off of the first power supply voltage supply unit; and on / off of the switch circuit in conjunction with on / off of the first power supply voltage supply unit A low-leakage MOS having a leakage current smaller than that of the MOS transistors included in the peripheral circuit and the transfer gate. When the first power supply voltage supply unit is controlled to be turned off by the first control unit, the switch circuit is held in the off state by the second control unit.

  According to another aspect of the present invention, there is provided a semiconductor memory device including a latch circuit including at least one MOS transistor for electrically holding 1-bit data in the form of a voltage, and at least one MOS for writing data to the latch circuit. A write circuit including a transistor; a first switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the write circuit; and at least one MOS transistor for reading data from the latch circuit A read circuit including: a second switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the read circuit; and an address connected to the first switch circuit in series. Write activity supplied in response to signal A first transfer gate including a MOS transistor for selecting the latch circuit in response to a signal; a first power supply voltage supply unit for supplying a first power supply voltage to the write circuit and the read circuit; A second power supply voltage supply section for supplying a second power supply voltage to the latch circuit; and for controlling on / off of the first power supply voltage supply section independently of the second power supply voltage supply section. A first control unit, and a second control unit for controlling on / off of the first and second switch circuits in conjunction with on / off of the first power supply voltage supply unit. MOS transistors included in the latch circuit and the first and second switch circuits are replaced with MOS transistors included in the write circuit, the read circuit, and the first transfer gate. When the first power supply voltage supply unit is off-controlled by the first control unit, the first and second switch circuits are configured with the low-leakage MOS transistor having a smaller leakage current than the first power supply voltage supply unit. The second control unit holds the off state.

  According to the present invention, the independent power supply voltage is supplied to the latch circuit and the peripheral circuit (for example, the write circuit and the read circuit), and the first power supply voltage supply unit cuts off the first power supply voltage for the peripheral circuit. The power supply of the second power supply voltage to the latch circuit can be maintained by the second power supply voltage supply unit, and the latch circuit can safely store the stored data. Moreover, since the latch circuit is composed of a low-leakage MOS transistor, data can be held with a small standby current or consumption current. Further, while the first power supply voltage on the peripheral circuit side is cut off, the switch circuit composed of the low-leakage MOS transistor is turned off to separate the latch circuit from the peripheral circuit. Current leakage can be sufficiently prevented, so that further reduction in power can be realized.

  In the present invention, the leakage current of the low leakage type MOS transistor is preferably 1/10 or less of the leakage current of the MOS transistor included in the peripheral circuit.

  As a preferred aspect of the semiconductor memory cell of the present invention, the latch circuit has a first terminal connected to the first data storage node, a second terminal connected to the power supply voltage terminal of the reference potential, and a control terminal. Has a first NMOS transistor connected to a second data storage node, a first terminal connected to the second data storage node, and a second terminal connected to the power supply voltage terminal of the reference potential The control terminal may include a second NMOS transistor connected to the first data storage node. Furthermore, the latch circuit has a first terminal connected to the first data storage node, a second terminal connected to the power supply voltage terminal of the first power supply voltage supply unit, and a control terminal connected to the second data storage node. The first PMOS transistor connected to the storage node, the first terminal is connected to the second data storage node, the second terminal is connected to the power supply voltage terminal of the first power supply voltage supply unit, and the control A configuration in which the terminal has a second PMOS transistor connected to the first data storage node is also preferable. However, the latch circuit includes a first resistance element having a first terminal connected to the first data storage node and a second terminal connected to the power supply voltage terminal of the first power supply voltage supply unit; It is also possible to have a configuration in which one terminal is connected to the second data storage node, and the second terminal is connected to the power supply voltage terminal of the first power supply voltage supply unit.

  In one embodiment of the present invention, a semiconductor memory cell includes at least first and second data storage nodes for electrically holding 1-bit data in the form of two types of voltages having opposite logic levels. A latch circuit including one MOS transistor, a first switch circuit for connecting or separating the first data storage node with respect to the first write bit line, and a second write bit line And a second switch circuit for connecting or separating the second data storage node, and at least one MOS transistor for outputting a voltage read from the latch circuit to a read bit line And an output circuit that is connected in series to the first switch circuit and is supplied in response to an address signal A first transfer gate including a MOS transistor for selecting the latch circuit in response to an activation signal for input and a second switch circuit connected in series and supplied in response to an address signal A second transfer gate including a MOS transistor for selecting the latch circuit in response to a write activation signal, and an input terminal of the output circuit is connected via one of the first or second switch circuit. A second power supply voltage that is connected to the first or second data storage node of the latch circuit and is independent of the first power supply voltage supplied to the output circuit is supplied to the latch circuit, and is connected to the output circuit. The first and second switch circuits are turned off and on in conjunction with the turning on and off of the first power supply voltage, and the latch circuit and the first and second switching circuits are turned on and off. Consisting of a small low-leakage MOS transistors leakage current than MOS transistors MOS transistors included in the second switch circuit is included in the output circuit.

  In the present invention, a switch circuit for separation is provided between the bit line and the memory cell (latch circuit) separately from the transfer gate for selection. Since the switch circuit is composed of a low-leakage MOS transistor, even if some noise is superimposed on the gate terminal of the MOS transistor constituting the switch circuit, a leak current that changes the stored data in the memory cell does not occur. Data retention characteristics are improved.

  According to the semiconductor device, the semiconductor memory, and the semiconductor memory cell of the present invention, the above-described configuration and operation can significantly reduce the current consumption for data retention and the current consumption during standby, thereby realizing low power consumption. it can.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a circuit configuration of a static RAM memory cell according to an embodiment of the present invention. This memory cell is configured as an asynchronous 2-port (1 write port + 1 read port) memory cell, and includes one word line WWL for writing and a pair of bit lines WBL and WBLZ and a pair of words for reading. It is connected to the lines RWL, RWLZ and one bit line RBL.

The latch circuit 10 of the memory cell includes a pair of CMOS inverters, that is, two PMOS transistors 12 and 14 and two NMOS transistors 16 and 18. More specifically, the source terminals of the PMOS transistors 12 and 14 are connected to the power supply voltage terminal of the power supply voltage V _RET , while the source terminals of the NMOS transistors 16 and 18 are connected to a reference potential such as the ground potential V _SS . is connected to the supply voltage terminal, the first data storage node N _a are respectively formed at the drain terminal of the PMOS transistor 12 and NMOS transistor 16 are interconnected, the drains of the PMOS transistor 14 and NMOS transistor 18 terminals are interconnected by a second data storage node N _b is formed. The first data storage node N _a is connected to the respective gate terminals of the PMOS transistor 14 and the NMOS transistor 18 facing it, and the second data storage node N _b is connected to the PMOS transistor 12 and The NMOS transistor 16 is connected to each gate terminal. In short, the PMOS transistor 12 and the NMOS transistor 16 constitute one CMOS inverter, and the PMOS transistor 14 and the NMOS transistor 18 constitute the other CMOS inverter, and each CMOS inverter input terminal ( The gate terminal) and the output terminal (node) are respectively connected to the counterpart output terminal (node) and input terminal (gate terminal), and V _RET is applied as the power supply voltage.

In the latch circuit 10, the first data storage node N _a is electrically connected to one of the write bit line WBL via the NMOS transistor 20 and 22, a second data storage node N _b is The other write bit line WBLZ is electrically connected via the transmission gate 24 and the NMOS transistor 30.

More specifically, the NMOS transistor 20 and NMOS transistor 22 are connected in series between the first data storage node N _a and one of the write bit line WBL. Here, NMOS transistor 20, which constitutes the switch circuit of the latch circuit enclosure for connecting or separating the first data storage node N _a of the latch circuit 10 to the peripheral circuits, the gate terminal Is supplied with a control signal RETZ from a power supply control unit 70 (FIG. 3) described later. The NMOS transistor 22 constitutes a transfer gate for writing, and a word line WWL for writing is connected to the gate terminal.

On the other hand, a transmission gate 24 and the NMOS transistor 30 between the second data storage node N _b and the other write bit line WBLZ are connected in series. The transmission gate 24 becomes connected in parallel to the NMOS transistor 26 and PMOS transistor 28, latch circuit enclosure for connecting or separating the second data storage node N _b of the latch circuit 10 to the circuit around The switch circuit is configured. Control signals RETZ and RET are applied to the respective gate terminals of the NMOS transistor 26 and the PMOS transistor 28 at complementary logic levels (H level / L level) from the power supply control unit 70 (FIG. 3). The NMOS transistor 30 constitutes a transfer gate for writing, and a word line WWL for writing is connected to the gate terminal thereof.

This memory cell has an output circuit 32 for providing an output port independent of the input port. The output circuit 32 is configured as a clock-type CMOS inverter composed of two PMOS transistors 34 and 36 and two NMOS transistors 38 and 40, and a power supply voltage V different from the power supply voltage _VRET of the latch circuit 10. It is supposed to work under _DD . More specifically, the PMOS transistor 34 and the NMOS transistor 40 constitute a CMOS inverter, and the PMOS transistor 36 and the NMOS transistor 38 are provided as read transfer gates. That is, the source terminal of the PMOS transistor 34 is connected to the power supply voltage terminal of the power supply voltage V _DD , the source terminal of the NMOS transistor 40 is connected to the power supply voltage terminal of the ground potential V _SS , and the drain terminals of both transistors 34 and 40 are connected. Are connected to an output node or data output terminal N _OUT via a PMOS transistor 36 and an NMOS transistor 38, respectively, and the gate terminals of both transistors 34 and 40, that is, the CMOS inverter input terminal (node N _d ) are the transmission gate 24 and the NMOS transistor 30. _Are connected to a node _Nc between Complementary read word lines RWLZ and RWL are connected to the gate terminals of the PMOS transistor 36 and the NMOS transistor 38, respectively. The data output terminal N _OUT is connected to the read bit line RBL.

PMOS transistor 42 is provided between the input terminal or the node N _d of the power supply voltage terminal and the output circuit 10 of the power supply voltage V _DD is connected. The PMOS transistor 42 serves to prevent the floating state of the node N _d when to turn off the power supply voltage V _DD in standby mode as described later, to a gate terminal power supply control unit 70 (FIG. 3) Is supplied with a control signal RETZ.

  One of the features of this memory cell is that all of the MOS transistors 12, 14, 16, 18 constituting the latch circuit 10 and the MOS transistors 20, 26, 28 constituting the switch circuit are low-leakage MOS transistors. This means that the leakage current is much smaller (preferably 1/10 or less) than the leakage current of the standard MOS transistor constituting the peripheral circuit including the output circuit 32. For example, it has been confirmed that a leakage current can be reduced to about 1/60 of that of a standard MOS transistor in a low leakage MOS transistor in which the thickness of the gate oxide film is set to be twice as large as that of a standard MOS transistor. . By selecting the conditions or characteristics of the MOS process, it is possible to arbitrarily set the division between the low-leakage MOS transistor and the standard MOS transistor.

  In general, however, a low-leakage MOS transistor operates at a lower speed than a standard MOS transistor. However, since the latch circuit 10 is a bistable circuit and has a positive feedback loop as described above, even if the latch circuit 10 is composed of low-leakage MOS transistors 12, 14, 16, and 18, there is no substantial decrease in the operating speed. However, since it is surrounded by a switch circuit composed of low-leakage MOS transistors 20, 26 and 28, the writing speed is only slightly lower than in the prior art. Since reading is performed in the form of charge reading through the output circuit 32 formed of a CMOS inverter, the reading performance is hardly affected.

In this memory cell, separate power supply voltages V _RET and V _DD are respectively supplied to the latch circuit 10 and the output circuit 32 as described above. The power supply voltage V _RET is a power supply voltage for memory backup mainly specialized in data retention or storage, and power is supplied continuously as long as the main power switch of the device is turned on. . On the other hand, the power supply voltage V _DD is a power supply voltage for normal operation that is used for almost all circuit operations other than data retention, and is cut off conditionally even while the main power switch of the device is on. It has become. That is, in the device, the power supply voltage V _DD is supplied during the normal mode in which the predetermined user function is working, and the power supply voltage V _DD is cut off during the standby mode in which the user function is temporarily stopped. It has become.

  In this memory cell, during normal mode, control signals RETZ and RET from the power supply control unit 70 (FIG. 3) are set to H level and L level, respectively, and the NMOS transistor 20 for enclosing the latch circuit and the transmission gate 24 are turned on. The PMOS transistor 42 for preventing floating is kept in the off state.

When 1-bit data is written to the memory cell, both write bit lines WBL and WBLZ are driven or precharged to complementary logic level (H level / L level) potentials according to the value of the write data. Then, the write word line WWL is activated to H level, and both transfer gates 22 and 30 are simultaneously turned on. Then, at the same time the voltage signal on one bit line WBL is written in the first data storage node N _a via the transfer gate 22 and the NMOS transistor 20, the transfer voltage signal on the other bit line WBLZ gate through the 30 and transmission gate 24 is written into the second data storage node N _b. At this time, a positive feedback loop works in the latch circuit 10 and the write voltages to both data storage nodes N _a and N _b are instantaneously stabilized. Note that it is possible to give a voltage signal of H level to both the bit lines WBL and WBLZ in the write cycle, but in this case, the stored contents in the memory cell are not changed, and the data held until then is stored. Maintained. It is prohibited to apply an L level voltage signal to both bit lines WBL and WBLZ.

When reading 1-bit data from the memory cell, the read word lines RWLZ and RWL are activated to L level and H level in the output circuit 32, respectively, and both transfer gates 36 and 38 are simultaneously turned on. At this time, since the potential of the node N _c is approximately equal potential to the second data storage node N _b via the transmission gate 24, as a voltage signal is output data having a logic level potential opposite node N _c The data is output from the data output terminal N _OUT onto the read bit line RBL.

When the device changes from the normal mode to the standby mode, in this memory cell, the power supply voltage V _DD is cut off with respect to the output circuit 32, and the control signals RETZ and RET from the power supply control unit 70 (FIG. 3) respectively. The NMOS transistor 20 and the transmission gate 24 for enclosing the latch circuit are turned off, and the floating prevention PMOS transistor 40 is turned on. Data is not written or read during the standby mode, and all the transfer gates 22, 30, 36, and 38 are kept off. The power supply voltage V _RET is supplied to the latch circuit 10 even during the standby mode.

During such a standby mode, the latch circuit 10 holds the stored data with a very small data holding current by the low-leakage MOS transistors 12, 14, 16, and 18 under the power supply voltage V _RET , and the standard MOS transistor A stable data holding function is achieved with much less power consumption than in the case of the above. Moreover, the latch circuit 10 is enclosed by the low-leakage MOS transistors 20 and (26, 28), and during the standby mode, the low-leakage MOS transistors 20, 26 and 28 are turned off to Therefore, the current hardly leaks from the latch circuit 10 to the peripheral circuit. In the output circuit 32, the power supply voltage V _DD is cut off during the standby mode, so that no power is consumed.

The PMOS transistor 42 for preventing floating is turned on immediately before the power supply voltage V _DD is cut off, and clamps the potential of the node N _d (input of the output circuit 32) to the level (H level) of the power supply voltage V _DD. The node _Nd is prevented from floating in the transition period until the voltage V _DD is completely cut off. That is, when the node _Nd is in a floating state, the output circuit 32 may cause a current passing through the MOS transistors 34, 36, 38, and 40 to break down the transistors. By thus preventing the floating state of the node N _d in the clamp by the PMOS transistor 42, it prevents the through current in the output circuit 32, to ensure the safety of the MOS transistors 34, 36, 38, 40 it can.

  In the memory cell of this embodiment, switch circuits 20, 24 (26, 28) for separation are provided between the bit lines WBL, WBLZ and the latch circuit 10 in addition to the transfer gates 22, 30 for selection. . Since the switch circuits 20, 24 (26, 28) are composed of low-leakage MOS transistors, even if some noise is superimposed on the gate terminals of the MOS transistors constituting the switch circuits, the data stored in the memory cell is changed. Leakage current that does not occur is not generated, and the data retention characteristics are improved.

FIG. 2 shows an example of the state change or timing of each unit when switching between the normal mode and the standby mode. As in this example, when switching from the normal mode to the standby mode, the control signals RET and RETZ are switched to the standby mode H level and L level, respectively, before the power supply voltage V _DD is cut off, and the standby mode is returned to the normal mode. In this case, it is preferable to return the control signals RET and RETZ to the L level and the H level for the normal mode after the power supply voltage V _DD is turned on and the inside is stabilized.

  FIG. 3 shows the overall configuration of the static RAM in this embodiment. The static RAM includes a memory cell array 50 formed as an integrated circuit on the same semiconductor chip, address buffers 52 and 54, address decoders 56 and 58, word line drivers 60 and 62, data buffers 64 and 66, and a memory control unit 68. And a power control unit 70 and the like. The memory cell array 50 includes the above-described memory cells (FIG. 1), and the number of memory cells (FIG. 1) equal to the number of bits of the memory size is provided in an array with a predetermined layout.

  When a memory access for writing is performed on the static RAM, an address signal for writing is sent to the writing address buffer 52 at an arbitrary timing from an associated external circuit (not shown), and writing data is sent to the input data buffer. 64, a control signal for writing is supplied to the memory control unit 68, respectively. The write address decoder 56 decodes the input write address signal and supplies a signal for selecting or activating any one write word line WWL in the memory cell array 50 to the write word line driver 60. When the write word line driver 60 activates the selected word line WWL, the write transfer gates 22 and 30 are respectively connected to the memory cells (FIG. 1) connected to the word line WWL in the memory cell array 50. Turn on. Then, the data for one word is transmitted from the input data buffer 64 to the memory cell array 50 via a pair of bit lines WBL and WBLZ for each bit, and is written in each corresponding memory cell (FIG. 1).

When a read memory access is made to the static RAM, a read address signal is sent to a read address buffer 54 and a read control signal is sent at an arbitrary timing from an associated external circuit (not shown). Each is given to the memory control unit 68. The read address decoder 58 decodes the input read address signal and outputs a signal for selecting or activating any one of the read word lines RWL and RWLZ in the memory cell array 50. To give. When the read word line driver 62 activates the selected set of read word lines RWL and RWLZ, in each memory cell (FIG. 1) connected to the word lines RWL and RWLZ in the memory cell array 50. The read transfer gates 38 and 36 of the output circuit 32 are turned on. Then, the read data output from the data output terminal N _OUT of the output circuit 32 as described above is sent to the output data buffer 66 through the read bit line RBL, and the output data buffer 66 to the related external circuit. Sent out.

In this static RAM, only the memory cell array 50 operates under both the power supply voltage V _RET for memory backup and the power supply voltage V _DD for normal operation. In addition to the address buffers 52 and 54 and the data buffers 64 and 66, etc. The functional circuits 52 to 68 operate under the power supply voltage V _DD for normal operation. As long as the main power switch is turned on, the power control unit 70 functions at any timing regardless of the main normal mode or the standby mode. Under the power supply voltage other than the power supply voltage V _DD , for example, V _RET May work. Therefore, during the normal mode, power is consumed under the power supply voltage V _DD or V _RET in all the functional blocks 50 to 70. During the standby mode, the power supply voltage V _DD is cut off, so that the power consumption of the V _DD function circuits 52 to 68 is completely eliminated. Further, the V _RET functional circuit, particularly the latch circuit 10 of each memory cell in the memory cell array 50 is not only composed of a low-leakage MOS transistor as described above, but also includes a switch circuit 20 composed of a low-leakage MOS transistor, 24, and in the standby mode, the switch circuits 20 and 24 isolate the peripheral _VDD circuit from the surroundings. Therefore, power consumption for data retention and current leakage is extremely small, and the entire memory cell array 50 is also consumed. There is very little power.

FIG. 4 schematically shows the configuration of the power supply voltage supply system in this embodiment. As shown in the figure, power supply voltages V _DD and V _RET output from an external power supply circuit (not shown) are respectively drawn into power supply lines in the chip via predetermined power supply input terminals or pads of the semiconductor chip 72. A power switch 74 is provided in the middle of the power line of the power supply voltage V _DD , and the power control unit 70 controls on / off of the power switch 74. The power supply line of the power supply voltage V _RET is directly connected to each part (particularly the memory cell array 50) to be fed. In the case of setting the power supply voltage V _RET to the same voltage level as the power supply voltage V _DD, the power supply to a fork from the power line of the power supply voltage V _DD by the upstream side of the power switch 74 as indicated by the dotted line 76 in FIG. 4 It can also be used for a power supply line of voltage V _RET .

The power supply control unit 70 inputs a mode control signal CNTR from an external main controller (not shown) that performs overall control of the operation and state of the entire device as a command via the control input terminal or pad of the chip 72, and the command content To control each related part. That is, when the normal mode is instructed by the main controller, the control signals RET and RETZ for the memory cells (FIG. 1) in the memory cell array 50 are held at the L level and the H level, respectively, as described above. The enclosing switch circuits 20 and 24 are turned on, the floating prevention transistor 42 is turned off, and the power switch 74 is turned on to supply the power supply voltage V _DD to each part. When the standby mode is instructed from the main controller, the control signals RET and RETZ for each memory cell (FIG. 1) in the memory cell array 50 are switched to the H level and the L level, respectively, as described above. The switch circuits 20 and 24 are turned off, the floating prevention transistor 42 is turned on, and the power switch 74 is turned off to cut off the supply of the power supply voltage V _DD to each part. Note that functional circuits 78 and 80 in FIG. 4 indicate arbitrary V _DD system circuits mounted on the semiconductor chip 72.

Although only one memory cell array 50 is shown in FIG. 4, in practice, many memory cell arrays or static RAMs are often distributed on one semiconductor chip 72. Even in such a case, power control for each V _RET circuit and V _DD system circuit is performed in the same manner as described above in each memory cell array, static RAM, and any other logic circuit. According to the present invention, the power consumption of the standard MOS transistor constituting the V _DD system circuit can be suppressed by shutting off the power supply in the standby mode, so that even if the leakage current increases, the speed can be increased. A MOS process can be suitably employed. On the other hand, in an actual product equipped with a semiconductor chip according to the present invention, not only can the performance be improved by increasing the speed of the V _DD system circuit, but also the memory in the V _RET system circuit can be effectively utilized by maximizing the standby mode. The power consumption of the entire chip can be reduced while ensuring the safety of data.

FIG. 5 shows a modification of the memory cell in the above embodiment. There are three main deformations. One is that the PMOS transistors 12 and 14 (FIG. 1) in the latch circuit 10 are replaced with resistance elements 82 and 84. Such a resistance load type has the disadvantage that the current consumption during operation and standby increases more than the MOS load type using PMOS transistors 12 and 14, but has the advantage of high integration density. is there. The second modification is that the PMOS transistor 42 (FIG. 1) for preventing floating in the output circuit 32 is replaced with an NMOS transistor 86. In this case, NMOS transistor 86 is connected between the power supply terminal of the input terminal or node N _d and the ground potential V _SS of the output circuit 32, the control signal RET from the power supply control unit 70 is supplied to its gate terminal. NMOS transistor 86 is turned from the normal mode when shifting to the standby mode will clamp the node N _d to the ground potential V _SS (L level) by. The third modification is that the transfer gate 22 for writing independent from the output port is omitted, and the NMOS transistor 20 of the switch circuit 20 also functions as the transfer gate 22. In this manner, the switch circuit for enclosing the latch circuit can also function as the transfer gate. The transmission gate 24 has an excellent signal propagation function with little voltage drop for both the H level and the L level. If necessary, the transmission gate 24 can be a single MOS transistor. For example, it can be replaced with an NMOS transistor.

  The present invention is not limited to the asynchronous 2-port (1 write port + 1 read port) memory cell and static RAM in the above embodiment, but can arbitrarily hold data while a power supply voltage is applied. The present invention can be applied to any semiconductor memory device, or any semiconductor memory device or semiconductor device including this type of semiconductor memory cell.

1 is a circuit diagram showing a circuit configuration of a memory cell of a static RAM according to an embodiment of the present invention. It is a timing diagram which shows the state change of each part at the time of switching to the normal mode and standby mode in embodiment. It is a block diagram which shows the whole static RAM structure in embodiment. It is a figure which shows typically the structure of the power supply voltage supply system in embodiment. It is a circuit diagram which shows the modification of the memory cell in embodiment.

Explanation of symbols

10 latch circuit 12, 14 PMOS transistor 16, 18 NMOS transistor 20 NMOS transistor (switch circuit)
22 (Transfer gate for writing)
24 Transmission gate (switch circuit)
26 NMOS transistor (switch circuit)
28 PMOS transistor (switch circuit)
30 NMOS transistor (write transfer gate)
32 Output circuit 34 PMOS transistor (CMOS inverter)
36 PMOS transistor (readout transfer gate)
38 NMOS transistor (readout transfer gate)
40 NMOS transistor (CMOS inverter)
42 (For floating prevention) PMOS transistor 50 Memory cell array 70 Power supply control unit 72 Semiconductor chip 74 Power switch 42 (For floating prevention) NMOS transistor

Claims (12)

A latch circuit for electrically holding 1-bit data in the form of a voltage;
A peripheral circuit for exchanging data with the latch circuit;
A switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the peripheral circuit;
A transfer gate including a MOS transistor connected in series to the switch circuit and selecting the latch circuit in response to an activation signal supplied in response to an address signal;
A first power supply voltage supply unit for supplying a first power supply voltage to the peripheral circuit;
A second power supply voltage supply unit for supplying a second power supply voltage to the latch circuit;
A first control unit for controlling on / off of the first power supply voltage supply unit independently of the second power supply voltage supply unit;
A second control unit for controlling on / off of the switch circuit in conjunction with on / off of the first power supply voltage supply unit;
Have
The MOS transistor included in the latch circuit and the switch circuit is configured with a low leak type MOS transistor having a leakage current smaller than that of the MOS transistor included in the peripheral circuit and the transfer gate,
The semiconductor device, wherein the switch circuit is held in an off state by the second control unit when the first power supply voltage supply unit is off-controlled by the first control unit.   The semiconductor device according to claim 1, wherein a leakage current of the low-leakage MOS transistor is 1/10 or less of a leakage current of a MOS transistor included in the peripheral circuit. A latch circuit for electrically holding 1-bit data in the form of a voltage;
A write circuit for writing data to the latch circuit;
A first switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the write circuit;
A read circuit for reading data from the latch circuit;
A second switch circuit including at least one MOS transistor for connecting or separating the latch circuit and the readout circuit;
A first transfer gate which is connected in series to the first switch circuit and includes a MOS transistor which selects the latch circuit in response to a write activation signal supplied in response to an address signal;
A first power supply voltage supply unit for supplying a first power supply voltage to the write circuit and the read circuit;
A second power supply voltage supply unit for supplying a second power supply voltage to the latch circuit;
A first control unit for controlling on / off of the first power supply voltage supply unit independently of the second power supply voltage supply unit;
A second control unit for controlling on / off of the first and second switch circuits in conjunction with on / off of the first power supply voltage supply unit;
Have
The MOS transistor included in the latch circuit and the first and second switch circuits is a low-leakage MOS transistor having a leakage current smaller than that of the MOS transistor included in the write circuit, the read circuit, and the first transfer gate. Consisting of
A semiconductor memory in which the first and second switch circuits are held off by the second control unit when the first power supply voltage supply unit is off-controlled by the first control unit apparatus.   4. The semiconductor memory device according to claim 3, wherein a leakage current of the low-leakage MOS transistor is 1/10 or less of a leakage current of a MOS transistor included in the write circuit and the read circuit. 5. The semiconductor memory device according to claim 3, wherein the first switch circuit and the first transfer gate share at least one MOS transistor. First and second data storage nodes for electrically holding 1-bit data in the form of two types of voltages having opposite logic levels, and the first and second data storage nodes A latch circuit including first and second MOS transistors respectively connected between a first voltage and a reference voltage;
A switch circuit including at least one MOS transistor for connecting or separating the latch circuit with respect to a peripheral circuit of the latch circuit;
A transfer gate including a MOS transistor connected in series to the switch circuit and selecting the latch circuit in response to an activation signal supplied in response to an address signal;
Have
A second power supply voltage independent of the first power supply voltage supplied to the peripheral circuits of the latch circuit is supplied to the latch circuit;
The switch circuit is turned on / off in conjunction with the turning on / off of the first power supply voltage to the peripheral circuits of the latch circuit,
The MOS transistors included in the latch circuit and the switch circuit are configured by low leakage type MOS transistors having a leakage current smaller than those of the peripheral circuits of the latch circuit and the MOS transistors included in the transfer gate,
A semiconductor memory cell in which an off state of the switch circuit is held when the supply of the first power supply voltage to a peripheral circuit of the latch circuit is in an off state.   The semiconductor memory cell according to claim 6, wherein a leakage current of the low-leakage MOS transistor is 1/10 or less of a leakage current of a MOS transistor included in a peripheral circuit of the latch circuit. The latch circuit is
A first terminal connected to the first data storage node, a second terminal connected to a power supply voltage terminal of a reference potential, and a control terminal connected to the second data storage node A low-leakage NMOS transistor;
A first terminal connected to the second data storage node, a second terminal connected to the power supply voltage terminal of the reference potential, and a control terminal connected to the first data storage node; Low-leakage NMOS transistors,
The semiconductor memory cell according to claim 6, comprising: The latch circuit is
A first terminal is connected to the first data storage node, a second terminal is connected to a power supply voltage terminal of the second power supply voltage supply unit, and a control terminal is connected to the second data storage node. A first low-leakage PMOS transistor connected;
A first terminal is connected to the second data storage node, a second terminal is connected to a power supply voltage terminal of the second power supply voltage supply unit, and a control terminal is connected to the first data storage node. A second low-leakage PMOS transistor connected;
The semiconductor memory cell according to claim 8, comprising: The latch circuit is
A first resistance element having a first terminal connected to the first data storage node and a second terminal connected to a power supply voltage terminal of the second power supply voltage supply;
A second resistance element having a first terminal connected to the second data storage node and a second terminal connected to a power supply voltage terminal of the second power supply voltage supply unit;
The semiconductor memory cell according to claim 8, comprising: First and second data storage nodes for electrically holding 1-bit data in the form of two types of voltages having opposite logic levels, and the first and second data storage nodes A latch circuit including first and second MOS transistors respectively connected between a first voltage and a reference voltage;
A first switch circuit for connecting or separating the first data storage node with respect to a first write bit line;
A second switch circuit for connecting or separating the second data storage node with respect to a second write bit line;
An output circuit for outputting a voltage read from the latch circuit to a read bit line;
A first transfer gate which is connected in series to the first switch circuit and includes a MOS transistor which selects the latch circuit in response to a write activation signal supplied in response to an address signal;
A second transfer gate including a MOS transistor connected in series to the second switch circuit and selecting the latch circuit in response to a write activation signal supplied in response to an address signal;
Have
The input terminal of the output circuit is connected to the first or second data storage node of the latch circuit via one of the first or second switch circuit,
A second power supply voltage independent of the first power supply voltage supplied to the output circuit is supplied to the latch circuit;
The first and second switch circuits are turned on / off in conjunction with turning on / off the first power supply voltage with respect to the output circuit,
The MOS transistors included in the latch circuit and the first and second switch circuits are low-leakage MOS transistors having a smaller leakage current than the MOS transistors included in the output circuit and the first and second transfer gates. Configured,
A semiconductor memory cell in which an off state of the first and second switch circuits is maintained when supply of the first power supply voltage to the output circuit is in an off state.   The semiconductor memory cell according to claim 11, wherein a leakage current of the low-leakage MOS transistor is 1/10 or less of a leakage current of a MOS transistor included in the output circuit.

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