Nothing Special   »   [go: up one dir, main page]

JP4873901B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP4873901B2
JP4873901B2 JP2005233182A JP2005233182A JP4873901B2 JP 4873901 B2 JP4873901 B2 JP 4873901B2 JP 2005233182 A JP2005233182 A JP 2005233182A JP 2005233182 A JP2005233182 A JP 2005233182A JP 4873901 B2 JP4873901 B2 JP 4873901B2
Authority
JP
Japan
Prior art keywords
wiring pattern
metal wiring
semiconductor device
metal
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005233182A
Other languages
Japanese (ja)
Other versions
JP2006121042A (en
Inventor
恵一郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2005233182A priority Critical patent/JP4873901B2/en
Publication of JP2006121042A publication Critical patent/JP2006121042A/en
Application granted granted Critical
Publication of JP4873901B2 publication Critical patent/JP4873901B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年の電子機器の高性能化、小型化の流れの中、半導体装置の高密度、高機能化が一層求められている。半導体装置を搭載したモジュールにおいても、高密度、高機能化への対応が要求されている。半導体装置を高密度に実装するために、両面回路基板や多層回路基板の適用が進展されつつある。   In recent years, with the trend toward higher performance and smaller size of electronic devices, there is a further demand for higher density and higher functionality of semiconductor devices. Modules equipped with semiconductor devices are also required to support high density and high functionality. In order to mount semiconductor devices with high density, application of double-sided circuit boards and multilayer circuit boards is being developed.

例えば、半導体チップに導電バンプを形成し、フリップチップ接続時の加熱により溶融可能な熱硬化樹脂で前記バンプ形成部分が塗布する。上記半導体装置の実装方法は前記バンプとプリント配線板の電極が対向するように位置合わせする。この時、プリント配線板上の金属配線パターン電極部はエッチング等により電気絶縁樹脂が剥離され、金属が露出している。次に、上記プリント配線板上に上記半導体装置を搭載し加圧しながら加熱することによって、バンプによるフリップチップ接続と熱硬化性樹脂層のゲル化を同時に行う(例えば、特許文献1参照。)。   For example, conductive bumps are formed on a semiconductor chip, and the bump forming portion is coated with a thermosetting resin that can be melted by heating at the time of flip chip connection. In the mounting method of the semiconductor device, the bumps and the printed wiring board are positioned so as to face each other. At this time, the metal wiring pattern electrode portion on the printed wiring board has the electrically insulating resin peeled off by etching or the like, and the metal is exposed. Next, the semiconductor device is mounted on the printed wiring board and heated while being pressed, whereby flip chip connection by bumps and gelation of the thermosetting resin layer are performed simultaneously (for example, see Patent Document 1).

特開平11−307586号公報JP-A-11-307586

しかしながら、従来の方法では予め半導体装置のバンプ形成部分が加熱により溶融可能な熱硬化樹脂で被覆する必要があるので、製造工程が複雑になるという問題を有していた。また、前記バンプに前記熱硬化性樹脂を介して前記プリント配線板電極部へ加圧しているため、熱硬化性樹脂がバンプとプリント配線板電極部間に局所的に介在してしまい接続の信頼性を低下させていた。したがって、本発明は、大幅に簡易な工程が可能で、かつ薄型化が可能な半導体装置および半導体装置の製造方法を提供することを目的とするものである。   However, the conventional method has a problem that the manufacturing process is complicated because the bump forming portion of the semiconductor device needs to be coated with a thermosetting resin that can be melted by heating. Further, since the printed wiring board electrode part is pressed through the thermosetting resin on the bumps, the thermosetting resin is locally interposed between the bumps and the printed wiring board electrode part, so that the connection reliability is ensured. Had reduced sex. Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device which can be significantly simplified and can be thinned.

本発明の半導体装置の製造方法は、電子部品に設けられた導電性バンプと、前記導電性バンプの厚さより薄く、金属配線パターンの全面を被覆するソルダーレジストとを対向配置する工程と、前記導電性バンプを前記ソルダーレジストに接触させ、前記ソルダーレジストに熱、荷重、及び超音波を印加する工程と、前記導電性バンプを押し込み、前記ソルダーレジストの前記導電性バンプと接触する部分を排除して、前記金属配線パターンの一部を露出する工程と、前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程とを備えることを特徴とする。  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a step of opposingly arranging a conductive bump provided on an electronic component; and a solder resist that is thinner than the conductive bump and covers the entire surface of a metal wiring pattern. And contacting the solder resist with the solder resist, applying heat, load, and ultrasonic waves to the solder resist, pressing the conductive bump, and eliminating the portion of the solder resist that contacts the conductive bump. A step of exposing a part of the metal wiring pattern; and a part of the metal wiring pattern and the metal atoms of the conductive bump are directly bonded to each other; And a step of electrically joining the two.

また、前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程の後、前記金属配線パターンの一部と前記導電性バンプとが接合された部分をアンダーフィル封止する工程を備えることを特徴とする。Further, after the step of directly bonding a part of the metal wiring pattern and each metal atom of the conductive bump, and electrically connecting the part of the metal wiring pattern and the conductive bump, A step of underfill sealing a portion where a part of the metal wiring pattern and the conductive bump are joined is provided.

本発明の半導体装置の製造方法により予め樹脂によって電気絶縁されている金属配線パターンの電極部分をエッチング等により露出させる工程が無くなり、大幅に簡易な工程で半導体装置を製造することが可能である。 According to the method for manufacturing a semiconductor device of the present invention, the step of exposing the electrode portion of the metal wiring pattern that has been electrically insulated in advance by resin is eliminated, and the semiconductor device can be manufactured by a significantly simpler process.

また、接合時に周波数40KHz〜60KHzで振幅3μm〜5μmの超音波を0.1sec〜0.5sec印加することにより露出した半導体装置の導電性バンプおよび基板の電極部表面にある1μm〜2μmの凹凸が無くなり電極接続部金属の真面が現れ、金属の原子同士が直接接合するため、従来の熱と荷重を印加しただけでは得られない接続の信頼性を得ることができる。 In addition, the conductive bumps of the semiconductor device exposed by applying ultrasonic waves having a frequency of 40 KHz to 60 KHz and an amplitude of 3 μm to 5 μm at the time of bonding for 0.1 sec to 0.5 sec and unevenness of 1 μm to 2 μm on the surface of the electrode part of the substrate Since the metal surface of the electrode connection portion disappears and the metal atoms are directly bonded to each other, it is possible to obtain connection reliability that cannot be obtained only by applying conventional heat and load.

本発明の半導体装置において、半導体チップの導電性バンプと金属配線パターンの全面を被覆する電気絶縁樹脂とを対向させてフェイスダウンによって実装するフリップチップ接続するものである。図1は本発明の実施の形態の一例を係る半導体装置製造方法を示す製造工程図であり、図3は、本発明の好ましい実施態様にかかる半導体装置の実装構造模式図である。 In the semiconductor device of the present invention, the flip-chip connection is performed in which the conductive bumps of the semiconductor chip and the electrically insulating resin covering the entire surface of the metal wiring pattern face each other and are mounted face down. FIG. 1 is a manufacturing process diagram showing a semiconductor device manufacturing method according to an example of an embodiment of the present invention, and FIG. 3 is a schematic diagram of a semiconductor device mounting structure according to a preferred embodiment of the present invention.

フリップチップ接続では、まず、半導体チップのパッド(表面電極)側に導電性バンプを形成し、半導体チップと電気絶縁樹脂によって電気絶縁されている金属配線パターンが形成されているチップ支持基板とを対向させた後、半導体チップの導電性バンプと金属配線パターンの電極部とを位置合わせし、半導体チップを搭載する。その後、チップ裏面から熱及び荷重及び超音波を印加することにより、電気絶縁樹脂によって電気絶縁されている電極部を露出させ、導電性バンプと支持基板の配線電極パターンとを接続するものである。 In flip chip connection, first, conductive bumps are formed on the pad (surface electrode) side of a semiconductor chip, and the semiconductor chip and a chip support substrate on which a metal wiring pattern electrically insulated by an electrical insulating resin is formed are opposed to each other. Thereafter, the conductive bumps of the semiconductor chip and the electrode portions of the metal wiring pattern are aligned, and the semiconductor chip is mounted. Thereafter, heat, load and ultrasonic waves are applied from the back surface of the chip to expose the electrode part electrically insulated by the electrically insulating resin and to connect the conductive bump and the wiring electrode pattern of the support substrate .

本発明の好ましい実施態様においては、電子部品が、集積回路およびチップ部品を含んでいる。本発明のさらに好ましい実施態様においては、金属が、銅、アルミニウム、銀、金、白金およびパラジウムからなる群より選ばれる金属によって構成されている。本発明のさらに好ましい実施態様においては、金属が、銅またはアルミニウムによって構成されている。   In a preferred embodiment of the present invention, the electronic component includes an integrated circuit and a chip component. In a further preferred embodiment of the present invention, the metal is constituted by a metal selected from the group consisting of copper, aluminum, silver, gold, platinum and palladium. In a further preferred embodiment of the present invention, the metal is constituted by copper or aluminum.

本発明のさらに好ましい実施態様においては、電気絶縁樹脂が、ポリエチレン(PE)、ポリプロピレン(PP)、ポリスチレン(PS)、アクリロニトリル/スチレン樹脂(AS)、アクリロニトリル/ブタジエン/スチレン樹脂(ABS)、メタクリル樹脂(PMMA)、塩化ビニル(PVC)、ポリアミド(PA)、ポリアセタール(POM)、超高分子量ポリエチレン(UHPE)、ポリブチレンテレフタレート(PBT)、GF強化ポリエチレンテレフタレート(GF―PET)、ポリメチルペンテン(TPX)、ポリカーボネイト(PC)、変性ポリフェニレンエーテル(PPE)、ポリフェニレンサルファイド(PPS)、ポリエーテルエーテルケトン(PEEK)、液晶ポリマー(LCP)、ポリテトラフロロエチレン(PTFE)、ポリエーテルイミド(PEI)、ポリアリレート(PAR)、ポリサルフォン(PSF)、ポリエーテルサルフォン(PES)、ポリアミドイミド(PAI)からなる群より選ばれる熱可塑性樹脂によって構成されている。本発明のさらに好ましい実施態様においては、樹脂がフィラーを含んでいる。本発明のさらに好ましい実施態様によれば、樹脂に、フィラーを添加することにより、機械的性質、熱伝導性、熱膨張率、コストなどを考慮して、樹脂の材料を選択することができる。 In a further preferred embodiment of the present invention, the electrically insulating resin is polyethylene (PE), polypropylene (PP), polystyrene (PS), acrylonitrile / styrene resin (AS), acrylonitrile / butadiene / styrene resin (ABS), methacrylic resin. (PMMA), vinyl chloride (PVC), polyamide (PA), polyacetal (POM), ultra high molecular weight polyethylene (UHPE), polybutylene terephthalate (PBT), GF reinforced polyethylene terephthalate (GF-PET), polymethylpentene (TPX) ), Polycarbonate (PC), modified polyphenylene ether (PPE), polyphenylene sulfide (PPS), polyether ether ketone (PEEK), liquid crystal polymer (LCP), polytetrafluoroethylene (P FE), polyetherimide (PEI), polyarylate (PAR), polysulfone (PSF), polyether sulfone (PES), is constituted by a thermoplastic resin selected from the group consisting of polyamide-imide (PAI). In a further preferred embodiment of the present invention, the resin contains a filler. According to a further preferred embodiment of the present invention, a resin material can be selected in consideration of mechanical properties, thermal conductivity, coefficient of thermal expansion, cost, etc. by adding a filler to the resin.

本発明のさらに好ましい実施態様においては、電気絶縁樹脂がソルダーレジスト材(エポキシ系、アクリル系、ウレンタン系樹脂)によって構成されている。 In a further preferred embodiment of the present invention, the electrically insulating resin is composed of a solder resist material (epoxy-based, acrylic-based, urethane-based resin).

本発明のさらに好ましい実施態様においては、電気絶縁樹脂がフリップチップ接続時の加熱により溶融可能な熱硬化樹脂によって構成されている。 In a further preferred embodiment of the present invention, the electrically insulating resin is composed of a thermosetting resin that can be melted by heating at the time of flip chip connection.

以下、添付図面に基づいて、本発明の好ましい実施態様につき、詳細に説明を加える。図3は、本発明の好ましい実施態様にかかる半導体装置の実装構造模式図である。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 3 is a schematic diagram of a mounting structure of a semiconductor device according to a preferred embodiment of the present invention.

図3に示されるように、まず、電気絶縁樹脂3上に金属配線パターン4を形成し、金属配線パターン4上を電気絶縁樹脂6で全面被覆した支持基板に、電子部品である集積回路1を位置決めされた所定の金属配線パターン4の電極部と対向させる。ここに、電子部品は、支持基板の電気絶縁樹脂6で被覆された電極部と接合するわけで、電極部上にある電気絶縁樹脂6を一部排除する必要がある。 As shown in FIG. 3, first, the metal wiring pattern 4 is formed on the electrical insulating resin 3, and the integrated circuit 1 that is an electronic component is mounted on the support substrate that is entirely covered with the electrical insulating resin 6. , to face the electrode portion of the predetermined metal wiring pattern 4 which is positioned. Here, the electronic component is joined to the electrode portion covered with the electrical insulating resin 6 of the support substrate, and it is necessary to partially remove the electrical insulating resin 6 on the electrode portion .

図4に示されるように、集積回路1がフリップチップボンデイング装置のヘッド5に吸着され熱及び荷重及び超音波振動により所定の電極部上にある電気絶縁樹脂6を排除し、導電性バンプ2が金属配線パターン4と接合または接触する。本実施態様によれば、電気絶縁樹脂6に熱及び荷重及び、周波数40KHz〜60KHzで振幅3μm〜5μmの超音波を0.1sec〜0.5sec印加することにより、集積回路1の導電性バンプ2が電気絶縁樹脂を一部排除し、電極部を露出させ、さらに露出した半導体装置の接合部および支持基板の電極部表面にある1μm〜2μmの凹凸が無くなり電極接続部金属の真面が現れ、金属の原子同士が直接接合することにより、金属配線パターン4の電極部と電気的に接合及び接触させることによって、半導体装置を製造することができるから、簡易な工程で半導体装置を製造することが可能になる。 As shown in FIG. 4, the integrated circuit 1 is adsorbed by the head 5 of the flip chip bonding apparatus, and the electrically insulating resin 6 on the predetermined electrode portion is removed by heat, load and ultrasonic vibration , and the conductive bumps 2 are formed. Join or contact with the metal wiring pattern 4. According to this embodiment, the conductive bump 2 of the integrated circuit 1 is applied to the electrical insulating resin 6 by applying heat and load and ultrasonic waves having a frequency of 40 KHz to 60 KHz and an amplitude of 3 μm to 5 μm for 0.1 sec to 0.5 sec. Eliminates part of the electrically insulating resin, exposes the electrode part, and further eliminates the 1 μm to 2 μm irregularities on the exposed part of the semiconductor device and the surface of the electrode part of the support substrate, and the true surface of the electrode connection part metal appears. Since metal atoms are directly bonded to each other, a semiconductor device can be manufactured by electrically bonding and contacting the electrode portion of the metal wiring pattern 4, and thus a semiconductor device can be manufactured by a simple process. It becomes possible.

これによって、半導体装置の製造工程が簡略化できる。本実施態様によれば、半導体装置を構成している支持基板上に金属配線パターン4が形成された後、金属配線パターン4上に腐食防止及び保護用にソルダーレジストを一括塗布できるため、電極部を除く配線部分に選択的に塗布する工程と比して、大幅に製造工程が簡略化でき低コストで製造可能になる。 Thereby, the manufacturing process of the semiconductor device can be simplified. According to this embodiment, after the metal wiring pattern 4 is formed on the support substrate constituting the semiconductor device, the solder resist can be collectively applied on the metal wiring pattern 4 for corrosion prevention and protection. Compared with the process of selectively applying to the wiring part except for the manufacturing process, the manufacturing process can be greatly simplified and it can be manufactured at low cost.

さらに、本実施態様によれば、金属配線パターンの金属が、銅、アルミニウム、銀、金、白金およびパラジウムからなる群より選ばれる金属によって構成されている場合においても回路パターン形成後、直ちにソルダーレジストを全面塗布するため金属表面の清浄度が非常に高い値で保たれるため、電極部を露出する選択塗布に比して後工程での電子部品実装の接合強度が高く、しかも長期耐久試験における信頼性テスト評価結果も良好である。 Furthermore, according to this embodiment, even when the metal of the metal wiring pattern 4 is composed of a metal selected from the group consisting of copper, aluminum, silver, gold, platinum and palladium, the solder is immediately formed after the circuit pattern is formed. Since the resist is applied over the entire surface, the metal surface is kept at a very high level of cleanliness. Therefore, the bonding strength of electronic component mounting in the subsequent process is higher than that of selective coating that exposes the electrode, and long-term durability testing is performed. The reliability test evaluation results in are also good.

さらに、本実施態様によれば、金属配線パターン形成後、直ちにソルダーレジストを全面塗布するため、電極部を露出する選択塗布の場合に比して、電子部品を実装する前に基板電極の清浄度を高めるためにドライ洗浄工程が必要で無くなり、電子部品実装設備にドライ洗浄装置を導入しなくてすむばかりでなく、工程も短縮化できる。 Furthermore, according to this embodiment, since the solder resist is applied to the entire surface immediately after the metal wiring pattern 4 is formed, the substrate electrode is cleaned before mounting the electronic component as compared with the case of selective application exposing the electrode part. In order to increase the degree, the dry cleaning process is not necessary, and it is not only necessary to introduce a dry cleaning apparatus into the electronic component mounting equipment, but also the process can be shortened.

さらに、本実施態様によれば、電気絶縁樹脂6にポリエチレン(PE)、ポリプロピレン(PP)、ポリスチレン(PS)系の樹脂を用い、電気絶縁樹脂厚みを導電性バンプ2高さと同じにしておけば、導電性バンプが電気絶縁樹脂6に埋没し、回路パターン電極と電気的に接合及び接触させることによって、半導体装置を製造することができるから、アンダーフィル封止工程が不要で、接続信頼性の高い半導体装置を製造することが可能になる。 Furthermore, according to the present embodiment, polyethylene electrically insulating resin 6 (PE), polypropylene (PP), using polystyrene (PS) based resins, if the electrically insulating resin thickness on the conductive bumps 2 height and the same Since the semiconductor device can be manufactured by burying the conductive bumps in the electrically insulating resin 6 and electrically connecting and contacting the circuit pattern electrodes, an underfill sealing step is unnecessary, and connection reliability is improved. A high semiconductor device can be manufactured.

さらに、本実施態様によれば、電気絶縁樹脂に電子部品が電気絶縁樹脂に埋没し、回路パターン電極と電気的に接合及び接触させることによって、半導体装置を製造することができるから、電気絶縁樹脂にフリップチップ接続時の加熱により溶融可能な熱硬化樹脂を用いれば、電気的接続が得られた後に樹脂が硬化し始めるため、硬化時の収縮により接触接合の効果も得ることができる。 Furthermore, according to this embodiment, a semiconductor device can be manufactured by embedding an electronic component in the electrical insulating resin 6 in the electrical insulating resin and electrically joining and contacting the circuit pattern electrode. If a thermosetting resin that can be melted by heating at the time of flip-chip connection is used for the resin 6 , the resin starts to harden after electrical connection is obtained, so that the effect of contact bonding can also be obtained by shrinkage at the time of curing.

本実施態様においては電気絶縁樹脂3として、熱可塑性樹脂が用いられる。これによって、半導体装置の薄型化が実現される。   In this embodiment, a thermoplastic resin is used as the electrical insulating resin 3. As a result, the semiconductor device can be thinned.

本実施態様によれば、半導体装置は、実施例1の半導体装置に、集積回路1Aを内蔵した電気絶縁樹脂3によって構成されており、電気絶縁樹脂3に電子部品が埋没しているから、支持基板上に、金属配線パターンが形成され、金属配線パターン上に、電子部品が搭載されて、封止樹脂によって被覆された従来の電子部品内蔵基板に比して、大幅に薄型化することが可能になる。 According to this embodiment, a semiconductor device, the semiconductor device of Embodiment 1 is constituted by an electrically insulating resin 3 with a built-in integrated circuit 1A, since the electronic component to an electrical insulating resin 3 is buried, the support A metal wiring pattern is formed on the substrate, and electronic components are mounted on the metal wiring pattern , making it possible to significantly reduce the thickness compared to conventional electronic component-embedded substrates covered with sealing resin. become.

以下、本発明の実施例を図面に基づいて詳細に説明する。図5は、本発明のさらに好ましい実施態様にかかる半導体装置の実装構造模式図である。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 5 is a schematic diagram of a mounting structure of a semiconductor device according to a further preferred embodiment of the present invention.

本実施の形態2の半導体装置は、図5に示されるように、実施例1の方法で製造された半導体装置において集積回路1がフリップチップボンデイングされている電極面と反対側面の金属配線パターン4に接する電気絶縁樹脂3は、電気絶縁樹脂3の厚みを導電性バンプ2Aの高さにし、かつ、電気絶縁樹脂3を加熱により溶融可能な樹脂で構成しておく。まず、実施例1の方法で製造された半導体装置において集積回路1がフリップチップボンデイングされている電極面と反対側面の配線パターンに電子部品である集積回路1Aを位置決めされた所定の電極と対向させる。ここに、集積回路1Aの端子は、金属敗戦パターン4の電極部との間にある電気絶縁樹脂3材を介して接合するわけで、電極部上にある電気絶縁樹脂3を一部排除する必要がある。実施例1と同様に集積回路1がフリップチップボンデイングされる時に熱により所定の電極部上にある加熱により溶融可能な樹脂で構成されている電気絶縁樹脂3を軟化させ、次に荷重を印加しながら電気絶縁樹脂3材を一部排除できる。さらに、超音波を印加しながら荷重をかけるため、導電性バンプ2Aと電極部間に局所的に介在している溶融可能な樹脂を完全に排除し、かつ、露出した半導体装置の接合部および支持基板の電極部表面にある1μm〜2μmの凹凸が無くなり電極部の金属の真面が現れ、金属の原子同士が直接接合することにより、導電性バンプ2Aと電極部とが接触または、接合する。 As shown in FIG. 5, the semiconductor device according to the second embodiment has a metal wiring pattern 4 on the side surface opposite to the electrode surface on which the integrated circuit 1 is flip-chip bonded in the semiconductor device manufactured by the method of the first embodiment. The electrical insulating resin 3 in contact with is made up of a resin that can be melted by heating, with the thickness of the electrical insulating resin 3 set to the height of the conductive bumps 2A . First, in the semiconductor device manufactured by the method of the first embodiment, the integrated circuit 1A, which is an electronic component, is opposed to a predetermined predetermined electrode on the wiring pattern opposite to the electrode surface on which the integrated circuit 1 is flip-chip bonded. . Here, the terminal of the integrated circuit 1A is joined to the electrode part of the metal defeat pattern 4 via the electrically insulating resin 3 material, and it is necessary to exclude a part of the electrically insulating resin 3 on the electrode part. There is. As in the first embodiment, when the integrated circuit 1 is flip-chip bonded, the electrical insulating resin 3 made of a resin that can be melted by heating on a predetermined electrode portion is softened by heat, and then a load is applied. However, a part of the three electrically insulating resins can be eliminated. Further, since the load is applied while applying the ultrasonic wave, the meltable resin locally interposed between the conductive bump 2A and the electrode portion is completely eliminated, and the exposed joint portion and support of the semiconductor device are removed. The 1 μm to 2 μm unevenness on the surface of the electrode part of the substrate disappears and the true surface of the metal of the electrode part appears, and the metal bumps are directly bonded to each other, so that the conductive bump 2A and the electrode part are contacted or bonded.

本実施態様においては電気絶縁樹脂3として、熱可塑性樹脂が用いられる。これによって、半導体装置の薄型化が実現される。本実施態様によれば、半導体装置は、集積回路1Aを内蔵した電気絶縁樹脂3と、金属配線パターン4とによって構成されており、電気絶縁樹脂3に電子部品が埋没しているから、支持基板上に、金属配線パターン4が形成され、金属配線パターン4上に、電子部品が搭載されて、封止樹脂によって被覆された従来の電子部品内蔵基板に比して、大幅に薄型化することが可能になる。 In this embodiment, a thermoplastic resin is used as the electrical insulating resin 3. As a result, the semiconductor device can be thinned. According to this embodiment, a semiconductor device, the electrical insulating resin 3 with a built-in integrated circuit 1A, is constituted by a metal wiring pattern 4, since the electronic component to an electrical insulating resin 3 is buried, the support substrate The metal wiring pattern 4 is formed on the metal wiring pattern 4 , and an electronic component is mounted on the metal wiring pattern 4 , so that the thickness can be significantly reduced as compared with a conventional electronic component built-in substrate covered with a sealing resin. It becomes possible.

さらに、本実施態様によれば、電気絶縁樹脂3に熱及び荷重及び超音波振動により、電子部品が埋没させ、金属配線パターン4の電極部と電気的に接合及び接触させることによって、半導体装置を製造することができるから、簡易な工程で、実装密度の高い半導体装置を製造することが可能になる。また、両面実装基板や多層実装基板に必ず必要となるスルーホールを予め製造する必要が無くなり、非常に安価な両面及び多層実装基板を製造できる。さらに、本実施態様によれば、電子部品が電気絶縁樹脂3に埋没し、金属配線パターン4の電極部と電気的に接合及び接触させることによって、半導体装置を製造することができるから、アンダーフィル封止工程が不要で、接続信頼性の高い半導体装置を製造することが可能になる。 Further, according to the present embodiment, the electronic component is buried in the electrical insulating resin 3 by heat, load and ultrasonic vibration, and is electrically joined and contacted with the electrode portion of the metal wiring pattern 4, thereby making the semiconductor device Since it can be manufactured, it becomes possible to manufacture a semiconductor device with a high mounting density by a simple process. Further, it is not necessary to manufacture through holes that are necessary for the double-sided mounting board or the multilayer mounting board in advance, and a very inexpensive double-sided and multilayer mounting board can be manufactured. Furthermore, according to this embodiment, the semiconductor device can be manufactured by burying the electronic component in the electrical insulating resin 3 and electrically joining and contacting the electrode part of the metal wiring pattern 4. It is possible to manufacture a semiconductor device with no connection process and high connection reliability.

さらに、本実施態様によれば、電子部品が電気絶縁樹脂に埋没し、回路パターン電極裏面と電気的に接合及び接触させることによって、半導体装置を製造することができるから、電気絶縁樹脂に加熱により溶融可能な熱可塑樹脂を用いれば、電気的接続が得られた後に樹脂が硬化し始めるため、硬化時の収縮により接触接合の効果も得ることができる。 Furthermore, according to this embodiment, since the electronic component is buried in the electrical insulating resin 3 and electrically joined and brought into contact with the back surface of the circuit pattern electrode, the semiconductor device can be manufactured. If a thermoplastic resin that can be melted by the above is used, the resin begins to harden after electrical connection is obtained, so that the effect of contact bonding can also be obtained by shrinkage during curing.

以下、本発明の実施例を図面に基づいて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図6に示されるように、まず、金属配線パターン4上にレジストで構成された電気絶縁樹脂6を形成した支持基板に、電子部品である集積回路1を位置決めされた所定の金属配線パターン4の電極部と対向させる。ここに、電子部品は、基板の電気絶縁樹脂6で被覆された電極部と接合するわけで、電極部上にある電気絶縁樹脂6を一部排除する必要がある。 As shown in FIG. 6, firstly, the metal on the support substrate formed with the electrical insulating resin 6 formed of on a resist wiring pattern 4, the integrated circuit 1 is an electronic component, a predetermined metal wiring pattern 4 which is positioned It is made to oppose with the electrode part. Here, the electronic component is joined to the electrode portion covered with the electrical insulating resin 6 on the substrate, and it is necessary to partially remove the electrical insulating resin 6 on the electrode portion .

本実施態様によれば、電気絶縁樹脂6に熱及び荷重及び、周波数40KHz〜60KHzで振幅3μm〜5μmの超音波を0.1sec〜0.5sec印加することにより、集積回路1の導電性バンプ2電気絶縁樹脂6を一部排除し、金属配線パターン4の電極部を露出させ、さらに露出した半導体装置の接合部および支持基板の電極部表面にある1μm〜2μmの凹凸が無くなり電極部の金属の真面が現れ、金属の原子同士が直接接合することにより、金属配線パターンの電極部と導電性バンプ2とが電気的に接合及び接触させることによって、半導体装置を製造することができるから、簡易な工程で半導体装置を製造することが可能になる。 According to this embodiment, the conductive bump 2 of the integrated circuit 1 is applied to the electrical insulating resin 6 by applying heat and load and ultrasonic waves having a frequency of 40 KHz to 60 KHz and an amplitude of 3 μm to 5 μm for 0.1 sec to 0.5 sec. there eliminate some electrical insulating resin 6, to expose the electrode portion of the metal wiring patterns 4, further exposed joint and eliminates the unevenness of 1μm~2μm in the electrode portion the surface of the supporting substrate electrode portion of the metal into the semiconductor device The semiconductor device can be manufactured by electrically connecting and contacting the electrode part of the metal wiring pattern and the conductive bump 2 by directly joining metal atoms to each other, and by bringing the metal atoms directly into contact with each other. A semiconductor device can be manufactured with a simple process.

これによって、半導体装置の製造工程が簡略化できる。本実施態様によれば、電気絶縁性樹脂6にレジスト材を用いることにより、半導体装置を構成している支持基板上に金属配線パターン4が形成された後金属配線パターン4上に腐食防止及び保護用にソルダーレジストを一括塗布できるため、電極部を除く配線部分に選択的に塗布する工程と比して、大幅に製造工程が簡略化でき低コストで製造可能になる。 Thereby, the manufacturing process of the semiconductor device can be simplified. According to this embodiment, by using a resist material on the electrically insulating resin 6, after the metal wiring pattern 4 is formed on the supporting substrate constituting the semiconductor device, corrosion and on the metal wiring pattern 4 Since the solder resist can be collectively applied for protection, the manufacturing process can be greatly simplified and can be manufactured at a lower cost than the process of selectively applying to the wiring portion excluding the electrode portion.

さらに、本実施態様によれば、金属配線パターン4の金属が、銅、アルミニウム、銀、金、白金およびパラジウムからなる群より選ばれる金属によって構成されている場合においても金属配線パターン4形成後、直ちにソルダーレジストを全面塗布するため金属表面の清浄度が非常に高い値で保たれるため、電極部を露出する選択塗布に比して後工程での電子部品実装の接合強度が高く、しかも長期耐久試験における信頼性テスト評価結果も良好である。 Furthermore, according to this embodiment, even when the metal of the metal wiring pattern 4 is composed of a metal selected from the group consisting of copper, aluminum, silver, gold, platinum, and palladium, after the metal wiring pattern 4 is formed, Since the solder resist is immediately applied to the entire surface, the cleanliness of the metal surface is kept at a very high value. Therefore, the bonding strength of the electronic component mounting in the subsequent process is higher than the selective application that exposes the electrode part, and it is long-lasting. The reliability test evaluation result in the durability test is also good.

以上、本発明の実施形態及び実施例を図面に沿って説明した。本発明が対象とする半導体装置は、電気絶縁樹脂でコーティングしてある電極に対し、熱及び荷重及び超音波振動を印加して、電極部上にある電気絶縁樹脂を一部排除し電子部品の端子と基板を接合または接触させ、かつ、接合部をアンダーフィル封止または電子部品封止ができる半導体装置製造方法である。 The embodiments and examples of the present invention have been described with reference to the drawings. The semiconductor device targeted by the present invention applies heat, load, and ultrasonic vibration to an electrode coated with an electrical insulating resin to eliminate part of the electrical insulating resin on the electrode portion and A method for manufacturing a semiconductor device in which a terminal and a substrate are bonded or brought into contact with each other, and a bonding portion can be sealed with an underfill or an electronic component.

また、接合または接触方式が、Au−Al、Au−Sn、In−Auによる合金接続の場合、Au−Au、Al−Al、Cu−Cuによる圧着接続の場合、ACF、ACP、NCP、NCFによる圧接接続の場合及びはんだによる溶融接続の場合、全ての接続方法において本発明を限定する要素にはならない。   Also, when the bonding or contact method is an alloy connection by Au-Al, Au-Sn, In-Au, in the case of a crimp connection by Au-Au, Al-Al, Cu-Cu, by ACF, ACP, NCP, NCF In the case of the pressure connection and the fusion connection by solder, the present invention is not limited to all connection methods.

また、接合または接触方式において、電子部品と支持基板の接続時に介在する樹脂が半熱硬化性、熱硬化性又はUV硬化性のものであるか、非導電性ものであるか、導電性のものであるか、その導電粒子の寸法および材質、その粒子組成が金属、金属メッキされた樹脂又は金属粒子、絶縁被覆された金属メッキ樹脂又は金属粒子であるかなどは、本発明を限定する要素にはならない。 In addition, in the bonding or contact method, the resin interposed when the electronic component and the support substrate are connected is semi-thermosetting, thermosetting, UV curable, non-conductive, or conductive. The size and material of the conductive particles, whether the particle composition is a metal, a metal-plated resin or metal particle, an insulating-coated metal-plated resin or metal particle, etc. are factors that limit the present invention. Must not.

本発明は、電気電子装置に用いられる支持基板にフリップチップボンデイング実装するに好適なる半導体装置に利用可能である。 The present invention can be used for a semiconductor device suitable for flip chip bonding mounting on a support substrate used in an electric / electronic device.

本発明の一実施形態に係る半導体装置の製造方法を示す製造工程図である。It is a manufacturing process figure which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 従来例に係る半導体装置の製造方法を示す製造工程図である。It is a manufacturing process figure which shows the manufacturing method of the semiconductor device which concerns on a prior art example. 本発明の実施形態に係る、集積回路を電気絶縁樹脂で被覆された金属配線パターンが形成された支持基板へ対向配置し、電気絶縁樹脂を排除し、金属配線パターン電極部と接合した後の断面図である。The cross-section after the integrated circuit according to the embodiment of the present invention is disposed opposite to the support substrate on which the metal wiring pattern coated with the electrical insulating resin is formed, the electrical insulating resin is excluded, and the metal wiring pattern electrode portion is joined FIG. 本発明の実施形態に係る集積回路と金属配線パターンが形成された支持基板とを対向させた後、集積回路をフリップチップボンデイング装置ヘッドで吸着し、導電性バンプと金属配線パターンとを位置合わせした時の半導体装置製造方法を示す断面図である。After the integrated circuit according to the embodiment of the present invention and the support substrate on which the metal wiring pattern is formed are opposed to each other, the integrated circuit is adsorbed by a flip chip bonding apparatus head, and the conductive bump and the metal wiring pattern are aligned. It is sectional drawing which shows the semiconductor device manufacturing method at the time. 本発明の実施形態に係る集積回路を図1で示した製造方法で接合した半導体装置の基板へ図1で集積回路が実装されている電極部の裏面に集積回路を実装した両面実装を示す断面図である。1 is a cross-sectional view showing a double-sided mounting in which an integrated circuit is mounted on the back surface of an electrode portion on which an integrated circuit is mounted in FIG. 1 on a substrate of a semiconductor device in which the integrated circuit according to the embodiment of the present invention is bonded by the manufacturing method shown in FIG. FIG. 本発明の実施形態に係る、集積回路を金属配線パターンが形成された支持基板へ金属配線パターン電極部のある面と反対方向から接合した後の断面図である。It is sectional drawing after joining the integrated circuit based on embodiment of this invention from the opposite direction to the surface with a metal wiring pattern electrode part to the support substrate in which the metal wiring pattern was formed.

1,1A 集積回路
2,2A 導電性バンプ
3 電気絶縁樹脂
4 金属配線パターン
5 フリップチップボンデイング装置ヘッド
6 電気絶縁樹脂
DESCRIPTION OF SYMBOLS 1,1A Integrated circuit 2,2A Conductive bump 3 Electrical insulation resin 4 Metal wiring pattern 5 Flip chip bonding apparatus head 6 Electrical insulation resin

Claims (1)

電子部品に設けられた導電性バンプと、前記導電性バンプの厚さより薄く、金属配線パターンの全面を被覆するソルダーレジストとを対向配置する工程と、
前記導電性バンプを前記ソルダーレジストに接触させ、前記ソルダーレジストに熱、荷重、及び超音波を印加する工程と、
前記導電性バンプを押し込み、前記ソルダーレジストの前記導電性バンプと接触する部分を排除して、前記金属配線パターンの一部を露出する工程と、
前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記電子部品と前記ソルダーレジストとの間に隙間を有する状態で、かつ前記導電性バンプの一部を前記ソルダーレジストから露出した状態で前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程とを備え、前記金属配線パターンの一部及び前記導電性バンプのそれぞれの金属の原子同士を直接接合し、前記金属配線パターンの一部と前記導電性バンプとを電気的に接合する工程の後、前記金属配線パターンの一部と前記導電性バンプとが接合された部分をアンダーフィル封止または電子部品封止をする工程を備えることを特徴とする半導体装置の製造方法。
A step of opposingly arranging a conductive bump provided on the electronic component and a solder resist that is thinner than the thickness of the conductive bump and covers the entire surface of the metal wiring pattern;
Contacting the conductive bumps with the solder resist and applying heat, load, and ultrasonic waves to the solder resist;
Pushing the conductive bumps, eliminating the portion of the solder resist that contacts the conductive bumps, exposing a part of the metal wiring pattern;
A part of the metal wiring pattern and the metal atoms of the conductive bumps are directly bonded to each other, with a gap between the electronic component and the solder resist, and a part of the conductive bumps. Electrically bonding a part of the metal wiring pattern and the conductive bump while being exposed from the solder resist, and a metal atom of each of the part of the metal wiring pattern and the conductive bump. After the step of directly bonding each other and electrically bonding a part of the metal wiring pattern and the conductive bump, the portion where the part of the metal wiring pattern and the conductive bump are bonded is underfilled. A method for manufacturing a semiconductor device comprising a step of sealing or electronic component sealing .
JP2005233182A 2004-09-21 2005-08-11 Manufacturing method of semiconductor device Expired - Fee Related JP4873901B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005233182A JP4873901B2 (en) 2004-09-21 2005-08-11 Manufacturing method of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004273697 2004-09-21
JP2004273697 2004-09-21
JP2005233182A JP4873901B2 (en) 2004-09-21 2005-08-11 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2006121042A JP2006121042A (en) 2006-05-11
JP4873901B2 true JP4873901B2 (en) 2012-02-08

Family

ID=36538595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005233182A Expired - Fee Related JP4873901B2 (en) 2004-09-21 2005-08-11 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4873901B2 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11150150A (en) * 1997-11-18 1999-06-02 Sumitomo Bakelite Co Ltd Board for semiconductor mounting and its manufacture and mounting method for semiconductor chip
JP3119230B2 (en) * 1998-03-03 2000-12-18 日本電気株式会社 Resin film and method for connecting electronic components using the same
JP2000036520A (en) * 1998-05-15 2000-02-02 Nec Corp Method for mounting flip chip and device therefor
JP3914332B2 (en) * 1998-05-18 2007-05-16 松下電器産業株式会社 Manufacturing method of semiconductor device
JP4097378B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
JP2003188210A (en) * 2001-12-18 2003-07-04 Mitsubishi Electric Corp Semiconductor device
JP3533665B1 (en) * 2002-12-17 2004-05-31 オムロン株式会社 A method for manufacturing an electronic component module and a method for manufacturing a data carrier capable of reading electromagnetic waves.

Also Published As

Publication number Publication date
JP2006121042A (en) 2006-05-11

Similar Documents

Publication Publication Date Title
JP2500462B2 (en) Inspection connector and manufacturing method thereof
EP1763295A2 (en) Electronic component embedded board and its manufacturing method
JP2001177045A (en) Semiconductor device and method for manufacturing the same
CN101128087B (en) circuit substrate and semiconductor device
JP4494785B2 (en) Anisotropic conductive adhesive film, method for producing the same, and semiconductor device
JP2000277649A (en) Semiconductor and manufacture of the same
JP2004128056A (en) Semiconductor device and its manufacturing method
JP4967467B2 (en) Flexible wiring board bonding method and wiring board
JPH1116949A (en) Acf-bonding structure
JP4873901B2 (en) Manufacturing method of semiconductor device
JP2005311293A (en) Semiconductor chip, semiconductor device, manufacturing method for the semiconductor device, and electronic device
JP4019328B2 (en) Electrode connection method
JP3743716B2 (en) Flexible wiring board and semiconductor element mounting method
JP3897278B2 (en) Manufacturing method of flexible wiring board
JP2008235007A (en) Anisotropic conductive sheet, wiring-board body connected by anisotropic conductive sheet, wiring-board connector, and wiring-board module
JP2007110095A (en) Substrate with built-in electronic component and method for manufacturing same
TWI838384B (en) Methods and devices for connecting electronic components to mounting substrates
JP4172433B2 (en) Substrate connecting member, three-dimensional connecting structure using the same, and manufacturing method of three-dimensional connecting structure
JP5590097B2 (en) Component built-in wiring board
JP2003258435A (en) Sheet material for wiring board and multilayered wiring board
JP2006261177A (en) Semiconductor device and its manufacturing process and packaging structure
JP2004127612A (en) Conductive fine particle, interconnecting method of electrode terminals, and conductive connection structure
JP3337922B2 (en) Semiconductor device and manufacturing method thereof
JP2004119464A (en) Wiring board with solder bump and method for manufacturing same
JP3383774B2 (en) Semiconductor element mounting method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080408

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091105

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091113

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100830

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100907

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101026

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20101124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110202

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20110222

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20110325

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111020

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111122

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141202

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4873901

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees