JP4870806B2 - Transimpedance amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve controlling in short response time in a transimpedance amplifier that performs gain control and offset control. <P>SOLUTION: A transimpedance amplifier has: a transimpedance amplifier core circuit 1 to which a current signal is input; a transimpedance amplifier core circuit 2 having the same structure as the core circuit 1 and whose input is in an open state; an average value detection circuit 5 that detects a voltage difference of the average values for output signals of the core circuits 1 and 2; and a single phase differential converting circuit 3 that converts the output signal of the core circuit 1 into a differential signal. The core circuits 1 and 2 have gain control circuits 9 and 11 that change a value of feedback resistance Rf depending on detection results of the average value detection circuit 5. The single phase differential converting circuit 3 has an offset control circuit that cancels the offset of the differential signal depending on the detection results of the average value detection circuit 5. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a transimpedance amplifier that converts an input current signal obtained in a light receiving element into a voltage signal, and more particularly to a transimpedance amplifier that can realize high sensitivity reception and wide dynamic range reception.

  An optical transmission system that enables high-speed data transmission, and in particular, an optical transmission device of a passive optical network (PON) system, includes an optical receiver circuit that converts an optical signal into an electrical signal. As one example, a transimpedance amplifier (TIA) is used. The TIA has a function of inputting an input current obtained by photoelectrically converting a received optical signal by a light receiving element, converting the input current into a voltage corresponding to an impedance conversion gain proportional to the value of a feedback resistor, and outputting the voltage. This TIA is required to have high sensitivity, a wide input dynamic range, and burst response due to the characteristics of the PON system described below.

  FIG. 9 shows the system configuration of the PON system. In the PON system, a plurality of home side devices (Optical Network Unit: ONU) are connected to one station side device (Optical Line Terminal: OLT), and the connection is made by passive devices such as the optical coupler 100 and the optical fiber 101. Is called. Upstream data from each ONU to the OLT has different optical power when reaching the OLT due to the difference in each path. For this reason, first, a wide dynamic range is required for the TIA used in the OLT optical receiver circuit.

  In general, in TIA, when the input current increases, the output voltage amplitude is saturated and waveform distortion occurs. Conventional TIA employs automatic gain control (AGC) technology in order to achieve both high sensitivity and wide dynamic range characteristics (see Patent Document 1 and Patent Document 2). When the input current increases, the value of the feedback resistance is reduced to reduce the impedance conversion gain, thereby increasing the input overload tolerance, and an output voltage with less distortion is obtained even when a large current is input. Further, when the input current is small, low noise and high sensitivity reception are realized by increasing the gain.

  By the way, in the upstream communication of the PON system, when a time division multiple access (Time Division Multiple Access: TDMA) system in which a unique data transmission time is assigned to each user is used, while a certain ONU is transmitting data (packets) In order to avoid collision, other ONUs cannot send packets. At this time, the time between packets is used for setup of an optical receiver, clock extraction, and the like. As shown in FIG. 10, a specific bit called a preamble bit 201 is provided at the beginning of the packet 200. The OLT uses this preamble bit 201 to synchronize the packet 200.

  In order to increase the transmission efficiency, the packet 200 must be synchronized with the short preamble bit 201, and an optical receiver circuit capable of instantaneously switching the gain with the short preamble bit 201 is required. For this reason, the TIA used in the OLT optical receiver circuit is required to have an instantaneous response in addition to the wide dynamic range described above.

  In TIA, in order to optimize the linear operation range of the amplifier, a technique is used in which the output offset amount of the differential signal is set to zero by automatic offset control (AOC) (see Patent Document 1). . By using AOC, the output offset of the differential signal becomes zero even if the input signal strength changes, so that not only the connection with the amplifier in the subsequent stage is easy, but also the signal after the offset control has a low distortion and gain. There is a feature that can be secured.

  FIG. 11 shows a configuration of an OLT optical receiving circuit having a TIA with an AGC function. In FIG. 11, 100 is a light receiving element that receives an input optical signal and converts it into a current signal IN, and 101 is a voltage signal that simultaneously amplifies the current signal IN output from the light receiving element 100 with a gain proportional to the value of the feedback resistor Rf. A transimpedance amplifier core circuit for converting the signal into a reference voltage generation circuit, a single phase-differential conversion circuit for converting a single phase output signal output from the transimpedance amplifier core circuit 101 into a differential signal, and 104 An output buffer 105 for outputting the signal converted by the single-phase-to-differential conversion circuit 103 as differential output signals OUTP and OUTN to the outside, 105 is an average value of the output signal of the transimpedance amplifier core circuit 101 and the reference voltage generation circuit 102 Average value that outputs a voltage difference from the average value of the output reference voltage as detection signal VC Circuit output, 106 is a coefficient multiplier which outputs a voltage obtained by multiplying a predetermined coefficient to the detection signal VC output from the average value detecting circuit 105 as a gain control signal VG.

The transimpedance amplifier core circuit 101 includes an amplifier 107 and a gain control circuit 108 that changes the value of a feedback resistor Rf that connects the signal output terminal and the signal input terminal of the amplifier 107 in accordance with the gain control signal VG. The
In the TIA shown in FIG. 11, the output amplitude of the transimpedance amplifier core circuit 101 is monitored, and a gain control signal VG for setting the gain of the amplifier 107 to a desired value is fed back to the transimpedance amplifier core circuit 101. , TIA gain is controlled.

  FIG. 12 shows the configuration of an OLT optical receiver circuit having a TIA with an AOC function. In FIG. 12, 100 is a light receiving element, 101a is a transimpedance amplifier core circuit, 102 is a reference voltage generation circuit, 103 is a single phase-differential conversion circuit, 104 is an output buffer, 109 is an average value detection circuit, and 110 is an average value. A coefficient multiplier 111 outputs a voltage obtained by multiplying the detection signal VC output from the detection circuit 109 by a predetermined coefficient as an offset control signal VO. 111 is an average of the current signal IN from the light receiving element 100 according to the offset control signal VO. This is a current control circuit for diverting a value current to the ground side. In the transimpedance amplifier core circuit 101a, the feedback resistor Rf is a fixed resistor.

In the TIA shown in FIG. 12, the output voltage (Vref) of the reference voltage generation circuit and the output voltage (Vcore) of the transimpedance amplifier core circuit 101a are monitored, and their offset voltages, that is, (Vcore−Vref) are set to zero. By feeding back an offset control signal VO to the transimpedance amplifier core circuit 101a, the output offset voltage of the TIA is controlled.
Furthermore, the configuration of the optical receiver circuit of the OLT having the TIA having both the AGC function and the AOC function is as shown in FIG.

JP 2001-127560 A JP 2006-050145 A

  In the TIA shown in FIGS. 11 to 13, feedback control is used to perform highly accurate AGC / AOC. However, in order to perform stable control, the feedback time constant is increased and the response time is increased. There is a need. However, increasing the feedback time constant is not suitable for applications such as PON systems that require synchronization with a short preamble length.

  Moreover, in an amplifier that performs gain control by feedback control, such as the amplifier used in the transimpedance amplifier core circuit 101, there is a trade-off relationship between the response time of the feedback loop and the low-frequency cutoff frequency of the amplifier, as shown in FIG. is there. The response time means a response time from when reception of the leading portion of the packet data starts until a TIA gain and an output offset amount reach appropriate values. Therefore, in TIA for PON system applications, it is necessary to make a response in as short a time as possible, and therefore it has been necessary to set a loop response time that satisfies both the response time and the low-frequency cutoff frequency. However, when NRZ or the like is used as a transmission line code, there is a problem of the same code continuous section (Consecutive identical digit: CID) in which “1” and “0” are continuously transmitted in a bit string. This is because, particularly when the AGC or AOC performs feedback control excessively when receiving the CID, there is a possibility that the head portion of the packet data may be missed. On the other hand, although it is possible to give high tolerance to a long CID by lowering the low-frequency cutoff frequency of the TIA, the response time becomes longer from the relationship of FIG.

Further, when both AGC and AOC control are performed as in the TIA shown in FIG. 13, the AGC loop and the AOC loop interfere with each other as shown in FIGS. 15 (A) to 15 (C). There is. As a result, an extra time is required until each feedback loop is stabilized, which causes a long response time.
Therefore, the conventional TIA for PON system use cannot adopt the configuration shown in FIG. 13, and only one of AGC and AOC is controlled.

  The present invention has been made to solve the above-described problems, and an object thereof is to realize control with a short response time in a transimpedance amplifier that performs both AGC and AOC control.

  The transimpedance amplifier of the present invention is the same as the first transimpedance amplifier core circuit that amplifies an input current signal with a gain proportional to the value of the feedback resistor and simultaneously converts it into a voltage signal. A second transimpedance amplifier core circuit having an input in an open state, an average value of output signals of the first transimpedance amplifier core circuit, and an average value of output signals of the second transimpedance amplifier core circuit; An average value detection circuit for detecting a voltage difference, an output signal of the first transimpedance amplifier core circuit, and an output signal of the second transimpedance amplifier core circuit as inputs, and the first transimpedance amplifier core circuit Single output signal is converted to differential signal. -A differential conversion circuit, wherein the first and second transimpedance amplifier core circuits are respectively connected to the first and second transimpedance amplifier core circuits according to the detection result of the average value detection circuit. A gain control circuit for changing a value of a feedback resistor, wherein the single-phase-to-differential conversion circuit is configured so that an offset of the differential signal becomes zero according to a detection result of the average value detection circuit; An offset control circuit for controlling a DC voltage of a signal is provided, feedback control is used as the gain control method, and feedforward control is used as the offset control method.

The transimpedance amplifier according to an embodiment of the present invention is further provided between the average value detection circuit and the gain control circuit, and a voltage output from the average value detection circuit is multiplied by a first coefficient. The first coefficient multiplier that outputs the obtained voltage as a gain control signal to the gain control circuit, and is provided between the average value detection circuit and the offset control circuit, and the voltage output from the average value detection circuit And a second coefficient multiplier that outputs the voltage multiplied by the second coefficient to the offset control circuit as an offset control signal.
In one configuration example of the transimpedance amplifier according to the present invention, the first and second transimpedance amplifier core circuits include a grounded emitter circuit connected to a signal input terminal and a voltage output from the grounded emitter circuit. An emitter follower circuit that amplifies a signal and outputs the amplified signal to a signal output terminal, the feedback resistor having one end connected to the signal output terminal and the other end connected to the signal input terminal, and the gain control circuit It is characterized by this.
Further, in one configuration example of the transimpedance amplifier of the present invention, the average value detection circuit is configured to use an operational amplifier that outputs a detection result and an average voltage of an output signal of the first transimpedance amplifier core circuit as a non-inversion of the operational amplifier. A first average voltage detecting means for applying to the input terminal; and a second average voltage detecting means for supplying the average voltage of the output signal of the second transimpedance amplifier core circuit to the inverting input terminal of the operational amplifier. It is what.

Further, in one configuration example of the transimpedance amplifier according to the present invention, the single-phase-to-differential conversion circuit includes an output signal of the first transimpedance amplifier core circuit and an output signal of the second transimpedance amplifier core circuit. , A pair of load resistors whose one end is connected to the output terminal of the first transistor pair, and an output of the first transistor pair , And a pair of emitter follower circuits that output the differential signal, a first current source that supplies a constant current to the first transistor pair, and the offset control circuit. The circuit includes a second transistor pair for controlling the amount of current flowing through the load resistor according to the detection result of the average value detection circuit, and the second transistor. It is characterized in that the data pair is composed of a second current source for supplying a constant current.
Further, in one configuration example of the transimpedance amplifier of the present invention, the first and second transimpedance amplifier core circuits are configured such that the frequency bands of the first and second transimpedance amplifier core circuits are the transmission of the input current signal, respectively. A frequency band control circuit is provided that changes the value of the feedback resistance of the first and second transimpedance amplifier core circuits so as to be in a band according to the speed.

  According to the present invention, an average value of a voltage difference between an average output voltage of a first transimpedance amplifier core circuit having a current signal as an input and an average output voltage of a second transimpedance amplifier core circuit having an input in an open state is detected. By detecting with the circuit, the output signal of the average value detection circuit becomes a signal indicating the first TIA core output voltage amplitude information or the information of the input offset voltage of the single phase-differential conversion circuit. In the present invention, the feedback control is used to perform the gain control, and the feedforward control is used to perform the offset control, thereby improving the interference between the gain control loop and the offset control loop. In a transimpedance amplifier that performs both gain control and offset control, control with a short response time can be realized.

  In the present invention, a voltage that is provided between the average value detection circuit and the gain control circuit and is obtained by multiplying the voltage output from the average value detection circuit by the first coefficient is output to the gain control circuit as a gain control signal. Provided between the first coefficient multiplier, the average value detection circuit, and the offset control circuit, a voltage obtained by multiplying the voltage output from the average value detection circuit by the second coefficient is used as an offset control signal in the offset control circuit. By providing the second coefficient multiplier for output, control signals used for gain control and offset control can be adjusted separately, so that gain control and offset control can be performed more appropriately and at high speed. .

  In the present invention, the first and second transimpedance amplifier core circuits are each provided with a frequency band control circuit so that the frequency band of the first transimpedance amplifier core circuit is adjusted to an appropriate band. be able to. Since the input current signal is obtained from a light receiving element such as a photodiode, performing frequency band control according to the transmission speed of the input current signal results in performing frequency band control according to the transmission speed of the input optical signal. Become.

It is a block diagram which shows the structure of the optical receiver circuit of the station side apparatus which concerns on the 1st Embodiment of this invention. 1 is a circuit diagram showing a configuration of a transimpedance amplifier core circuit according to a first embodiment of the present invention. FIG. 1 is a circuit diagram showing a configuration of a single phase-differential conversion circuit according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows another structure of the single phase-differential conversion circuit which concerns on the 1st Embodiment of this invention. 1 is a circuit diagram showing a configuration of an average value detection circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the optical receiver circuit of the station side apparatus which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the transimpedance amplifier core circuit based on the 2nd Embodiment of this invention. It is a figure which shows the change of the frequency band of the transimpedance amplifier core circuit by the change of a feedback resistance. It is a block diagram which shows the structure of a passive optical network system. It is a figure which shows the packet data from the home side apparatus which arrives at a station side apparatus. It is a block diagram which shows the structure of the optical receiver circuit of the station side apparatus which has a transimpedance amplifier with an automatic gain control function. It is a block diagram which shows the structure of the optical receiver circuit of the station | side apparatus which has a transimpedance amplifier with an automatic offset control function. It is a block diagram which shows the structure of the optical receiver circuit of the station | side apparatus which has a transimpedance amplifier with an automatic gain control function and an automatic offset control function. It is a figure which shows the relationship between the feedback loop response time and the low cut off frequency in the amplifier of feedback control. It is a figure for demonstrating lengthening of the response time of a transimpedance amplifier by interference of an AGC loop and an AOC loop.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an optical receiver circuit of the OLT according to the first embodiment of the present invention.
As shown in FIG. 1, the OLT optical receiver circuit includes a light receiving element 100 and a TIA as in the conventional case. The TIA has the same configuration as the transimpedance amplifier core circuit 1 and the transimpedance amplifier core circuit 1 that amplify the current signal IN output from the light receiving element 100 by a gain proportional to the value of the feedback resistor Rf and simultaneously convert the current signal IN into a voltage signal. Transimpedance amplifier core circuit 2 having an open input, single-phase-to-differential conversion circuit 3 that converts a single-phase output signal output from transimpedance amplifier core circuit 1 into a differential signal, and single-phase-to-differential An output buffer 4 that outputs the signals converted by the conversion circuit 3 to the outside as differential output signals OUTP and OUTN, an average value of the output signals of the transimpedance amplifier core circuit 1, and an average of the output signals of the transimpedance amplifier core circuit 2 Average value detection circuit for outputting a voltage difference from a value as a detection signal VC A coefficient multiplier 6 such as an operational amplifier that outputs, as a gain control signal VG, a voltage obtained by multiplying the detection signal VC output from the average value detection circuit 5 by a predetermined coefficient, and a voltage obtained by multiplying the detection signal VC by a predetermined coefficient Is output as an offset control signal VO, and a coefficient multiplier 7 such as an operational amplifier.

The transimpedance amplifier core circuit 1 includes an amplifier 8 and a gain control circuit 9 that changes the value of a feedback resistor Rf that connects the signal output terminal and the signal input terminal of the amplifier 8 in accordance with the gain control signal VG. The
Similarly, the transimpedance amplifier core circuit 2 includes an amplifier 10 and a gain control circuit 11 that changes the value of a feedback resistor Rf that connects the signal output terminal and the signal input terminal of the amplifier 10 according to the gain control signal VG. Consists of

  FIG. 2 is a circuit diagram showing a configuration of the transimpedance amplifier core circuit 1. As shown in FIG. 2, the transimpedance amplifier core circuit 1 includes an amplifying transistor Q1 whose base is connected to a signal input terminal, a base connected to the collector of the amplifying transistor Q1, and a power supply voltage VCC supplied to the collector. An output transistor Q2 having an emitter connected to the signal output terminal, a bias voltage VCS supplied to the gate, a current source transistor Q3 having a drain connected to the emitter of the output transistor Q2 and the signal output terminal, and a power supply at one end The voltage VCC is supplied, the other end of the collector resistor Rc1 is connected to the collector of the amplifying transistor Q1 and the base of the output transistor Q2, the one end is connected to the emitter of the amplifying transistor Q1, and the power supply voltage VEE is connected to the other end. The emitter resistor Re1 to be supplied and one end of the current source transistor The emitter resistor Re2 is connected to the source of the transistor Q3, the other end is supplied with the power supply voltage VEE, and the feedback resistor Rf has one end connected to the signal output terminal and the other end connected to the signal input terminal. .

  The amplifying transistor Q1, the collector resistor Rc1, and the emitter resistor Re1 constitute a grounded emitter circuit, and the output transistor Q2, the current source transistor Q3, and the emitter resistor Re2 constitute an emitter follower circuit. That is, the transimpedance amplifier core circuit 1 shown in FIG. 2 has a grounded emitter / parallel feedback type circuit configuration including a grounded emitter circuit, an emitter follower circuit, and a feedback resistor Rf. The grounded emitter circuit and the emitter follower circuit constitute the amplifier 8 shown in FIG. The transimpedance amplifier core circuit 1 amplifies the input signal IN (current signal) input from the signal input terminal to the base of the amplifying transistor Q1 according to the value of the feedback resistor Rf, and converts it into a voltage signal. Thereafter, the output signal COP (voltage signal) obtained by power amplification is output from the emitter of the output transistor Q2 with low impedance. The current source transistor Q3 and the emitter resistor Re2 of the emitter follower circuit are current sources that supply a constant current to the output transistor Q2. In the present embodiment, bipolar transistors are used for Q1 and Q2, and field effect transistors (FETs) are used for Q3 and Q4. When FET is used for Q3 in particular, the drain-source voltage Vds of the FET is An ideal current source that can supply a large current even when the current is reduced can be obtained, and as a result, even when a large output voltage is output to the COP, there is an effect that the output waveform is hardly distorted. However, if the COP waveform distortion is allowed to some extent, Q3 may be composed of a bipolar transistor.

  In the feedback resistor Rf of the present embodiment, the gain control signal VG is input to the gate, the source is connected to the signal output terminal of the transimpedance amplifier core circuit 1, and the drain is connected to the signal input terminal of the transimpedance amplifier core circuit 1. Transistor Q4, and a feedback resistor Rf1 having one end connected to the signal output terminal and the other end connected to the signal input terminal. The transistor Q4 constitutes the gain control circuit 9 shown in FIG.

  The transimpedance amplifier core circuit 2 has the same circuit configuration as the transimpedance amplifier core circuit 1 shown in FIG. 2 except that the current signal IN is not input and the signal input terminal is open. Thereby, the transimpedance amplifier core circuit 2 outputs an output signal CON having the same voltage as the output signal COP of the transimpedance amplifier core circuit 1 when no input is made.

  FIG. 3 is a circuit diagram showing a configuration of the single-phase / differential conversion circuit 3. The single-phase-to-differential conversion circuit 3 has a base connected to the first signal input terminal, a transistor Q5 to which the output signal COP of the transimpedance amplifier core circuit 1 is input, and a base connected to the second signal input terminal. The transistor Q6 to which the output signal CON of the transimpedance amplifier core circuit 2 is input, the offset control signal VO to the base, the transistor Q7 having the collector connected to the collector of the transistor Q6, and the collector to the collector of the transistor Q5 The transistor Q8 connected to the base, the base connected to the collectors of the transistors Q6 and Q7, the power supply voltage VCC supplied to the collector, the emitter connected to the positive phase output terminal, and the bases of the transistors Q5 and Q8 Connected to the collector and the power supply voltage VC to the collector Is supplied, the emitter is connected to the inverting output terminal, the power supply voltage VCC is supplied to one end, and the other end is connected to the collectors of the transistors Q5 and Q8 and the base of the transistor Q10, and one end Is connected to the collectors of the transistors Q6 and Q7 and the base of the transistor Q9, the power supply voltage VCC is supplied to one end, and the other end is connected to the base of the transistor Q8. The resistor Rb1, one end connected to the base of the transistor Q8, the other end connected to the power supply voltage VEE, the other end connected to the emitters of the transistors Q5 and Q6, and the other end supplied the power supply voltage VEE. , A current source I1 for supplying a constant current to the transistors Q5 and Q6, and one end of the transistor 7 and Q8 are connected to the emitter, the other end is supplied with the power supply voltage VEE, the transistor Q7 and Q8 are supplied with a constant current, one end is connected to the emitter of the transistor Q9 and the positive phase output terminal, A power source voltage VEE is supplied to the other end, a current source I3 that supplies a constant current to the transistor Q9, one end is connected to the emitter and the inverted output terminal of the transistor Q10, and the other end is supplied with the power source voltage VEE. And a current source I4 for supplying a constant current.

Transistor Q9 and current source I3 constitute an emitter follower circuit, and similarly, transistor Q10 and current source I4 constitute an emitter follower circuit.
The transistors Q7 and Q8, the resistors Rb1 and Rb2, and the current source I2 constitute an offset control circuit that cancels the offset of the differential output signals OUTP and OUTN. The offset control circuit adjusts the DC offset voltage of the differential output signals OUTP and OUTN by changing the balance of the current values flowing through the resistors Rl1 and Rl2 in accordance with the offset control signal VO.

FIG. 4 is a circuit diagram showing another configuration of the single-phase / differential conversion circuit 3. The single-phase-to-differential conversion circuit 3 shown in FIG. 4 removes the resistors Rb1 and Rb2 from the configuration shown in FIG. 3, inputs a positive-phase offset control signal VOP to the base of the transistor Q7, and supplies the base of the transistor Q8. The offset control signal VON obtained by inverting the signal VOP is input to the signal. That is, in the configuration shown in FIG. 3, the offset control signal VO is a single-phase signal, whereas in the configuration shown in FIG. 4, the offset control signals VOP and VON are differential signals. In order to use the configuration shown in FIG. 3, a single-phase output operational amplifier may be used as the coefficient multiplier 7, and in order to use the configuration shown in FIG. Can be used.
In the configuration shown in FIGS. 3 and 4, bipolar transistors are used, but there is no problem even if field effect transistors are used.

  FIG. 5 is a circuit diagram showing a configuration of the average value detection circuit 5. The average value detection circuit 5 includes an operational amplifier A1 that outputs a detection signal VC corresponding to the input voltage difference between the non-inverting input terminal and the inverting input terminal, one end connected to the first signal input terminal, and the other end of the operational amplifier A1. A resistor R1P connected to the non-inverting input terminal, to which the output signal COP of the transimpedance amplifier core circuit 1 is input, one end connected to the second signal input terminal, and the other end connected to the inverting input terminal of the operational amplifier A1. The resistor R1N to which the output signal CON of the transimpedance amplifier core circuit 2 is input, the resistor R2P having one end connected to the non-inverting input terminal of the operational amplifier A1, and the resistor R2N having one end connected to the inverting input terminal of the operational amplifier A1. And one end connected to the other end of the resistor R2P, the other end connected to the ground, and one end connected to the other end of the resistor R2N, and the other end Composed of the capacitor CN connected to the signal output terminal of the amplifier A1.

  The average value detection circuit 5 outputs a voltage difference between the average value of the output signal COP of the transimpedance amplifier core circuit 1 and the average value of the output signal CON of the transimpedance amplifier core circuit 2 as a detection signal VC. In the circuit shown in FIG. 5, the resistors R1P and R2P and the capacitor CP constitute a low-pass filter (first average voltage detecting means), and the average value of the output signal COP of the transimpedance amplifier core circuit 1 is the value of the operational amplifier A1. The signal is input to the non-inverting input terminal. Similarly, the resistors R1N and R2N and the capacitor CN constitute a low-pass filter (second average voltage detecting means), and the average value of the output signal CON of the transimpedance amplifier core circuit 2 is input to the inverting input terminal of the operational amplifier A1. It has come to be.

  The average value detection circuit 5 moves the value of the detection signal VC so that the input voltage difference of the operational amplifier A1 (voltage difference between the average value of the signal COP and the average value of the signal CON) becomes zero. When the input voltage difference of the operational amplifier A1 becomes zero, the detection signal VC becomes constant. In the example of FIG. 5, the detection signal VC increases when the average value of the signal COP is larger than the average value of the signal CON, and conversely, when the average value of the signal COP is smaller than the average value of the signal CON, the detection signal VC decreases. To do.

Hereinafter, the operation of the TIA according to the present embodiment will be described in more detail. The transistor Q4 constituting the gain control circuit 9 becomes a continuously variable resistance whose resistance value between the drain and the source continuously changes in accordance with the gain control signal VG. As apparent from the fact that the transistor Q4 is connected in parallel to the feedback resistor Rf1, it plays a role of continuously changing the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1.
Similarly, the gain control circuit 11 plays a role of continuously changing the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 2 in accordance with the gain control signal VG.

  When the power of the input optical signal incident on the light receiving element 100 is increased and the average value of the output signal COP of the transimpedance amplifier core circuit 1 is increased, the detection signal VC is increased and the gain control signal VG is increased. The resistance value between the drain and source of Q4 becomes small. As a result, the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1 (the combined resistance value of the transistor Q4 and the feedback resistor Rf1) is reduced, so that the gain of the transimpedance amplifier core circuit 1 is reduced. The same operation as that of the transimpedance amplifier core circuit 1 also occurs in the transimpedance amplifier core circuit 2, and the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 2 becomes small. Only the gain of the transimpedance amplifier core circuit 2 is reduced.

  On the contrary, when the power of the input optical signal becomes weak and the average value of the output signal COP of the transimpedance amplifier core circuit 1 becomes small, the detection signal VC is lowered and the gain control signal VG is lowered, so that the drain of the transistor Q4 -The resistance value between sources increases. Thereby, since the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1 is increased, the gain of the transimpedance amplifier core circuit 1 is increased. The same operation also occurs in the transimpedance amplifier core circuit 2 and the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 2 is increased. Therefore, the transimpedance amplifier core circuit 2 is equivalent to the gain increase of the transimpedance amplifier core circuit 1. The gain of increases. Thus, in this embodiment, AGC can be performed so that the output signal of the TIA has a desired amplitude.

  On the other hand, when the power of the input optical signal is increased and the average value of the output signal COP of the transimpedance amplifier core circuit 1 is increased, the detection signal VC rises and the offset control signal VO rises. In the single-phase / differential conversion circuit 3, the collector current of the transistor Q7 increases, and the current flowing through the resistor Rl2 increases. As a result, the base voltage of the transistor Q9 decreases, and the emitter voltage of the transistor Q9, that is, the bias voltage of the positive phase output terminal of the single phase-differential conversion circuit 3 decreases. Due to the decrease in the bias voltage, the offset amounts of the differential output signals OUTP and OUTN are suppressed so as to approach zero.

  Conversely, when the power of the input optical signal becomes weak and the average value of the output signal COP of the transimpedance amplifier core circuit 1 becomes small, the necessary offset compensation voltage also becomes small. As a result, the detection signal VC decreases and the offset control signal VO decreases, so that the collector current of the transistor Q7 decreases. When the collector current of the transistor Q7 decreases, the effect of lowering the bias voltage at the positive phase output terminal of the single-phase-to-differential conversion circuit 3 is weakened, so the effect of reducing the offset voltage of the differential output signals OUTP and OUTN is also weakened. Become. Thus, in this embodiment, it is possible to appropriately compensate for the offset voltage between the differential signals in accordance with the input current to the TIA.

  In the example of FIG. 3, only the current flowing through the resistor Rl2 is adjusted. However, in the example of FIG. 4, AOC is performed by adjusting the current flowing through the resistors Rl1 and Rl2. That is, when the power of the input optical signal is increased, the offset control signal VOP is increased and at the same time the offset control signal VON is decreased. Therefore, the collector current of the transistor Q7 is increased in the single-phase-differential conversion circuit 3 shown in FIG. As the current flowing through the resistor Rl2 increases, the collector current of the transistor Q8 decreases and the current flowing through the resistor Rl1 decreases. As a result, the base voltage of the transistor Q9 decreases, the bias voltage at the positive phase output terminal of the single phase-differential conversion circuit 3 decreases, and at the same time, the base voltage of the transistor Q10 increases, and the single phase-differential conversion circuit 3 The bias voltage of the inverting output terminal increases. Due to these changes in the bias voltage, the offset amounts of the differential output signals OUTP and OUTN are suppressed so as to approach zero. On the contrary, when the power of the input optical signal is weakened, the change in the bias voltage is reduced, so that the effect of suppressing the offset amount of the differential output signals OUTP and OUTN is also weakened.

  As described above, in this embodiment, by using the transimpedance amplifier core circuit 2 having the same configuration as that of the transimpedance amplifier core circuit 1 and having an input in an open state, the output signal of the transimpedance amplifier core circuit 1 at the time of no input is used. It is possible to obtain an output signal CON having the same voltage as COP. In the present embodiment, the average value of the output signal COP of the transimpedance amplifier core circuit 1 whose input is connected to the light receiving element 100 and the average value of the output signal CON of the transimpedance amplifier core circuit 2 whose input is open Is detected by the average value detection circuit 5, the detection signal VC becomes a signal indicating both the amplitude information of the input signal IN and the information of the input offset amount of the single-phase-to-differential conversion circuit 3.

  In this embodiment, by using feedback control to perform AGC and using feedforward control to perform AOC, interference between the AGC loop and the AOC loop can be improved. A control with a short response time can be realized in a TIA that performs both controls.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a configuration of an optical receiver circuit of an OLT according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.
The TIA of the present embodiment is composed of transimpedance amplifier core circuits 1a and 2a, a single-phase / differential conversion circuit 3, an output buffer 4, an average value detection circuit 5, and coefficient multipliers 6 and 7. The

The transimpedance amplifier core circuit 1a includes an amplifier 8, a gain control circuit 9, and a frequency band control circuit 12.
Similarly, the transimpedance amplifier core circuit 2 includes an amplifier 10, a gain control circuit 11, and a frequency band control circuit 13.

FIG. 7 is a circuit diagram showing a configuration of the transimpedance amplifier core circuit 1a. The feedback resistor Rf of the present embodiment includes a transistor Q4 that constitutes the gain control circuit 9, a transistor Q11 that has a gate to which the frequency band control signal rate_sel is input, and a drain that is connected to the signal output terminal of the transimpedance amplifier core circuit 1a. A feedback resistor Rf1 having one end connected to the signal output terminal and the other end connected to the signal input terminal of the transimpedance amplifier core circuit 1a, one end connected to the source of the transistor Q11, and the other end connected to the signal input terminal. The feedback resistor Rf2 is connected. The transistor Q11 and the feedback resistor Rf2 constitute the frequency band control circuit 12 shown in FIG. The other configuration of the transimpedance amplifier core circuit 1a is the same as that of the transimpedance amplifier core circuit 1.
The transimpedance amplifier core circuit 2a has the same configuration as the transimpedance amplifier core circuit 1a shown in FIG. 7 except that the signal input terminal is open.

  In the present embodiment, a frequency band control signal rate_sel for controlling the frequency band of the transimpedance amplifier core circuit 1a according to the transmission rate of the input optical signal is input. By changing the value of the feedback resistor Rf in accordance with the frequency band control signal rate_sel, the transimpedance amplifier core circuit 1a has the frequency band of the transimpedance amplifier core circuit 1a corresponding to the transmission speed of the input optical signal. Control for adjusting the gain is performed.

  FIG. 8 is a diagram showing changes in the frequency band of the transimpedance amplifier core circuit 1a due to changes in the feedback resistor Rf, where the horizontal axis represents frequency and the vertical axis represents the open loop gain of the transimpedance amplifier core circuit 1a. As shown in FIG. 8, when the value of the feedback resistor Rf is changed to R1, R2,..., Rn (R1> R2>...> Rn), the frequency band of the transimpedance amplifier core circuit 1a is changed. Changes to f1, f2,..., Fn (f1 <f2 <... <Fn). In other words, when the value of the feedback resistor Rf is reduced, the gain of the transimpedance amplifier core circuit 1a is reduced, but the frequency band is widened.

  In the present embodiment, the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1a is changed by turning on / off the transistor Q11. When the transmission speed of the input optical signal is low (for example, 1 Gbit / s), the transistor Q11 is turned off by the frequency band control signal rate_sel given from the host controller (not shown). In this case, the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1a is mainly determined by the combined resistance of the transistor Q4 and the feedback resistor Rf1, and the influence of the transistor Q11 and the feedback resistor Rf2 on the resistance value of the feedback resistor Rf is reduced. .

  On the other hand, when the transmission speed of the input optical signal is high (for example, 10 Gbit / s), the transistor Q11 is turned on by the frequency band control signal rate_sel. As a result, the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 1a (the combined resistance value of the transistors Q4 and Q11 and the feedback resistors Rf1 and Rf2) is reduced, so that the gain of the transimpedance amplifier core circuit 1a decreases. The frequency band of the transimpedance amplifier core circuit 1a is widened.

  The same operation as that of the transimpedance amplifier core circuit 1a also occurs in the transimpedance amplifier core circuit 2a, and the resistance value of the feedback resistor Rf of the transimpedance amplifier core circuit 2a decreases or increases according to the frequency band control signal rate_sel. Therefore, the frequency band of the transimpedance amplifier core circuit 2a becomes wider or narrower in conjunction with the transimpedance amplifier core circuit 1a. Thereby, the transimpedance amplifier core circuit 2a outputs an output signal CON having the same voltage as the output signal COP of the transimpedance amplifier core circuit 1a when there is no input.

  As described above, in the present embodiment, control for adjusting the gain of the transimpedance amplifier core circuit 1a is realized so that the frequency band of the transimpedance amplifier core circuit 1a becomes a band corresponding to the transmission speed of the input optical signal. can do.

  The present invention can be applied to a transimpedance amplifier that converts an input current signal obtained in a light receiving element into a voltage signal. The transimpedance amplifier is used as an optical receiver that converts an optical signal into an electric signal in an optical transmission circuit such as an optical transmission system, an optical interconnection, or a passive optical network system that enables high-speed data transmission.

  DESCRIPTION OF SYMBOLS 1, 1a, 2, 2a ... Transimpedance amplifier core circuit, 3 ... Single phase-differential conversion circuit, 4 ... Output buffer, 5 ... Average value detection circuit, 6, 7 ... Coefficient multiplier, 8, 10 ... Amplifier, 9, 11 ... gain control circuit, 12, 13 ... frequency band control circuit, 100 ... light receiving element, TIA ... transimpedance amplifier, A1 ... operational amplifier, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11 ... transistor, Rb1, Rb2, Rc1, Re1, Re2, Rf, Rf1, Rf2, Rl1, Rl2, R1P, R1N, R2P, R2N ... resistor, CP, CN ... capacitor, I1, I2, I3, I4 ... Current source.

Claims (6)

A first transimpedance amplifier core circuit that amplifies the input current signal by a gain proportional to the value of the feedback resistor and simultaneously converts it into a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input in an open state;
An average value detection circuit for detecting a voltage difference between an average value of the output signal of the first transimpedance amplifier core circuit and an average value of the output signal of the second transimpedance amplifier core circuit;
The output signal of the first transimpedance amplifier core circuit and the output signal of the second transimpedance amplifier core circuit are input, and the output signal of the first transimpedance amplifier core circuit is converted into a differential signal. A phase-to-differential conversion circuit,
The first and second transimpedance amplifier core circuits each change a feedback resistance value of the first and second transimpedance amplifier core circuits according to a detection result of the average value detection circuit. With
The single-phase to differential conversion circuit includes an offset control circuit that controls a DC voltage of the differential signal so that an offset of the differential signal becomes zero according to a detection result of the average value detection circuit,
A transimpedance amplifier, wherein feedback control is used as the gain control method, and feedforward control is used as the offset control method. The transimpedance amplifier according to claim 1,
Further, provided between the average value detection circuit and the gain control circuit, a voltage obtained by multiplying the voltage output from the average value detection circuit by a first coefficient is output to the gain control circuit as a gain control signal. A first coefficient multiplier;
A second circuit is provided between the average value detection circuit and the offset control circuit, and outputs a voltage obtained by multiplying the voltage output from the average value detection circuit by a second coefficient to the offset control circuit as an offset control signal. A transimpedance amplifier. The transimpedance amplifier according to claim 1 or 2,
The first and second transimpedance amplifier core circuits are:
A grounded-emitter circuit connected to each signal input terminal;
An emitter follower circuit that amplifies the voltage signal output from the grounded emitter circuit and outputs the amplified signal to the signal output terminal;
The feedback resistor having one end connected to the signal output terminal and the other end connected to the signal input terminal;
A transimpedance amplifier comprising the gain control circuit. The transimpedance amplifier according to claim 1 or 2,
The average value detection circuit includes:
An operational amplifier that outputs detection results;
First average voltage detection means for giving an average voltage of an output signal of the first transimpedance amplifier core circuit to a non-inverting input terminal of the operational amplifier;
A transimpedance amplifier, comprising: a second average voltage detection unit that applies an average voltage of an output signal of the second transimpedance amplifier core circuit to an inverting input terminal of the operational amplifier. The transimpedance amplifier according to claim 1 or 2,
The single phase-differential conversion circuit is:
A first transistor pair that receives an output signal of the first transimpedance amplifier core circuit and an output signal of the second transimpedance amplifier core circuit;
A pair of load resistors having one end supplied with a power supply voltage and the other end connected to the output terminal of the first transistor pair;
A pair of emitter follower circuits that receive the output of the first transistor pair and output the differential signal;
A first current source for supplying a constant current to the first transistor pair;
The offset control circuit,
The offset control circuit
A second transistor pair for controlling an amount of current flowing through the load resistor in accordance with a detection result of the average value detection circuit;
A transimpedance amplifier comprising: a second current source for supplying a constant current to the second transistor pair. The transimpedance amplifier according to any one of claims 1 to 5,
The first and second transimpedance amplifier core circuits are configured so that the frequency bands of the first and second transimpedance amplifier core circuits are in accordance with the transmission speed of the input current signal, respectively. A transimpedance amplifier comprising a frequency band control circuit for changing a value of a feedback resistor of the transimpedance amplifier core circuit.

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