JP4862390B2 - Manufacturing method of electronic substrate - Google Patents

Description

  The present invention relates to an electronic substrate, a manufacturing method thereof, a circuit board, and an electronic device, and more particularly to an electronic substrate in which a resistor is provided on the substrate, a manufacturing method thereof, a circuit substrate, and an electronic device.

In recent years, with the miniaturization and high functionality of electronic devices, the size and density of packages have been required to be reduced.
For example, Patent Document 1 and Patent Document 2 disclose a technique related to a semiconductor device (semiconductor package) in which a resistive element of a film body is provided on an interposer substrate.
Japanese Patent Laid-Open No. 10-41434 JP 2003-204016 A

However, the following problems exist in the conventional technology as described above.
In any of the technologies, since the resistor is built in the interposer substrate, it cannot be said that the miniaturization is sufficiently achieved.
It is also possible to reduce the size by patterning a part of the wiring to form a resistance element. In this case, however, patterning for removing a part of the wiring at the time of patterning at the time of wiring formation and the resistor is performed. In each case, it is necessary to apply a resist, resulting in a problem that productivity is lowered.

  The present invention has been made in consideration of the above points. An electronic substrate that can form a resistance element without causing a decrease in productivity and can be reduced in size, a manufacturing method thereof, a circuit substrate, and an electronic device. The purpose is to provide.

In order to achieve the above object, the present invention employs the following configuration.
The method for manufacturing an electronic substrate according to the present invention is a method for manufacturing an electronic substrate in which a wiring pattern having a first conductive layer and a second conductive layer is formed in a wiring region on the substrate, wherein the wiring pattern is formed on the first conductive layer. A step of forming the second conductive layer in a range excluding the resistance element formation region in the wiring region, forming a photosensitive layer on the first conductive layer, and among the wiring regions of the photosensitive layer Removing the range excluding the resistance element formation region, forming an opening, forming the second conductive layer on the first conductive layer through the opening, and the second conductive layer And a step of removing the first conductive layer outside the wiring region, and a step of removing the photosensitive layer in the resistance element formation region, using the photosensitive layer in the resistance element formation region as a mask. .
The method for manufacturing an electronic substrate according to the present invention is a method for manufacturing an electronic substrate in which a wiring pattern having a first conductive layer and a second conductive layer is formed in a wiring region on the substrate, wherein the wiring pattern is formed on the first conductive layer. The wiring region includes a step of forming the second conductive layer in a range excluding the resistance element formation region.

Therefore, in the method for manufacturing an electronic substrate according to the present invention, since a part of the resistance element forming region of the wiring pattern does not have the second conductive layer, the resistance value is higher than that of the other part, and the resistance element can be easily obtained. Can be formed. Since this resistance element is formed by a wiring pattern, it is possible to reduce the size, and an independent process for separately forming the resistance element is not required, and a reduction in productivity can be avoided.
In the present invention, it is sufficient to apply a resist when forming the second conductive layer, and it is necessary to apply the resist again as in the case of forming a resistance element by removing a part of the second conductive layer. It becomes possible to contribute to the improvement of productivity.

In the present invention, a step of forming a photosensitive layer on the first conductive layer, a step of removing an area excluding the resistance element formation region in the wiring region of the photosensitive layer, and forming an opening, Forming the second conductive layer on the first conductive layer through the opening; and using the photosensitive layer in the second conductive layer and the resistance element formation region as a mask, the second conductive layer outside the wiring region. A procedure having a step of removing one conductive layer and a step of removing the photosensitive layer in the resistance element forming region can be suitably employed.
Accordingly, in the present invention, a wiring pattern in which a resistance element is formed in the resistance element formation region can be easily formed by the photosensitive layer that has been applied once.

In the present invention, it is possible to preferably employ a procedure including a step of forming the photosensitive layer with a positive resist and exposing the photosensitive layer outside the wiring region while shielding at least the resistance element forming region.
Therefore, in the present invention, the photosensitive layer outside the wiring region can be removed by developing the substrate, and the wiring pattern can be easily patterned by removing the exposed first conductive layer by etching or the like. At this time, since the photosensitive layer in the resistance element formation region is not exposed, it is not removed even after development, and can function as a mask during the etching process.

  The method for manufacturing an electronic substrate according to the present invention includes a step of forming a photosensitive layer on a substrate having a first conductive layer and a second conductive layer, and leaving the photosensitive layer located in a wiring region out of the photosensitive layer. A method of manufacturing an electronic substrate, comprising: exposing the photosensitive layer located in the non-wiring region to form an opening; and patterning the first conductive layer and the second conductive layer through the opening. A step of exposing the photosensitive layer located in the resistance element formation region of the photosensitive layer remaining in the wiring region to form a second opening; and the resistance through the second opening. And a step of removing the second conductive layer located in the element formation region.

  Therefore, in the method for manufacturing an electronic substrate of the present invention, the first conductive layer and the second conductive layer located in the non-wiring region can be removed and patterned using the photosensitive layer that has been applied once, and also located in the resistance element formation region. The second conductive layer can be removed. In this case, since a part of the resistance element formation region of the wiring pattern does not have the second conductive layer, the resistance value is higher than that of the other part, and the resistance element can be easily formed. Since this resistance element is formed by a wiring pattern, it is possible to reduce the size, and an independent process for separately forming the resistance element is not required, and a reduction in productivity can be avoided.

In the present invention, it is preferable that the first conductive layer includes a material having a larger resistance value than the second conductive layer.
Thereby, in this invention, it becomes possible to form easily a resistive element with a large resistance value.

As this wiring pattern, it is possible to adopt a configuration in which it is connected to the electrode portion or a configuration in which at least a part forms a connection terminal.
Further, the wiring pattern may be configured to be connected to the electrode portion and at least partly connected to an external terminal (for example, a wafer level CSP (Wafer Level Chip Size Package) package body).

As the connection terminal, it is possible to suitably adopt a configuration in which a resin material is used as a core and at least a top portion is formed of a bump electrode covered with the wiring pattern.
Thereby, in the present invention, since the resistance element can be formed in the vicinity of the bump electrode, the path between the bump electrode and the resistance element can be minimized, and the wiring can be minimized.

Moreover, the structure by which the semiconductor element is provided in the said board | substrate and is electrically connected to the said wiring pattern can also be employ | adopted suitably.
Accordingly, in the present invention, since the resistance element can be formed in the vicinity of the semiconductor element, the path between the semiconductor element and the resistance element can be minimized, and the wiring can be minimized.
In this case, the semiconductor element can be configured such that a switching element such as a transistor is formed by a wiring pattern formed in the active region, or a semiconductor chip containing the semiconductor element is mounted in the active region.
Further, the present invention is applicable even when the semiconductor element is not mounted on the substrate, that is, when the semiconductor element is not provided, for example, a silicon substrate state.

And the electronic board | substrate of this invention was manufactured with the manufacturing method as described previously, It is characterized by the above-mentioned.
Therefore, according to the present invention, it is possible to obtain a resistance element efficiently and easily.
Moreover, in this invention, the structure by which the 2nd wiring pattern laminated | stacked through the insulating layer is electrically connected to the said wiring pattern which has the said resistive element can also be employ | adopted suitably.
Thus, according to the present invention, it is possible to easily and efficiently form a resistance element on an electronic substrate on which wiring patterns are laminated.

A circuit board according to the present invention includes the electronic board described above. And the electronic device of this invention is equipped with the electronic substrate as described above, It is characterized by the above-mentioned.
Therefore, according to the present invention, it is possible to efficiently obtain a circuit board and an electronic device without reducing productivity.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an electronic board, a manufacturing method thereof, a circuit board, and an electronic device according to the present invention will be described below with reference to FIGS.
[Electro-optical device]
FIG. 1 is a schematic view showing a liquid crystal display device which is an embodiment of an electro-optical device.
The illustrated liquid crystal display device (electro-optical device) 100 includes a liquid crystal panel 110 and a semiconductor device 121. Moreover, incidental members, such as a polarizing plate, a reflective sheet, and a backlight (not shown), are appropriately provided as necessary.

  The liquid crystal panel 110 includes substrates 111 and 112 made of glass or plastic. The substrate 111 and the substrate 112 are disposed to face each other and are bonded to each other by a sealing material (not shown). A liquid crystal (not shown) that is an electro-optical material is sealed between the substrate 111 and the substrate 112. An electrode 111a made of a transparent conductor such as ITO (Indium Tin Oxide) is formed on the inner surface of the substrate 111, and an electrode 112a disposed opposite to the electrode 111a is formed on the inner surface of the substrate 112. . The electrode 111a and the electrode 112a are arranged so as to be orthogonal to each other. Then, the electrode 111a and the electrode 112a are drawn out to the substrate extension portion 111T, and an electrode terminal 111bx and an electrode terminal 111cx are formed at the end portions, respectively. An input wiring 111d is formed in the vicinity of the edge of the substrate overhanging portion 111T, and a terminal 111dx is also formed at the inner end thereof.

  A semiconductor device 121 is mounted on the substrate extension 111T via a sealing resin 122. The semiconductor device 121 is, for example, a liquid crystal driving IC chip that drives the liquid crystal panel 110. A large number of bump electrodes (not shown) are formed on the lower surface of the semiconductor device 121, and these bumps are conductively connected to terminals 111bx, 111cx, 111dx on the substrate overhanging portion 111T, respectively.

  A flexible wiring board 123 is mounted on the input terminal 111dy formed at the outer end of the input wiring 111d via an anisotropic conductive film 124. The input terminals 111dy are conductively connected to wirings (not shown) provided on the flexible wiring board 123, respectively. Then, a control signal, a video signal, a power supply potential, and the like are supplied from the outside via the flexible wiring board 123 to the input terminal 111dy, and a driving signal for driving the liquid crystal is generated in the semiconductor device 121 and supplied to the liquid crystal panel 110. It is like that.

  According to the liquid crystal display device 100 of the present embodiment configured as described above, an appropriate voltage is applied between the electrode 111a and the electrode 112a via the semiconductor device 121, whereby the electrodes 111a and 112a are Light can be modulated by re-orienting the liquid crystal of the pixel portions opposed to each other, whereby a desired image can be formed in the display area in which the pixels in the liquid crystal panel 110 are arranged.

  FIG. 2 is a side cross-sectional view taken along the line HH in FIG. 1, and is an explanatory diagram of a mounting structure of the semiconductor device 121 in the liquid crystal display device 100. As shown in FIG. 2, a plurality of electrodes 10 are provided as connection terminals on the active surface (lower surface in the drawing) of the semiconductor device 121 as connection terminals, and the tips thereof are in direct conductive contact with the terminals 111bx and 111dx of the substrate 111. is doing. A cured sealing resin 122 made of a thermosetting resin or the like is filled around the conductive contact portion between the electrode 10 and the terminals 111bx and 111dx.

[Method for Manufacturing Semiconductor Device]
(First embodiment)
Next, a method for manufacturing the semiconductor device 121 as the electronic substrate according to the first embodiment will be described. Here, a case where the semiconductor device 121 is a wafer level CSP type will be described.
3 to 5 are process diagrams showing an example of a method for manufacturing the semiconductor device 121.
The semiconductor device 121 is, for example, an IC chip that drives a pixel of a liquid crystal display device, and an electronic circuit (integrated circuit) such as a plurality of electronic elements such as thin film transistors and wirings connecting the electronic elements on the active surface side. Or the like (both not shown).

First, as shown in FIG. 3A, a passivation film 26 is formed on the active surface 121a of the substrate P on which a semiconductor element (not shown) is formed. That is, after a passivation film 26 such as SiO ₂ or SiN is formed on the substrate P by a film formation method, an opening 26a through which the electrode pad (electrode portion) 24 is exposed is formed by patterning using a photolithography method. The electrode pad 24 is made of Al or the like and is drawn out from the above-described electronic element or the like and functions as an external electrode of the electronic circuit.

  The opening 26a is formed by forming a resist layer on the passivation film 26 by a spin coating method, a dipping method, a spray coating method, or the like, and further exposing and developing the resist layer using a mask in which a predetermined pattern is formed. Then, a resist pattern (not shown) having a predetermined shape is formed. Thereafter, the film is etched using the resist pattern as a mask to form an opening 26a exposing the electrode pad 24, and the resist pattern is removed using a stripping solution or the like.

Here, dry etching is preferably used for the etching, and reactive ion etching (RIE) is preferably used as the dry etching. Wet etching can also be used as the etching.
On the passivation film 26, an organic resin film such as polyimide having a high stress relaxation property may be formed on the entire surface or a part other than the opening by using a photolithography method or the like. That is, a resistance element R (described later) formed by the following method may be formed on an organic resin film (insulating film).

Next, after removing the oxide film (Al oxide film) on the electrode pad 24 by Ar reverse sputtering, for example, as shown in FIG. 3B, the conductive film 20a covering the electrode pad 24 and the passivation film 26 and 20b is sequentially formed by sputtering. The conductive film 20a forms a first wiring pattern, and is formed with a thickness of, for example, 0.1 μm by TiW as a barrier metal layer. The conductive film 20b is formed of Cu as a seed layer, for example, with a thickness of 0.3 μm. These conductive films 20a and 20b constitute the first conductive layer according to the present invention.
These conductive films 20a and 21a are not patterned here, but are entirely formed as so-called solid films.

Thereafter, similarly to the passivation film 26, the conductive films 20a and 20b are patterned by photolithography.
Specifically, as shown in FIG. 3C, a positive resist layer (photosensitive layer) 21 is formed on the conductive films 20a and 20b by a spin coating method, a dipping method, a spray coating method, etc. A mask in which a pattern excluding a resistance element region is opened in a wiring region for forming a wiring pattern, and a non-wiring region outside the wiring region and the resistance element forming region are shielded from exposure light is formed. The resist layer 21 is exposed and developed using M1, and as shown in FIG. 3D, a resist pattern (a pattern in which the wiring portion is opened) having an opening 21a in the wiring pattern forming region is formed. To do.
At this time, since no opening is formed in the resist layer 21 in the resistance element formation region, the resist remains as the remaining portion 21b on the conductive films 20a and 20b. In addition, the width of the wiring pattern is set in consideration of the side etching amount generated during the etching process described later.

  Then, Cu electrolytic plating is performed using this resist pattern as a mask, and as shown in FIG. 3E, Cu (copper) is embedded in the opening 21a, and the seed layer of the conductive film 20b exposed from the opening 21a is formed. Then, a Cu conductive film (second conductive layer) 20c is formed.

  Subsequently, as shown in FIG. 4A, the resist layer is masked using a mask M2 that shields the remaining portion 21b from the exposure light and opens corresponding to a region other than the remaining portion 21b including the non-wiring region. The resist layer 21 other than the remaining portion 21b is removed as shown in FIG.

Then, as shown in FIG. 4C, the exposed conductive films 20a and 20b are removed by an etching process using the conductive film 20c and the remaining portion 21b as a mask. At this time, since the surface of the conductive film 20c is also removed, it is desirable that the thickness of the conductive film 20c be formed in advance in consideration of this removal amount.
Thereby, the conductive films 20a and 20b in the non-wiring region are removed.
Subsequently, as shown in FIG. 4D, the resist of the remaining portion 21 is removed using a stripping solution or the like, and the exposed conductive film 20b is removed by re-etching.
As a result, as shown in FIG. 4E, the wiring pattern 1 having the resistance element R made of the conductive film 20a is formed on the substrate P.

Here, the material, film thickness, and area of the resistance element R are set according to the required resistance value.
TiW constituting the conductive film 20a has a specific resistance value ρ of about 75 μΩ · cm, which is larger than the specific resistance value (about 1.67 μΩ · cm) of Cu forming the conductive film 20b.
When the resistance element R has a film thickness t, a width w, and a length L, the resistance value is expressed by the following equation.
Resistance value = (L / (t × w)) × ρ (1)
Therefore, for example, when a resistance value of 50Ω is set, the resistor element R may be formed with t = 0.1 μm, w = 15 μm, and L = 100 μm using Equation (1).

  Thereafter, an insulating material such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, acrylic resin, phenol resin, BCB (benzocyclobutene) and PBO (polybenzoxazole) is used to cover the wiring pattern 1. A stress relaxation layer (insulating layer) 2 is formed and electrically connected to the wiring pattern 1 with the same procedure and material as the procedure for forming the wiring pattern 1 on the stress relaxation layer 2. A wiring pattern (second wiring pattern) 3 including the film 3a, the conductive film 3b of the seed layer, and the conductive film 3c of the plating layer is formed.

Then, after forming the solder resist layer 4 covering the wiring pattern 3 and the stress relaxation layer 2, the opening 4a exposing the wiring pattern 3 is formed by patterning, and the solder terminal to be the electrode 10 is formed in the opening 4a. As a result, the semiconductor device 121 is manufactured.
By using this electrode 10, it is possible to electrically perform various function tests and function adjustments on a semiconductor element such as an integrated circuit provided on the substrate P.

  The semiconductor device 121 can be mounted by a known SMT (Surface Mount Technology).

  As described above, in the present embodiment, since the resistance element R is formed on a part of the wiring pattern 1, it is not necessary to newly mount a resistance member or the like, and the resistance portion can be easily formed. This contributes to downsizing of the apparatus and improvement of manufacturing efficiency. In the present embodiment, since the resistive element R is formed by forming the conductive film 20c on the conductive films 20a and 20b in a range excluding the resistive element formation region, the resist layer 21 may be formed once. Unlike the case where the resistive element R is formed by removing a part of the conductive film 20c, it is not necessary to form a separate resist layer for forming the resistive element, thereby improving the manufacturing efficiency without causing a decrease in productivity. It can contribute even more.

In the present embodiment, since the resistance value corresponding to the material for forming the resistance element R and the area of the resistance element R can be set, a desired resistance value can be ensured with high accuracy, and the semiconductor device (electronic The reliability of the substrate 121 can be improved.
In particular, in the present embodiment, since the wiring patterns 1 and 3 are formed by a method having excellent film composition, thickness accuracy, and dimensional accuracy, such as sputtering, plating, and photolithography, the resistance value of the resistance element R is further increased. It is possible to control and manage with accuracy.

Furthermore, in this embodiment, since the conductive film 20a located in the lower layer has a larger resistance than the upper conductive films 20b and 20c, it is possible to easily obtain a larger resistance value.
In other words, in this embodiment, the resistance range and the allowable current resistance value are selected by selecting the type of film according to the required value as the resistance and which layer of the conductive film in the laminated structure is used. The design selectivity can be improved.
The same applies to a structure of three or more layers.

  In addition, in the present embodiment, since the resistance element R can be formed in the vicinity of the semiconductor element via the electrode pad 24, the electrical path from the semiconductor element to the resistance element R can be minimized, and extra wiring Can be minimized. Therefore, it is possible to minimize parasitic capacitance, stubs, and the like due to wiring, and it is possible to improve electrical characteristics (loss, noise radiation) particularly in a high frequency region.

(Second Embodiment)
Next, a second embodiment of the method for manufacturing a semiconductor device will be described with reference to FIGS.
In this embodiment, a case where a semiconductor device having a resin core bump electrode is manufactured will be described.
In these drawings, the same components as those in the first embodiment shown in FIGS. 1 to 5 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

First, as shown in FIG. 6A, a passivation film 26 is formed on the active surface 121a of the substrate P on which a semiconductor element (not shown) is formed. That is, after a passivation film 26 such as SiO ₂ or SiN is formed on the substrate P by a film formation method, an opening 26a through which the electrode pad (electrode portion) 24 is exposed is formed by patterning using a photolithography method.

  Next, as shown in FIG. 6B, the resin protrusion 12 is formed on the active surface 121a of the substrate P on which the electrode pad 24 and the passivation film 26 are formed by using, for example, an ink jet method (droplet discharge method). To do. This ink jet method discharges (drops) a droplet-shaped resin material (liquid material) whose liquid amount per droplet is controlled from a nozzle provided in a droplet discharge head, and makes the nozzle face the substrate P. Further, by moving the nozzle and the substrate P relative to each other, a film pattern having a desired shape made of a resin material is formed on the substrate P. And the resin protrusion 12 is obtained by heat-processing this film | membrane pattern.

  The resin protrusion 12 is made of a resin material having elasticity such as a polyimide resin, an acrylic resin, a phenol resin, an epoxy resin, a silicone resin, or a modified polyimide resin, and is formed using, for example, an inkjet method. The cross-sectional shape of the resin protrusion 12 is desirably a shape that can be easily elastically deformed, such as a semicircular shape or a trapezoidal shape as shown in the figure. By doing so, the electrode 10 can be easily elastically deformed at the time of contact with the counterpart substrate, and the reliability of the conductive connection with the counterpart substrate can be improved.

Here, by dropping a plurality of droplets from the droplet discharge head and arranging the resin material, it becomes possible to arbitrarily set the shape of the film made of the resin material, and the resin protrusion 12 by the lamination of the resin material It is possible to increase the film thickness. For example, by repeating a step of placing the resin material on the substrate P and a step of drying the resin material, the resin material dry film is laminated and the resin protrusion 12 is reliably thickened. Further, by dropping droplets including a resin material from a plurality of nozzles provided in the droplet discharge head, it is possible to control the arrangement amount and the arrangement timing of the resin material for each part.
Alternatively, the resin protrusion 12 may be formed by a photolithography method or the like, and a desired resin protrusion 12 shape may be obtained by slackening the periphery of the protrusion during curing.

Next, after removing the oxide film (Al oxide film) on the electrode pad 24 by Ar reverse sputtering, for example, as shown in FIG. Conductive films 20a and 20b covering the electrode pads 24 and the tops of the resin protrusions 12 are sequentially formed by sputtering. The conductive films 20a and 20b are not patterned here, but are formed entirely as a solid film.
In the present embodiment, the conductive film 20a is formed as a barrier metal layer with TiW, for example, with a thickness of 0.1 μm, and the conductive film 20b is formed as a conductive layer with Au, for example, with a thickness of 0.5 μm. .

Thereafter, the conductive films 20a and 20b are patterned using a photolithography method.
Specifically, as shown in FIG. 6D, a positive resist layer (photosensitive layer) 21 is formed on the conductive films 20a and 20b, and a predetermined pattern (a wiring region for forming a wiring pattern is exposed). The resist layer 21 is subjected to an exposure process and a development process using a mask M3 formed with a pattern that is shielded from light and opens in the non-wiring region. As shown in FIG. 21c is provided, and a resist pattern in which the wiring region is covered with a resist is formed.

  Then, etching is performed using the remaining resist layer 21 as a mask to remove the conductive films 20a and 20b exposed in the openings 21c, so that the conductive films 20a and 20b are formed as shown in FIG. Patterned into a predetermined shape.

  Next, as shown in FIG. 7B, an opening corresponding to the shape and position of the resistance element formation region is opened, and other wiring regions remain on the conductive films 20a and 20b using a mask that blocks exposure light. The resist layer 21 to be exposed is subjected to exposure processing and development processing for exposing the resist layer located in the resistance element formation region, and as shown in FIG. 2 openings) 21d. Then, using the resist layer 21 as a mask, only the conductive film 20b exposed from the opening 21d is selectively etched and removed to expose the conductive film 20a.

  Then, by removing the resist layer 21 using a stripping solution or the like, as shown in FIG. 7E, the conductive films 20a and 20b are laminated, and a part (resistance element formation region) is only the conductive film 20a. A wiring pattern 1 having a resistance element R that is formed and having a large resistance value and having a resin core bump electrode 10 is formed.

  Thus, also in this embodiment, since the resistance element R is formed in a part of the wiring pattern 1, it is not necessary to newly mount a resistance member or the like, and the resistance portion can be easily formed. In addition to contributing to downsizing of the device and improvement of manufacturing efficiency, the wiring pattern 1 having the resistance element R can be formed using the resist layer 21 once formed, and therefore a resist layer is separately formed for forming the resistance element. The effect similar to 1st Embodiment can be acquired, such that it becomes unnecessary and can contribute more to the improvement of manufacturing efficiency, without causing the fall of productivity.

[Circuit board]
In the circuit board of the present invention, the semiconductor device 121 shown in FIG. 7E is mounted on the resin core bump electrode 10 on, for example, the substrate 111 shown in FIG. 2, or the semiconductor device 121 shown in FIG. It is formed by being mounted (not shown).
In other words, the external connection terminal 10 of the semiconductor device 121 is electrically connected to the conductive portion of the external structure, thereby forming a circuit board according to an embodiment of the present invention.
According to this circuit board, since the semiconductor device 121 that is reduced in size and improved in manufacturing efficiency is mounted, high-density mounting and productivity can be increased correspondingly, and thus higher functionality and lower cost can be achieved. Can be achieved.

[Electronics]
FIG. 8 is a perspective view showing an example of an electronic apparatus according to the present invention. A cellular phone 1300 shown in the figure includes the above-described electro-optical device as a small-sized display unit 1301 and includes a plurality of operation buttons 1302, a mouthpiece 1303, and a mouthpiece 1304.
The above-described electro-optical device is not limited to the above mobile phone, but an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, It can be suitably used as an image display means for word processors, workstations, videophones, POS terminals, touch panel-equipped devices, etc. In any case, the resistance value is ensured with high accuracy and excellent quality and high functionality It is possible to provide an electronic device that is reduced in cost and cost.

  As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

  For example, as a method of adjusting the resistance value of the resistance element, in addition to the method of adjusting the film thickness t, the width w, and the length L shown in the above formula (1), the shape of the conductive film itself may be adjusted. realizable. For example, as shown in FIG. 9A, a resistance element having a large resistance value formed by a meander-type electrode film bent in a ninety-nine fold shape with a narrower line width than other portions, or FIG. As shown in FIG. 6, a resistance element having a reduced diameter portion (drawing shape) having a large resistance may be used.

Moreover, although the said embodiment demonstrated as what adjusts the resistance value in a resistive element with the thickness and width | variety of a electrically conductive film, as shown, for example in FIG. 10, it forms by exposing the electrically conductive film 20a to a part of wiring pattern. The resistor element R may be trimmed using a laser or the like to provide a cutout portion Ra in which a part of the conductive film 20a is cut out (removed).
In this case, the resistance value can be finely adjusted by adjusting the size of the notch Ra (that is, the size to which the conductive film 20a is connected), and a highly accurate resistance element can be formed more easily. Is possible. In particular, in the embodiment described above, the resistance element R is disposed near the surface of the semiconductor device 121, so that the resistance value can be easily finely adjusted.

Moreover, the material of the conductive film (resistive element) shown in the above embodiment is an example, and other conductive materials such as Ag, Ni, Pd, Al, Cr, Ti, W, NiV, or lead-free solder are also available. Can be used. Even in this case, when a conductive film having a stacked structure is formed using a plurality of materials, the material may be selected so that the conductive film located in the lower layer has a higher resistance value than the conductive film located in the upper layer. preferable.
The conductive films 20 and 21 described above are also formed by sputtering or plating in the present embodiment, but an inkjet method may be used.

  In the above embodiment, the example of the semiconductor device in which the electronic substrate has a semiconductor element is used. However, the electronic substrate according to the present invention does not necessarily have to be provided with a semiconductor element, for example, a semiconductor chip. A non-mounting silicon substrate in which no external device is mounted in an external device mounting region (active region) such as a glass substrate, a ceramic substrate, an organic substrate, or a film substrate is also included. In this case, the electronic substrate according to the present invention may be connected to, for example, a circuit substrate having a semiconductor element via the bump electrode 10, and other electronic circuits are incorporated in those substrates. May be. They may be electronic devices such as liquid crystal panels, plasma displays, crystal oscillators and the like.

Further, in these embodiments, the formed resistance element only needs to be formed using a part of the wiring, and thus does not necessarily have to be connected to the electrodes of the electronic substrate, and contributes only to the connection between the electrodes. However, it may not be connected to the external electrode or the external terminal.
Further, in the above-described embodiment, a mobile phone including an electro-optical device is also exemplified in the electronic apparatus. However, the electronic device is not necessarily provided with an electro-optical device, and an electronic device including the above-described electronic substrate is not provided. Equipment is also included in the present invention.

1 is a schematic diagram illustrating a liquid crystal display device that is an embodiment of an electro-optical device. FIG. It is explanatory drawing of the mounting structure of the semiconductor device in a liquid crystal display device. It is process drawing for demonstrating the manufacturing method of a semiconductor device. FIG. 5 is a process diagram for describing the method for manufacturing a semiconductor device. FIG. 5 is a process diagram for describing the method for manufacturing a semiconductor device. It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 5 is a process diagram for describing the method for manufacturing a semiconductor device. It is a perspective view which shows an example of an electronic device. It is a top view which shows the modification of a resistive element. It is a figure for demonstrating the method to finely adjust resistance value.

Explanation of symbols

R ... resistance element, 1 ... wiring pattern, 2 ... stress relaxation layer (insulating layer), 3 ... wiring pattern (second wiring pattern), 10 ... electrode (bump electrode), 20a, 20b ... conductive film (first conductive layer) 20c ... conductive film (second conductive layer), 21 ... resist layer (photosensitive layer), 21a, 21c ... opening, 21d ... opening (second opening), 24 ... electrode pad (electrode part), 100 Liquid crystal display device (electro-optical device) 121 Semiconductor device (electronic substrate) 121a Active surface 1300 Mobile phone (electronic device)

Claims (7)

A method for manufacturing an electronic substrate, wherein a wiring pattern having a first conductive layer and a second conductive layer is formed in a wiring region on a substrate,
A step of forming the second conductive layer in a range excluding a resistance element forming region in the wiring region on the first conductive layer;
Forming a photosensitive layer on the first conductive layer;
Removing the range excluding the resistance element formation region in the wiring region of the photosensitive layer to form an opening;
Depositing the second conductive layer on the first conductive layer through the opening;
Removing the first conductive layer outside the wiring region using the second conductive layer and the photosensitive layer in the resistance element forming region as a mask;
And a step of removing the photosensitive layer in the resistance element forming region. In the manufacturing method of the electronic substrate of Claim 1,
Forming the photosensitive layer with a positive resist;
A method of manufacturing an electronic substrate, comprising a step of exposing the photosensitive layer outside the wiring region while shielding at least the resistance element forming region. In the manufacturing method of the electronic substrate of Claim 1 or 2,
The method of manufacturing an electronic substrate, wherein the first conductive layer includes a material having a resistance value larger than that of the second conductive layer. In the manufacturing method of the electronic substrate in any one of Claim 1 to 3,
The method of manufacturing an electronic substrate, wherein the wiring pattern is connected to an electrode portion. In the manufacturing method of the electronic substrate of Claim 4,
At least a part of the wiring pattern forms a connection terminal. In the manufacturing method of the electronic substrate of Claim 5,
The connection terminal is formed by a bump electrode having a resin material as a core and at least a top portion covered with the wiring pattern. In the manufacturing method of the electronic substrate in any one of Claim 1 to 6,
A method of manufacturing an electronic substrate, wherein a semiconductor element is provided on the substrate and is electrically connected to the wiring pattern.

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