JP4845005B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device suitable for use in detection of a mask misalignment in a semiconductor manufacturing process and a method for manufacturing the same.

  With the miniaturization of semiconductor devices, high accuracy is required for mask alignment for each layer, and accurate measurement of mask misalignment is an important technique for manufacturing semiconductor devices.

  Therefore, an electrical inspection using a TEG (test element group) is performed as a method for detecting the displacement of the mask.

  An example of this method will be described with reference to FIG. In this method, a pair of contact holes 101 is formed in an insulating film deposited on a semiconductor substrate, and a reference wiring pattern 102 is formed on the upper layer so that the pair of contact holes 101 are completely covered. By detecting the electrical characteristics of the connected TEG, it is determined whether or not there is a displacement.

  However, in the above method, since the reference wiring pattern is formed so as to completely cover the contact hole, when the positional deviation of the reference wiring pattern is very small, the connection state between the contact hole and the reference wiring pattern changes. No change in the electrical characteristics of the TEG could be detected.

  The above-described method has been improved so that the positional deviation can be detected as a change in the electrical characteristics of the TEG even when the positional deviation of the reference wiring pattern is very small. Patent Document 1 discloses this improved method.

  This improved method will be described with reference to FIG. In this method, a plurality of pairs of contact holes 101a to 101h for measuring the displacement of the mask are opened around a predetermined circuit pattern 104. Then, the reference wiring patterns 102a to 102h having a width smaller than the diameter of the contact holes 101a to 101h are shifted to the circuit pattern 104 side with respect to the centers of the contact holes 101a to 101h above the pairs of contact holes 101a to 101h. Arrange. Thereafter, the electrical characteristics of the TEG connected to the contact holes 101a to 101h corresponding to the positional deviation between the contact holes 101a to 101h stored in advance and the reference wiring patterns 102a to 102h, and the actual electrical characteristics of the TEG And referring to the comparison result, the actual positional deviation between the contact holes 101a to 101h and the reference wiring patterns 102a to 102h is detected.

In this method, the width of the reference wiring pattern is smaller than the diameter of the contact hole, and the reference wiring pattern is disposed so that the center line in the length direction of the reference wiring pattern is shifted from the center of the contact hole. Even if the positional deviation is minute, the reference wiring pattern and the contact hole are disconnected. Therefore, it is possible to detect the displacement of the mask from the electrical conduction of the TEG even for a slight displacement.
JP 2001-176882 A

  However, in the method disclosed in Patent Document 1, two TEGs including a pair of contact holes and one reference wiring pattern are provided in order to detect misalignment in two different directions. Therefore, the area of the TEG with respect to the circuit pattern is large, and this large TEG area hinders miniaturization of the semiconductor device.

  Hereinafter, means for solving the problem will be described using the numbers used in (Best Mode for Carrying Out the Invention). These numbers are added to clarify the correspondence between the description of (Claims) and (Best Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  A semiconductor device according to the present invention includes a circuit pattern (4) provided on a semiconductor substrate, a contact hole pair (1) disposed around the circuit pattern, and an upper layer of an insulating film provided with the contact hole pair. And a reference wiring pattern (2) provided so as to be connected to the contact hole pair. Here, the reference wiring pattern includes a first portion (2a) extending in a first direction and a second portion (2b) connected to the first portion and extending in a second direction different from the first direction. ing.

  Since the reference wiring pattern includes a first portion extending in the first direction and a second portion connected to the first portion and extending in a second direction different from the first direction, a pair of contact holes and one reference A single TEG provided with a wiring pattern can appropriately detect misalignment in two directions of different masks.

  In the semiconductor device and the method of manufacturing the same according to the present invention, since the positional deviation in two different directions of the mask is appropriately detected by a single TEG, the area of the TEG is reduced, and as a result, the semiconductor device is miniaturized. .

  The best mode for carrying out a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the accompanying drawings.

  1 and 2 are plan views schematically showing a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a case where there is no displacement between the contact hole pair 1 and the reference wiring pattern 2, and FIG. 2 shows a case where there is a displacement between the contact hole pair 1 and the reference wiring pattern 2.

  The chip 5 includes a circuit pattern 4 and a plurality of check transistors 3. The circuit pattern 4 is disposed in the center portion of the chip 5, and the check transistor 3 is disposed around the circuit pattern 4.

  A Y direction perpendicular to the first side 5a of the chip outer peripheral frame and an X direction perpendicular to the second side 5b of the chip outer peripheral frame adjacent to the first side 5a of the chip outer peripheral frame are defined.

  Here, it is preferable to dispose the check transistors 3 at the four corners of the rectangular chip 5 in order to detect the displacement of the mask.

  The check transistor 3 includes TEGs (test element groups) 11 to 14 for detecting the displacement of the mask.

  The TEGs 11 to 14 include a contact hole pair 1 having a first contact hole 1 a and a second contact hole 1 b, and an L-shaped reference wiring pattern 2 provided on the contact hole pair 1.

  Typically, the contact hole pair 1 is formed in the insulating film on the semiconductor substrate, and the reference wiring pattern 2 is formed on the upper layer so as to be connected to the contact hole pair 1.

  The reference wiring pattern 2 includes a first portion 2a extending in the first direction and a second portion 2b connected to the first portion 2a and extending in a second direction different from the first direction. The first portion 2a is disposed corresponding to the first contact hole 1a, and the second portion 2b is disposed corresponding to the second contact hole 1b.

  If the first direction and the second direction are perpendicular to each other, misalignment in various directions can be efficiently detected by the TEGs 11 to 14.

  In the present embodiment, the first direction and the Y direction are perpendicular, and the second direction and the X direction are perpendicular. In addition, the reference wiring pattern 2 has the second partial center line 2d at the second contact hole so that the first partial center line 2c is shifted toward the circuit pattern 4 along the Y direction with respect to the center 1c of the first contact hole. It is arranged so as to be shifted toward the circuit pattern 4 along the X direction with respect to the center 1d. Such an arrangement is suitable for detecting misalignment of the mask in the X and Y directions.

  Furthermore, the fact that the width W1 of the first portion 2a is smaller than the diameter D1 of the first contact hole 1a and the width W2 of the second portion 2b is smaller than the diameter D2 of the second contact hole 1b is to detect a minute displacement. To make it easier. In particular, the width W1 is half of the diameter D1, the width W2 is half of the diameter D2, half of the first contact hole 1a overlaps the first portion 2a, and half of the second contact hole 1b is the second portion 2b. It is important that they overlap.

  Note that the amount of deviation of the center line of the reference wiring pattern 2 from the center of the contact hole pair 1 and the ratio between the diameter of the contact hole pair 1 and the width of the reference wiring pattern 2 depends on the amount of positional deviation of the mask to be detected. Can be set arbitrarily.

  A method for detecting misalignment of a semiconductor device according to this embodiment will be described below.

  The deviation of the reference wiring pattern 2 with respect to the contact hole pair 1 in the lithography process is 0 in the X and Y directions, 0 in the X direction, ± 0.01 μm, ± 0.02 μm, and 0 in the Y direction, ± 0.01 μm, ± In the case of 0.02 μm, the electrical characteristics of the TEGs 11 to 14 are calculated with theoretical values or are obtained in advance by measurement.

  Then, after forming the TEGs 11 to 14 including the contact hole pair 1 and the reference wiring pattern 2, the actual values obtained by measuring the electrical characteristics of the TEGs 11 to 14 are compared with the values obtained in advance. The amount of displacement of the mask is detected.

  For example, as shown in FIG. 2, when the masks of the contact hole pair 1 and the reference wiring pattern 2 are shifted in the Y direction, the second contact hole 1b and the reference wiring pattern 2 are in a connected state in the TEG 11 and TEG 14. However, the first contact hole 1a and the reference wiring pattern 2 are disconnected. At this time, the electrical characteristics of the TEG 11 and the TEG 14 change, so that it is possible to detect the positional deviation between the masks of the contact hole pair 1 and the reference wiring pattern 2.

  The semiconductor device and the manufacturing method thereof according to the present embodiment can be applied not only to misalignment in the X and Y directions, but also to misalignment due to rotation θ, shot expansion / contraction, and wafer expansion / contraction. Also in this case, the electrical characteristics of the TEG with respect to the positional deviation are calculated by theoretical values, or obtained by measurement, and the position in the PR process is compared by comparing the obtained value with the value of the electrical characteristics on the actual device. The amount of deviation can be detected.

FIG. 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention, and shows a case where there is no displacement. FIG. 2 is a plan view schematically showing the semiconductor device according to the embodiment of the present invention, and shows a case where there is a positional deviation. FIG. 3 is a plan view schematically showing a conventional TEG. FIG. 4 is a plan view schematically showing a conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Contact hole pair 1a ... 1st contact hole 1b ... 2nd contact hole 1c ... Center 1d of 1st contact hole ... Center 2 of 2nd contact hole ... Reference wiring pattern 2a ... 1st part 2b ... 2nd part 2c ... 1st partial center line 2d ... 2nd partial center line 3 ... check transistor 4 ... circuit pattern 5 ... chip 5a ... first side 5b of chip outer peripheral frame ... second side 11-14 of chip outer peripheral frame ... TEG
101, 101a to 101h ... contact holes 102, 102a to 102h ... reference wiring pattern 104 ... circuit pattern X ... arrow indicating X direction Y ... arrow indicating Y direction

Claims (4)

A circuit pattern provided on a semiconductor substrate;
A contact hole pair disposed around the circuit pattern and having a first contact hole and a second contact hole;
A reference wiring pattern provided on the upper layer of the insulating film provided with the contact hole pair so as to be connected to the contact hole pair;
The reference wiring pattern is
A first portion extending in a first direction parallel to the first side of the outer peripheral frame of the rectangular chip having the circuit pattern ;
A second portion connected to the first portion and extending in a second direction parallel to the second side of the outer peripheral frame adjacent to the first side ;
The reference wiring pattern has a center line extending in the first direction of the first portion shifted toward the circuit pattern along a direction perpendicular to the first direction with respect to the center of the first contact hole. A semiconductor device is arranged such that a center line extending in the second direction of the second portion is shifted toward the circuit pattern along a direction perpendicular to the second direction with respect to the center of the second contact hole. . A first width of the first portion is smaller than a first diameter of the first contact hole;
The semiconductor device according to claim 1, wherein a second width of the second portion is smaller than a second diameter of the second contact hole. The first part and the second part are arranged to form an L shape,
The first width is half of the first diameter;
The semiconductor device according to claim 2 , wherein the second width is half of the second diameter. A contact hole opening step of opening a contact hole pair having a first contact hole and a second contact hole so that the contact hole pair is arranged around a predetermined circuit pattern;
A reference wiring provided on the contact hole pair with a reference wiring pattern including a first part extending in a first direction and a second part connected to the first part and extending in a second direction different from the first direction A pattern placement step;
A measurement step of measuring electrical characteristics of a TEG (test element group) comprising the contact hole pair and the reference wiring pattern;
Position shift detection for detecting the position shift corresponding to the electrical characteristics measured in the measurement step with reference to data associating the position shift between the contact hole pair and the reference wiring pattern and the electrical characteristics. A method of manufacturing a semiconductor device.

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