JP4727638B2 - Method of manufacturing a chip resistor having a low resistance value - Google Patents

Description

    The present invention relates to a method of manufacturing a chip resistor having a low resistance value, for example, 1Ω or less.

  Conventionally, this type of chip resistor has been disclosed in, for example, Patent Document 1 and the like, in which a resistor is a base metal having a low resistance such as copper (hereinafter referred to as a low resistance metal). And a metal having a higher resistance than the metal of the base material (hereinafter referred to as a high-resistance metal) such as nickel. Among them, connection terminal electrodes are provided at both left and right ends of the rectangular parallelepiped along the longitudinal direction to be connected to a printed circuit board by soldering or the like, and at least a portion between the connection terminal electrodes of the resistor is an insulator. It is configured to cover with.

  In this type of chip resistor, the resistance value between the two connection terminal electrodes largely depends on the specific resistance of the alloy constituting the resistor, and the specific resistance of the alloy is higher than that of the high resistance metal. The ratio is low in proportion to the ratio of the low-resistance metal to the high-resistance metal so that the ratio is low when the ratio of the low-resistance metal is large and increases as the ratio of the high-resistance metal to the low-resistance metal increases. It increases in proportion to the ratio of high resistance metal to metal.

For this reason, in the conventional chip resistor, when the length dimension along the longitudinal direction of the rectangular parallelepiped of the resistor and the width dimension perpendicular to the longitudinal direction are determined in advance, both the connections are made. To lower the resistance value between the terminal electrodes, that is, the resistance value of the chip resistor,
(1). The alloy is an alloy in which the ratio of the low resistance metal to the high resistance metal is reduced.
(2). The plate thickness dimension of the resistor is increased.
Either one or both of these are employed.
JP 2001-118701 A

  However, in general, metal materials have a temperature coefficient of resistance that the resistance varies with temperature, and it is known that this temperature coefficient of resistance is higher for pure metals than for alloys. Yes.

  Therefore, in order to reduce the resistance value of the chip resistor, it is necessary to increase the proportion of the low-resistance metal (base metal) in the alloy constituting the resistor as in (1). Since this alloy approaches the purity of the low-resistance metal (base metal), there is a problem that the temperature coefficient of resistance in the chip resistor is increased.

  Further, in order to reduce the resistance value in the chip resistor, increasing the thickness of the resistor in the resistor as in (2) only increases the weight of the chip resistor. Alternatively, it is difficult to bend the both ends of the resistor in the longitudinal direction to the connection terminal electrode, and trimming adjustment for adjusting the resistance value to a predetermined value by engraving a trimming groove on the resistor is performed. There is a problem that it becomes extremely difficult.

  On the other hand, the temperature coefficient of resistance in metal materials is positive in the case of most pure metals, but in the case of an alloy in which a plurality of these pure metals are alloyed, a negative resistance temperature coefficient is given to some of the alloys. If an alloy having this negative resistance temperature coefficient is used for the resistor, this negative resistance temperature coefficient appears as a negative resistance temperature coefficient as it is in the chip resistor. That was also a problem.

  An object of the present invention is to provide a method of manufacturing a chip resistor that solves these problems.

In order to achieve this technical problem , claim 1 of the present invention provides:
“A high-resistance metal and a low-resistance metal alloy with negative resistance temperature coefficient , and a resistor alloy plate made by aligning and integrating a large number of resistors made into a rectangular parallelepiped, and a metal having a lower resistance than this A process of making a laminated metal plate by laminating and joining a metal plate for a connection terminal electrode using
After forming a pure metal plating layer having a positive resistance temperature coefficient on the upper surface of the alloy plate for resistor in the laminated material metal plate, the portion other than the connection terminal electrode is removed from the metal plate for connection terminal electrode, Alternatively, after removing the portion other than the connection terminal electrode from the metal plate for connection terminal electrode in the laminated material metal plate , a pure metal plating layer having a positive resistance temperature coefficient is formed on the upper surface of the alloy plate for resistor. Process,
Coating a portion of the lower surface of the resistor alloy plate other than the two connection terminal electrodes with an insulator; and
Cutting the laminated material metal plate for each resistor;
And comprising. "
It is characterized by that.
Claim 2
“In the first aspect of the present invention, prior to the step of forming the plating layer, a step of providing a partial reduction portion of a cross-sectional area in each resistor in the resistor alloy plate is provided. The step of forming the step includes the step of filling the partial reduction portion of the cross-sectional area.
It is characterized by that.

  According to the present invention, a chip resistor is formed on a surface of a resistor made of an alloy of a high resistance metal and a low resistance metal, and a plated layer of pure metal having a resistance lower than that of the alloy is formed on the surface of the resistor. It is possible to manufacture by making a connection terminal electrode made of metal having a resistance lower than that of the alloy constituting the resistor at both ends of the back surface of the resistor.

  According to this configuration, the resistance value between both connection terminal electrodes is lower by the amount of the pure metal plating layer and the low resistance both connection terminal electrodes than when the resistor is composed of an alloy alone. The resistance value between the two connection terminal electrodes, that is, the resistance value in the chip resistor, is obtained without increasing the ratio of the low resistance metal to the high resistance metal in the alloy constituting the resistor, and in the resistor. Since the plate thickness can be lowered without increasing the thickness, the resistance temperature coefficient increases when the resistance value of the chip resistor is lowered with the same length and width dimensions. Further, it is possible to reliably avoid the trimming adjustment of the resistance value and the bending process of the connection terminal electrode and the increase in weight.

Therefore, according to the manufacturing method of the present invention, a large number of chip resistors having the above-described configuration can be manufactured simultaneously at low cost.
In addition, according to the present invention, the negative resistance temperature coefficient of the resistor can be offset by the positive resistance temperature coefficient of the plating layer formed on the surface of the resistor, so that the chip resistor has a negative resistance temperature coefficient. Appearance can be avoided, or negative resistance temperature coefficient appearing on the chip resistor can be reduced.
According to the second aspect of the present invention, the resistance value of the chip resistor can be further reduced to a very small resistance value.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 and 2 show a chip resistor 11 according to the first embodiment.

  The chip resistor 11 includes a resistor 12 formed in a rectangular parallelepiped having a length dimension of L, a width dimension of W, and a thickness dimension of T, and connection terminal electrodes fixed to both ends of the lower surface of the resistor body 12. 13, an upper surface insulator 14 that covers the entire upper surface of the resistor 12, and a lower surface insulator 14 ′ that covers a portion of the lower surface of the resistor 12 between the connection terminal electrodes 13.

The resistor 12 is formed on a base metal having a low resistance (hereinafter referred to as a low resistance metal) such as a copper / nickel alloy, a nickel / chromium alloy, or an iron / chromium alloy. metal having a higher resistance than the metal of the timber Ri alloy der made by adding (hereinafter, referred to as the high-resistance metal), the alloy that has a negative temperature coefficient of resistance.

  On the other hand, both connection terminal electrodes 13 are made of an alloy having a lower resistance than the alloy constituting the resistor 12 or a metal made of a pure metal such as copper.

Then, a pure metal plating layer 15 having a positive temperature coefficient of resistance such as copper or silver having a lower resistance than the alloy constituting the resistor 12 is formed on the surface of the resistor 12 over the entire surface. Form over.

  By forming this plating layer 15, as in the case of the first embodiment, the resistance value between the connection terminal electrodes 13 is higher than that in the case where the resistor 12 is made of only an alloy. Therefore, the resistance value between the connection terminal electrodes 13, that is, the resistance value in the chip resistor 11, is reduced by the metal constituting the resistor 12. It is possible to reduce the alloy without increasing the ratio of the low-resistance metal to the high-resistance metal and without increasing the thickness T of the resistor 12.

  The resistance value of the chip resistor 11 is formed by dividing the plating layer 15 formed on the surface of the resistor 12 by a length S as shown in FIG. 3, or by forming a narrow width as shown in FIG. By doing so, the resistance value can be arbitrarily set by the plating layer 15 so that it can be increased.

  In addition to the above-described configuration, as shown in FIGS. 5 and 6, at least one slit groove 17 extending laterally from the longitudinal side surface is formed in the portion of the resistor 12 between the connection terminal electrodes 13. The sectional area of the resistor 12 is partially reduced by providing a through hole or the like, and a partially reduced portion of the sectional area such as the slit groove 17 or the through hole is provided as a resistor. It is configured to be filled with a plating layer 15 formed on the surface of 12.

  Thereby, the resistance value in the chip resistor 11 can be set to a lower and minute resistance value.

  By the way, since the resistance temperature coefficient of the pure metal of the plating layer 15 is generally positive, the pure metal plating layer 15 having the positive resistance temperature coefficient is made of, for example, 43 to 45 wt% of nickel and the rest. By forming the resistor 12 made of an alloy metal having a negative resistance temperature coefficient such as a copper-nickel alloy of copper, the negative resistance temperature coefficient in the resistor 12 is applied to the surface of the resistor 12. Since the positive resistance temperature coefficient in the formed plating layer 15 can be offset, it is possible to avoid the negative resistance temperature coefficient from appearing in the chip resistor 11 or to reduce the negative resistance temperature coefficient appearing in the chip resistor 11. it can.

  In manufacturing the chip resistor 11 according to the above embodiment, the following method is adopted.

  That is, first, as shown in FIGS. 7 and 8, there is prepared a resistor alloy plate B1 in which a large number of the resistors 12 are aligned in the vertical and horizontal directions, and this resistor alloy plate B1 is prepared. A laminated material metal plate B is manufactured by overlapping and joining a connecting terminal electrode metal plate B2 for forming the connecting terminal electrode 13 on the lower surface of the metal plate, and the resistor alloy in the laminated material metal plate B is manufactured. A plated layer 15 made of pure metal is formed on each of the resistor elements 12 on the upper surface of the plate B1.

  When each of the resistors 12 is provided with a partially reduced portion having a cross-sectional area such as a slit groove 17 or a through hole as shown in FIGS. 5 and 6, the plating layer 15 Is formed, the plating layer 15 fills a partially reduced portion of the cross-sectional area.

  Next, as shown in FIG. 9 and FIG. 10, in the connection terminal electrode metal plate B2 in the laminated material metal plate B, the portions of the connection terminal electrodes 13 at both ends of the resistor 12 are left, and the other portions are replaced. Remove by cutting or the like.

  Next, as shown in FIGS. 11 and 12, the entire upper surface of the resistor alloy plate B1 of the laminated material metal plate B is covered with the upper surface insulator 14, while the lower surface of the resistor alloy plate B1 is covered. Of these, the portion between the connection terminal electrodes 13 is covered with a lower surface insulator 14 '.

  Finally, the laminated material metal plate B is cut along a vertical cutting line B ′ and a horizontal cutting line B ″ partitioning each resistor 12, so that FIGS. The chip resistor 11 having the structure shown in FIG.

  Further, in this manufacturing method, the step of forming the plated layer 15 of pure metal on the upper surface of the resistor alloy plate B1 in the laminated material metal body B includes the metal for connection terminal electrodes in the laminated material metal body B. You may make it carry out after the process of removing parts other than the connection terminal electrode 13 among board B2 by cutting.

It is a perspective view which shows the chip resistor by embodiment of this invention. FIG. 2 is a sectional view taken along line II-II in FIG. 1. It is a perspective view which shows the 1st modification in the said chip resistor. It is a perspective view which shows the 2nd modification in the said chip resistor. It is a fragmentary top view which shows the 3rd modification in the said chip resistor. FIG. 6 is a sectional view taken along line VI-VI in FIG. 5. It is a perspective view which shows the 1st process at the time of manufacture of the said chip resistor. FIG. 8 is an enlarged sectional view taken along line VIII-VIII in FIG. 7. It is a perspective view which shows the 2nd process at the time of manufacture of the said chip resistor. FIG. 10 is an enlarged sectional view taken along line XX in FIG. 9. It is a perspective view which shows the 3rd process in the case of manufacture of the said chip resistor. FIG. 12 is an enlarged sectional view taken along line XII-XII in FIG. 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Chip resistor 12 Resistor 13 Connection terminal electrode 14 Upper surface insulator 14 'Lower surface insulator 15 Plating layer

Claims (2)

An alloy plate for a resistor formed by integrating a plurality of resistors made of a rectangular parallelepiped with an alloy having a negative resistance temperature coefficient of a high resistance metal and a low resistance metal, and a metal having a lower resistance than this A process of making a laminated metal plate by laminating and joining the metal plate for the connection terminal electrode used,
After forming a pure metal plating layer having a positive resistance temperature coefficient on the upper surface of the alloy plate for resistor in the laminated material metal plate, the portion other than the connection terminal electrode is removed from the metal plate for connection terminal electrode, Alternatively, after removing the portion other than the connection terminal electrode from the metal plate for connection terminal electrode in the laminated material metal plate , a pure metal plating layer having a positive resistance temperature coefficient is formed on the upper surface of the alloy plate for resistor. Process,
Coating a portion of the lower surface of the resistor alloy plate other than the two connection terminal electrodes with an insulator; and
Cutting the laminated material metal plate for each resistor;
A method of manufacturing a chip resistor having a low resistance value. 2. The method according to claim 1, further comprising a step of providing a partial reduced portion of a cross-sectional area on each resistor in the resistor alloy plate prior to the step of forming the plating layer. A method of manufacturing a chip resistor having a low resistance value, wherein the forming step includes a step of filling a partially reduced portion of the cross-sectional area.

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