JP4717519B2 - Step-down switching regulator, its control circuit, and electronic equipment using the same - Google Patents

Description

  The present invention relates to a step-down switching regulator, and more particularly to a control technology for a synchronous rectification switching regulator.

Various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers in recent years are equipped with microcomputers that perform digital signal processing. The power supply voltage required for driving such a microcomputer has been reduced with the miniaturization of the semiconductor manufacturing process, and there is one that operates at a low voltage of 1.5 V or less.
On the other hand, a battery such as a lithium ion battery is mounted on such an electronic device as a power source. Since the voltage output from the lithium ion battery is about 3 V to 4 V, if this voltage is supplied to the microcomputer as it is, useless power consumption occurs. Therefore, a step-down switching regulator or a series regulator is used. In general, the battery voltage is stepped down to a constant voltage and supplied to a microcomputer.

As a step-down switching regulator, there are a method using a rectifying diode (hereinafter referred to as a diode rectifying method) and a method using a rectifying transistor instead of a diode (hereinafter referred to as a synchronous rectifying method). In the former case, there is an advantage that high efficiency can be obtained when the load current flowing through the load is low. However, since a diode in addition to the inductor and the output capacitor is required outside the control circuit, the circuit area becomes large. In the latter case, the efficiency when the current supplied to the load is small is inferior to the former, but since a transistor is used instead of a diode, it can be integrated inside the LSI, and the circuit area including peripheral components As a result, downsizing is possible. When an electronic device such as a cellular phone is required to be downsized, a switching regulator using a rectifying transistor (hereinafter referred to as a synchronous rectification switching regulator) is often used.
For example, Patent Documents 1 and 2 disclose synchronous rectification type and diode rectification type switching regulators.

JP 2004-32875 A JP 2002-252971 A

  Here, when a load connected to the step-down switching regulator is temporarily short-circuited, an overcurrent flows. This overcurrent is supplied to the load via the inductor. When a large current flows through the inductor, the inductor cannot hold any more magnetic flux, that is, becomes saturated. When the inductor is saturated, the inductance component decreases and approaches a simple conductor. At this time, the current flowing through the inductor flows through the switching transistor, and the current increases. When this current increases, it affects the reliability of the switching transistor and the load.

  The present invention has been made in view of such problems, and an object thereof is to provide a control circuit for a step-down switching regulator capable of detecting and protecting an overcurrent state.

  One embodiment of the present invention relates to a control circuit for a step-down switching regulator. The control circuit includes a switching transistor and a synchronous rectification transistor connected in series between the input terminal and the ground, an output stage that outputs the voltage at the connection point of the two transistors to the switching regulator output circuit as a switching voltage, and switching First and second gate voltages to be applied to the gates of the switching transistor and the synchronous rectification transistor based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the regulator output circuit approaches a predetermined reference voltage A comparison circuit that compares a voltage across the switching transistor with a predetermined threshold voltage and outputs a comparison signal of a predetermined level when the voltage across the switching transistor exceeds the threshold voltage A comparison signal of a predetermined level is output from the comparison unit During this period, the first protection circuit for forcibly turning off the switching transistor and the comparison signal output from the comparison unit are monitored, and when a predetermined level is continuously output for a predetermined first period, the control circuit is stopped. A second protection circuit to be in a state.

The control circuit detects the current flowing through the switching transistor by monitoring the voltage across the switching transistor. The circuit can be protected by determining that the voltage across the switching transistor exceeds the threshold voltage as an overcurrent state and forcibly turning off the switching of the switching transistor. According to this aspect, the first protection circuit can suitably perform circuit protection for each cycle. Further, the comparison signal is monitored by the second protection circuit, and when the overcurrent state continues for the first period, it is determined as a long-term short-circuit state, the control circuit is stopped, and the output voltage of the switching regulator is lowered. At the same time, current consumption in the circuit can be suppressed.
Here, “compare the voltage across the switching transistor with a predetermined threshold voltage” refers to comparing the voltage across the switching transistor directly with the threshold voltage, as well as the voltage across the switching transistor. This includes the case of indirectly comparing with the threshold voltage.

The comparison unit includes a voltage comparator that compares the voltage across the switching transistor and a threshold voltage, and a latch circuit that is set by the output of the voltage comparator and is reset for each period of the pulse width modulation signal. The first protection circuit may forcibly turn off the switching transistor based on the output signal of the latch circuit.
By resetting the latch circuit for each cycle of the pulse width modulation signal, the switching transistor is forcibly turned off within one cycle. Therefore, the instantaneous overcurrent state can be returned to the normal current state. It can be done in a short time.

  The first protection circuit may change the logic value of the pulse width modulation signal. When the logic value of the pulse width modulation signal is changed, the synchronous rectification transistor is turned on during the period in which the switching transistor is forcibly turned off, so that an increase in output voltage can be suitably suppressed.

  The first protection circuit may change an error voltage between the output voltage of the switching regulator and the reference voltage. The pulse width modulation signal can be changed by changing the error voltage input to the voltage comparator used to generate the pulse width modulation signal.

The second protection circuit may include an integrator that integrates the comparison signal output from the comparison unit, and a first time measurement circuit that measures a time during which the output signal of the integrator is held at a predetermined level. Even if the current that flows through the switching transistor decreases for a moment despite the overcurrent state and the comparison signal is not at the predetermined level, the overcurrent state is maintained by removing the high-frequency component of the comparison signal using the integrator. Can be determined.
The first time measurement circuit may include a digital filter to which the output signal of the integration circuit is input, and the first period may be measured by the digital filter.

The second protection circuit further includes a second time measurement circuit that starts measurement of a predetermined second period in response to transition of the output of the first time measurement circuit, and a second period measured by the second time measurement circuit. During this time, the present control circuit may be stopped.
In this case, if the overcurrent state continues, after the first protection circuit performs overcurrent protection for each period in the first period, the control circuit is stopped by the second protection circuit in the second period. If the overcurrent state continues for a long time, it becomes an intermittent operation in which the first period and the second period are alternately repeated, and the overcurrent protection is suitably performed and the current path is completely cut off in the second period, thereby wasting power consumption. Can be suppressed.

  The integrator may generate a signal that quickly follows one edge of the comparison signal and gently follows the other edge, and outputs the signal to the first time measurement circuit. The integrator may include a transistor having a comparison signal input to the control terminal, an RC filter connected to one end of the transistor, and a constant current source connected to a connection point between the transistor and the RC filter.

  The comparison unit further includes a detection transistor and a detection resistor connected in series so as to form a path parallel to the switching transistor between the drain and source of the switching transistor and having a first gate voltage input to the gate. May compare the voltage across the detection resistor with the threshold voltage. By providing a detection transistor and a detection resistor in parallel with the switching transistor, and monitoring the voltage drop at the detection resistor, the current flowing through the switching transistor can be indirectly monitored, and an overcurrent state can be suitably detected. it can.

  The control circuit may be integrated on a single semiconductor substrate.

Another aspect of the present invention is a step-down switching regulator. This step-down switching regulator supplies a switching voltage to a switching regulator output circuit including an output capacitor having one end grounded, an inductor having one end connected to the other end of the output capacitor, and the other end of the inductor. And a voltage at the other end of the output capacitor.
According to this aspect, when the load connected to the step-down switching regulator is short-circuited, it is possible to prevent the overcurrent from constantly flowing.

Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery and a step-down switching regulator that steps down and outputs the voltage of the battery.
According to this aspect, the step-down switching regulator can be protected from overcurrent, heat generation of the entire electronic device can be suppressed, and when the overcurrent state continues for a long time, an intermittent operation is performed. Consumption can be reduced.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the step-down switching regulator control circuit of the present invention, overcurrent protection can be realized.

FIG. 1 is a block diagram showing a configuration of an electronic device equipped with a step-down switching regulator according to an embodiment. The electronic device 300 is, for example, a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360.
The battery 310 is a lithium ion battery, for example, and outputs about 3 to 4 V as the battery voltage Vbat.
The analog circuit 330 includes high-frequency circuits such as a power amplifier, an antenna switch, an LNA (Low Noise Amplifier), a mixer, and a PLL (Phase Locked Loop), and includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. . The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V.
The microcomputer 350 is a block that comprehensively controls the entire electronic device 300 and operates with a power supply voltage of 1.5V.
The LED 360 includes RGB three-color LEDs (Light Emitting Diodes) and is used as a liquid crystal backlight or illumination, and a driving voltage of 4 V or more is required for driving.

The power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel. For the analog circuit 330, digital circuit 340, microcomputer 350, and LED 360, Supply an appropriate power supply voltage.
The step-down switching regulator according to this embodiment can be suitably used for such a power supply device 320. Hereinafter, the configuration of the step-down switching regulator according to the present embodiment will be described in detail.

FIG. 2 is a circuit diagram showing a configuration of the step-down switching regulator 200 according to the embodiment. The step-down switching regulator 200 is a synchronous rectification step-down switching regulator, and includes a control circuit 100 and a switching regulator output circuit 110. The control circuit 100 is an LSI chip integrated on a single semiconductor substrate, and a switching transistor M1 functioning as a switching element and a synchronous rectification transistor M2 are incorporated in the control circuit 100.
The switching regulator output circuit 110 includes an output capacitor C1 and an inductor L1. One end of the output capacitor C1 is grounded, and the other end is connected to the load RL and the inductor L1. The inductor L1 is connected to the control circuit 100 and applied with the switching voltage Vsw.

The step-down switching regulator 200 controls the current flowing through the inductor L1 by the control circuit 100, steps down the battery voltage Vbat by charging the output capacitor C1, and supplies the voltage appearing at the output capacitor C1 to the load RL. .
Hereinafter, the voltage supplied to the load RL is referred to as an output voltage Vout, and the current flowing through the load RL is referred to as a load current IL.

  The control circuit 100 includes an input terminal 102, a switching terminal 104, and a voltage feedback terminal 106 as input / output terminals. A battery 310 is connected to the input terminal 102, and a battery voltage Vbat is input as an input voltage. The switching terminal 104 is connected to the inductor L1 and outputs a switching voltage Vsw generated inside the control circuit 100. The voltage feedback terminal 106 is a terminal to which the output voltage Vout applied to the load RL is fed back.

  The control circuit 100 includes a driver circuit 10, a PWM control unit 20, a comparison unit 30, a forced off transistor 40 as a first protection circuit, a second protection circuit 50, a switching transistor M1, and a synchronous rectification transistor M2.

The switching transistor M1 is a P-channel MOS transistor, and has a source connected to the input terminal 102 and a drain connected to the switching terminal 104. The synchronous rectification transistor M2 is an N-channel MOS transistor, the source is grounded, and the drain is connected to the drain of the switching transistor M1 and the switching terminal 104. The back gate of the synchronous rectification transistor M2 is grounded.
The switching transistor M1 and the synchronous rectification transistor M2 are connected in series between the input terminal 102 to which the battery voltage Vbat is applied and the ground, and the control circuit 100 uses the voltage at the connection point of the two transistors as the switching voltage Vsw. Is applied to one end of an inductor L1 connected to the outside via a switching terminal 104.

The PWM control unit 20 controls a pulse width modulation signal (hereinafter, referred to as duty ratio) that defines the duty ratio of the on-time of the switching transistor M1 and the synchronous rectification transistor M2 so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined reference voltage. PWM signal Vpwm). The output voltage Vout of the step-down switching regulator 200 is input to the PWM control unit 20 via the voltage feedback terminal 106.
The resistors R1 and R2 divide the output voltage Vout, and output the output voltage Vout ′ multiplied by R2 / (R1 + R2) to the inverting input terminal of the error amplifier 22. The reference voltage Vref is input to the non-inverting input terminal of the error amplifier 22, and an error between the output voltage Vout ′ and the reference voltage Vref is amplified and output as an error voltage Verr.

  The oscillator 26 oscillates at a predetermined frequency and outputs a periodic voltage Vosc having a triangular wave shape or a sawtooth wave shape. The first comparator 24 compares the periodic voltage Vosc and the error voltage Verr, and outputs a PWM signal Vpwm that is at a low level when Vosc> Verr and at a high level when Vosc <Verr. This PWM signal Vpwm is a pulse width modulated signal having a constant cycle time and a period of high level and low level changing according to the output voltage Vout ′.

Based on the PWM signal Vpwm output from the PWM control unit 20, the driver circuit 10 includes a first gate voltage Vg1 to be applied to the gate of the switching transistor M1 and a second gate voltage to be applied to the gate of the synchronous rectification transistor M2. Vg2 is generated. In the present embodiment, the first gate voltage Vg1 and the second gate voltage Vg2 are generated by inverting the logic value of the PWM signal Vpwm.
The switching transistor M1 is turned on when the first gate voltage Vg1 is at a low level and turned off when the first gate voltage Vg1 is at a high level. The synchronous rectification transistor M2 is turned on when the second gate voltage Vg2 is at a high level, and turned off when the second gate voltage Vg2 is at a low level.
As described above, the driver circuit 10 sets the ratio of the time during which the switching transistor M1 and the synchronous rectification transistor M2 are turned on based on the high-level and low-level duty ratios of the PWM signal Vpwm, and alternates the two transistors. Turn on and off. In order to prevent the switching transistor M1 and the synchronous rectification transistor M2 from being turned on at the same time and causing a through current to flow, the driver circuit 10 sets a period (dead time) during which the switching transistor M1 and the synchronous rectification transistor M2 are simultaneously turned off. You may provide for every period.

The comparison unit 30 receives the switching voltage Vsw and the battery voltage Vbat. The comparison unit 30 compares the voltage across the switching transistor M1 (hereinafter referred to as the monitoring voltage) ΔV = (Vbat−Vsw) with the threshold voltage Vth. When the monitoring voltage ΔV exceeds the threshold voltage Vth, the comparison unit 30 The comparison signal Vcmp is output.
The comparison unit 30 includes a second comparator 32, a voltage source 34, and a latch circuit 36. The voltage source 34 generates a predetermined threshold voltage Vth. A voltage (Vbat−Vth) is input to the + input terminal of the second comparator 32. The switching voltage Vsw is input to the negative input terminal of the second comparator 32.

  The monitoring voltage ΔV is given by the product of the on-resistance Ron1 of the switching transistor M1 and the current Ipeak flowing through the switching transistor M1. That is, ΔV = Ron1 × Ipeak is established. Since Ipeak = ΔV / Ron1, the comparison unit 30 can detect a state where the current Ipeak flowing through the switching transistor M1 exceeds the threshold current given by Ith = Vth / Ron1. The threshold current Ith is set according to the allowable current of the switching transistor M1. For example, when the maximum value of the current flowing through the switching transistor M1 during normal operation is about Ipeak = 500 mA, the threshold current Ith is set to about 1A.

  The latch circuit 36 is a D flip-flop, and the comparison signal Vcmp output from the second comparator 32 is input to the data terminal, and the periodic voltage Vosc output from the oscillator 26 is input to the clock terminal. The latch circuit 36 latches the comparison signal Vcmp output from the comparison unit 30, is reset by the periodic voltage Vosc that is an output signal of the oscillator 26 used to generate the PWM signal Vpwm, and latches the comparison signal Vcmp again. The latch circuit 36 may be configured using an RS flip-flop or the like. The comparison unit 30 outputs the output of the latch circuit 36 as the comparison signal SIG1 to the gate of the forced-off transistor 40 and the second protection circuit 50 in the subsequent stage.

The forced off transistor 40 is a first protection circuit, and is an N-channel MOS transistor whose drain is connected to the output of the error amplifier 22 and whose source is grounded. When the comparison signal SIG1 output from the comparison unit 30 is at a high level, the forced-off transistor 40 is turned on, and at this time, the output voltage of the error amplifier 22, that is, the error voltage Verr becomes 0V. When the error voltage Verr becomes 0V, the PWM signal Vpwm output from the first comparator 24 becomes a low level. That is, the forcible off transistor 40 as the first protection circuit forcibly turns off the switching transistor M1 by changing the logical value of the pulse width modulation signal Vpwm.
As described above, the driver circuit 10 generates the first gate voltage Vg1 and the second gate voltage Vg2 based on the duty ratio of the PWM signal Vpwm. When the PWM signal Vpwm is at a high level, the switching transistor M1 is turned on. Therefore, the driver circuit 10 forcibly turns off the switching transistor M1 while the comparison signal Vcmp is latched at a high level in the latch circuit 36.

  The second protection circuit 50 receives the comparison signal SIG1 output from the comparison unit 30. The second protection circuit 50 monitors the comparison signal SIG1, and stops the control circuit 100 when detecting that the high level has continued for a predetermined first period Tp1. The first period Tp1 is desirably set sufficiently longer than the period time of the periodic voltage Vosc output from the oscillator 26. For example, when the period time is about 1 μs, the first period Tp1 is set to about 2 ms.

FIG. 3 is a circuit diagram showing a configuration of the second protection circuit 50. The second protection circuit 50 includes an integrator 52, a digital filter 62, a timer circuit 64, and an inverter 66. Inverter 66 inverts the logical value of comparison signal SIG 1 and outputs the result to integrator 52.
The integrator 52 integrates the comparison signal SIG <b> 1 ′ output from the inverter 66 and outputs it to the digital filter 62. The integrator 52 generates a signal SIG2 that follows the rising edge of the comparison signal SIG1 ′ at high speed and gently follows the falling edge. The integrator 52 includes a transistor 54, a constant current source 56, a resistor 58, and a capacitor 60.

The transistor 54 is a P-channel MOS transistor, and the comparison signal SIG1 ′ is input to the gate, and the power supply voltage Vdd is input to the source. The resistor 58 and the capacitor 60 constitute an RC filter and are connected to the drain of the transistor 54. The constant current source 56 is connected to a connection point between the transistor M54 and the RC filter.
When the comparison signal SIG1 becomes high level, the gate of the transistor 54 becomes low level and the transistor 54 is turned on. As a result, the output signal SIG2 of the integrator 52 rises according to the CR time constant. When the comparison signal SIG1 becomes low level, the comparison signal SIG1 ′ input to the gate of the transistor 54 becomes high level, the transistor 54 is turned off, and the charge stored in the capacitor 60 is discharged by the constant current source 56, and the integrator The output signal SIG2 of 52 gradually decreases.

The digital filter 62 functions as a first time measurement circuit that measures the time during which the output signal SIG2 of the integrator 52 is held at a high level. The digital filter 62 sets the output signal SIG3 to high level when the output signal SIG2 becomes high level for a predetermined first period Tp1 or more.
The timer circuit 64 is a second time measurement circuit that starts measuring a predetermined second period Tp2 when the output signal SIG3 of the digital filter 62 transitions from a low level to a high level. The second period Tp2 is desirably set longer than the first period Tp1, and is set to about 18 ms, for example. The second protection circuit 50 sets the enable signal EN to the low level during the second period Tp2 measured by the timer circuit 64. The enable signal EN output from the timer circuit 64 is used for controlling the operation state of the control circuit 100.

Hereinafter, the operation of the control circuit 100 according to the present embodiment will be described with reference to FIGS. FIG. 4 is a time chart showing an operation state of the control circuit 100 according to the present embodiment.
First, the overcurrent protection by the forced off transistor 40 as the first protection circuit will be described with reference to FIG. The time chart of FIG. 4 shows an overcurrent state in which the load current IL is very large. FIG. 4 shows, in order from the top, the error voltage Verr and the periodic voltage Vosc, the PWM signal Vpwm, the monitoring voltage ΔV, the comparison signal Vcmp, the comparison signal SIG1, and the first gate voltage Vg1.
The switching transistor M1 is turned off when the first gate voltage Vg1 is at a high level, and turned on when the first gate voltage Vg1 is at a low level. That is, in the figure, Ton1 indicates a period during which the switching transistor M1 is on.

  The duty ratio of the PWM signal Vpwm is controlled so that the output voltage Vout of the step-down switching regulator 200 approaches a predetermined voltage, and becomes a high level when Verr> Vosc, and a low level when Verr <Vosc. The first gate voltage Vg1 is generated based on the PWM signal Vpwm. The on / off state of the switching transistor M1 is controlled by the first gate voltage Vg1, and the switching voltage Vsw repeats a high level and a low level. During the period from time T0 to time T1, the driver circuit 10 drives the switching transistor M1 and the synchronous rectification transistor M2 based on the PWM signal Vpwm.

  At time T1, the load RL is short-circuited and the load current IL increases. Along with this, the monitoring voltage ΔV increases. When the monitoring voltage ΔV exceeds the threshold voltage Vth at time T2, the comparison signal Vcmp output from the second comparator 32 becomes high level. When the comparison signal Vcmp becomes high level, the latch circuit 36 is set, and the comparison signal SIG1 output from the comparison unit 30 becomes high level. When the comparison signal SIG1 becomes high level and the forced-off transistor 40 is turned on, the error voltage Verr is fixed near 0V, and the PWM signal Vpwm is forcibly set to low level. That is, the high time TH of the pulse width signal Vpwm is shorter than the on-time TH ′ when it is generated based on the error voltage Verr ′ indicated by the broken line. This means that the ON time Ton1 of the switching transistor M1 is shortened and the ON time of the synchronous rectification transistor M2 is increased. When the switching transistor M1 is turned off and the synchronous rectification transistor M2 is turned on at time T2, the current flowing through the inductor L1 decreases, and the monitoring voltage ΔV starts to drop.

  When the monitoring voltage ΔV becomes lower than the threshold voltage Vth at time T3, the comparison signal Vcmp becomes low level. When the periodic voltage Vosc, which is the output of the oscillator 26, rises to the level Vx at time T4, the latch circuit 36 is reset, and the comparison signal SIG1 becomes low level. When the comparison signal SIG1 becomes low level, the forced-off transistor 40 is turned off, and the error voltage Verr is released from the fixed state of 0V. Thereafter, when Verr <Vosc at time T5, the PWM signal Vpwm becomes high level, and the driver circuit 10 sets the first gate voltage Vg1 to low level and turns on the switching transistor M1.

Thus, the control circuit 100 according to the present embodiment monitors the monitoring voltage ΔV that is the voltage across the switching transistor M1. Since the monitoring voltage ΔV is proportional to the current flowing through the switching transistor M1, an overcurrent state can be detected by comparing with the threshold voltage Vth.
When an overcurrent state is detected with ΔV> Vth, the switching transistor M1 is forcibly turned off by the forcible off transistor 40, which is the first protection circuit, and the current supply path is cut off. Therefore, the switching transistor M1 itself, The inductor L1 or the load RL can be suitably protected.
Further, the forced off state of the switching transistor M1 in the overcurrent state is canceled for each cycle by the periodic voltage Vosc output from the oscillator 26. For this reason, even when the load is short-circuited momentarily and a large current flows, overcurrent detection and overcurrent protection are performed every cycle. Can return.

  Next, overcurrent protection by the second protection circuit 50 will be described with reference to FIG. FIG. 5 shows, in order from the top, the PWM signal Vpwm, the monitoring voltage ΔV, the comparison signal Vcmp, the comparison signal SIG1, the output signal SIG2 of the integrator 52, the output signal SIG3 of the digital filter 62, and the enable signal EN. At time T0, the load RL is short-circuited and enters an overcurrent state. This overcurrent state is detected for each cycle by the comparison unit 30 as described above. In the overcurrent state, as described with reference to FIG. 4, the comparison signal Vcmp and the comparison signal SIG1 repeat high and low levels every period. Since the transistor 54 in FIG. 3 is turned on while the comparison signal SIG1 is at a high level, the output signal SIG2 of the integrator 52 rises. Further, since the transistor 54 in FIG. 3 is turned off while the comparison signal SIG1 is at the low level, the charge of the capacitor 60 is discharged by the constant current source 56, and the output signal SIG2 of the integrator 52 is lowered. Since the discharge speed is set moderately, as shown in FIG. 5, when the overcurrent state continues, the output signal SIG2 of the integrator 52 continues to maintain a high level. The output signal SIG3 of the digital filter 62 becomes high level at time T1 after the elapse of a predetermined first period Tp1 from time T0. When the output signal SIG3 becomes high level, the timer circuit 64 sets the enable signal EN, which is the output thereof, to low level, and starts time measurement. When the enable signal EN becomes a low level, the control circuit 100 is stopped. In the stop state, the control circuit 100 stops power supply to unnecessary circuits, and stops the switching operation of the switching transistor M1 and the synchronous rectification transistor M2.

The timer circuit 64 returns the enable signal EN to the high level at the time T2 after the elapse of the predetermined second period Tp2 from the start of the time measurement at the time T1. When the enable signal EN becomes high level, the control circuit 100 returns to normal operation. If the short circuit state of the load RL is maintained at this time, the state returns to the state at time T0 in FIG. Therefore, the control circuit 100 performs an intermittent operation that alternately repeats the first period Tp1 protected by the first protection circuit and the second period Tp2 in which the control circuit 100 is stopped.
In addition, when the load RL is released from the short-circuit state during the stop period from the time T1 to the time T2, the normal step-down operation can be resumed from the time T2.

  Thus, according to the control circuit 100 according to the present embodiment, the circuit protection can be performed for each cycle by the forced off transistor 40 which is the first protection circuit, and an overcurrent state occurs in a very short time. Therefore, the step-down switching regulator 200 can be suitably protected. In addition, by providing the second protection circuit 50, when the overcurrent state continues for a long time, an intermittent operation in which the first period Tp1 and the second period Tp2 are alternately repeated is performed, and the overcurrent protection is suitably performed and the second period By completely interrupting the current path at Tp2, wasteful power consumption can be suppressed.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

FIG. 6 is a circuit diagram showing a modification of the control circuit 100, and shows the configuration of the comparison unit 30. In the subsequent drawings, the same or equivalent components as those already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
In the above-described embodiment, the voltage across the switching transistor M1 is directly monitored as the monitoring voltage ΔV. However, a path formed by the detection transistor M3 and the detection resistor R3 is provided in parallel with the switching transistor M1, and flows through this path. The current may be monitored.

The comparison unit 30 includes a detection resistor R3 and a detection transistor M3 in addition to the second comparator 32, the voltage source 34, and the latch circuit 36. A detection transistor M3 and a detection resistor R3 are connected in series between the drain and source of the switching transistor M1. The detection transistor M3 is a P-channel MOS transistor like the switching transistor M1, and has a drain and a gate connected in common with the switching transistor M1. The transistor size of the detection transistor M3 is set smaller than that of the switching transistor M1, and the on-resistance Ron3 of the detection transistor M3 is set sufficiently higher than the on-resistance Ron1 of the switching transistor M1. The resistance value of the detection resistor R3 is set sufficiently higher than the on-resistance Ron3 of the detection transistor M3. That is, the impedance of the path including the detection transistor M3 and the detection resistor R3 is set sufficiently higher than the impedance of the switching transistor M1, and Ron3 + R3 >> Ron1 is established.
The second comparator 32 indirectly monitors the voltage ΔV ′ across the switching transistor M1 by monitoring the voltage across the detection resistor R3 as the monitoring voltage ΔV ′, and detects an overcurrent state.

  The operation of the control circuit 100 of FIG. 6 configured as described above will be described. If the current flowing through the switching transistor M1 is Im1, and the current flowing through the detection transistor M3 is Im3, then Im1 >> Im3 because of the impedance relationship of the two paths described above. The voltage ΔV across the switching transistor M1 is given by Im1 × Ron1, and this voltage is applied to the detection resistor R3 and the detection transistor M3. Therefore, the voltage across the detection resistor R3, that is, the monitoring voltage ΔV ′ is ΔV ′ = Im1 × Ron1 × R3 / (R3 + Ron3). That is, the monitoring voltage ΔV ′ is proportional to the current Im1 flowing through the switching transistor M1.

When the load RL is short-circuited and an overcurrent flows through the switching transistor M1, the voltage ΔV across the switching transistor M1 increases, and accordingly, the voltage ΔV ′ across the detection resistor R3 increases. When the monitoring voltage ΔV ′ exceeds the threshold voltage Vth, the comparison signal Vcmp output from the second comparator 32 becomes high level, the latch circuit 36 is set, and the first gate voltage Vg1 output from the driver circuit 10 is set. Becomes high level, and the switching transistor M1 and the detection transistor M3 are forcibly turned off.
As described above, in the control circuit 100 of FIG. 6, by monitoring the voltage ΔV ′ across the detection resistor R3, the voltage ΔV across the switching transistor M1 can be indirectly monitored, and an overcurrent state is detected. Thus, circuit protection can be performed.

  In the embodiment, the forced-off transistor 40 that is the first protection circuit controls the error voltage Verr in order to forcibly turn off the switching transistor M1 when an overcurrent state is detected. However, the present invention is not limited to this. Not. For example, the first gate voltage Vg1 is controlled by inputting the comparison signal SIG1 to the driver circuit 10 and logically operating the comparison signal SIG1 and the PWM signal Vpwm inside the driver circuit 10, thereby forcing the switching transistor M1. You may turn it off.

  In the embodiment, the case where the control circuit 100 is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are provided as discrete elements or chip components outside the LSI. Or you may comprise by several LSI. What part and how much to integrate can be determined by cost, occupied area, and the like.

  Further, in the present embodiment, the setting of high level and low level logical values is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.

It is a block diagram which shows the structure of the electronic device carrying the pressure | voltage fall type switching regulator which concerns on embodiment. 1 is a circuit diagram showing a configuration of a step-down switching regulator according to an embodiment. It is a circuit diagram which shows the structure of a 2nd protection circuit. It is a time chart which shows the operation state of the control circuit of FIG. It is a time chart which shows the operation state of the control circuit of FIG. It is a circuit diagram which shows the modification of the control circuit of FIG. 2, and is a figure which shows the structure of a comparison part.

Explanation of symbols

  100 control circuit, 102 input terminal, 104 switching terminal, 106 voltage feedback terminal, 110 switching regulator output circuit, 200 step-down switching regulator, 10 driver circuit, 20 PWM control unit, 22 error amplifier, 24 first comparator, 26 oscillator, 30 comparator, 36 latch circuit, 40 forced off transistor, 50 second protection circuit, 52 integrator, 62 digital filter, 64 timer circuit, C1 output capacitor, L1 inductor, Vg1 first gate voltage, Vg2 second gate voltage, M1 switching transistor, M2 synchronous rectification transistor, M3 detection transistor, R3 detection resistor.

Claims (13)

A step-down switching regulator control circuit,
An output stage including a switching transistor and a synchronous rectifying transistor connected in series between the input terminal and the ground, and outputting a voltage at a connection point of the two transistors as a switching voltage to the switching regulator output circuit;
Based on a pulse width modulation signal whose duty ratio is controlled so that the output voltage of the switching regulator output circuit approaches a predetermined reference voltage, the first to be applied to the gates of the switching transistor and the synchronous rectification transistor, A driver circuit for generating a second gate voltage;
A comparison unit that compares a voltage across the switching transistor with a predetermined threshold voltage, and outputs a comparison signal of a predetermined level when the voltage across the switching transistor exceeds the threshold voltage;
A first protection circuit for forcibly turning off the switching transistor during a period in which the comparison signal of the predetermined level is output from the comparison unit;
The control signal output from the comparator is monitored, and when the predetermined level is output continuously for a predetermined first period , the control circuit is configured to reduce power consumption for a predetermined second period. A second protection circuit which is in a stopped state and then returns to normal operation ;
A control circuit comprising: The comparison unit includes:
A voltage comparator for comparing the voltage across the switching transistor with the threshold voltage;
A latch circuit which is set by the output of the voltage comparator and is reset every one period of the pulse width modulation signal;
The control circuit according to claim 1, wherein the first protection circuit forcibly turns off the switching transistor based on an output signal of the latch circuit.   The control circuit according to claim 1, wherein the first protection circuit changes a logical value of the pulse width modulation signal.   The control circuit according to claim 1, wherein the first protection circuit changes an error voltage between an output voltage of the switching regulator and the reference voltage. The second protection circuit includes:
An integrator for integrating the comparison signal output from the comparison unit;
A first time measuring circuit for measuring a time during which the output signal of the integrator is held at the predetermined level;
The control circuit according to claim 1, further comprising: The control circuit according to claim 5, wherein the first time measurement circuit includes a digital filter to which an output signal of the integrator is input, and the first period is measured by the digital filter. The second protection circuit further includes a second time measurement circuit for starting the measurement of the second period according to the transition of the output of the first time measurement circuit, the first it is measured by the second time measurement circuit 6. The control circuit according to claim 5, wherein the control circuit is stopped for two periods.   6. The integrator according to claim 5, wherein the integrator generates a signal that quickly follows one edge of the comparison signal and gently follows the other edge, and outputs the signal to the first time measurement circuit. Control circuit according to. The integrator is
A transistor in which the comparison signal is input to a control terminal;
An RC filter connected to one end of the transistor;
A constant current source connected to a connection point of the transistor and the RC filter;
The control circuit according to claim 8, comprising: The comparison unit further includes:
Between the drain and source of the switching transistor, a detection transistor and a detection resistor connected in series so as to form a path parallel to the switching transistor and having the first gate voltage input to the gate, the voltage comparator includes: The control circuit according to claim 2, wherein the voltage across the detection resistor is compared with the threshold voltage.   The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate. A switching regulator output circuit comprising: an output capacitor having one end grounded; and an inductor having one end connected to the other end of the output capacitor;
The control circuit according to any one of claims 1 to 11, wherein a switching voltage is supplied to the other end of the inductor;
And a voltage at the other end of the output capacitor is output. Battery,
The step-down switching regulator according to claim 12, wherein the voltage of the battery is stepped down and output.
An electronic device comprising:

Images