JP4702550B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A ferroelectric memory device (FeRAM) is a non-volatile memory capable of low voltage and high speed operation, and a memory cell can be composed of one transistor / one capacitor (1T / 1C), so that it can be integrated like a DRAM. Therefore, it is expected as a large-capacity nonvolatile memory.

In order to maximize the ferroelectric characteristics of the ferroelectric capacitor constituting the ferroelectric memory device, the crystal orientation of each layer constituting the ferroelectric capacitor is extremely important.
JP 2000-277701 A

  An object of the present invention is to provide a semiconductor device in which the crystal orientation of each layer constituting a ferroelectric capacitor is well controlled and a method for manufacturing the same.

One method of manufacturing a semiconductor device according to the present invention includes a first step of forming a barrier layer above a substrate, a second step of forming a lower electrode on the barrier layer, and a strong step on the lower electrode. A third step of forming a dielectric layer; and a fourth step of forming an upper electrode on the ferroelectric layer, wherein the second step forms a metal layer on the barrier layer. Converting the metal layer into a first electrode layer having (111) orientation by performing a heat treatment in an inert gas atmosphere; and forming a second electrode layer on the first electrode layer; The lower electrode includes the first electrode and the second electrode, and the barrier layer is amorphous.
In the method for manufacturing a semiconductor device, the first electrode layer preferably has a thickness of 5 nm to 20 nm.
In the method for manufacturing a semiconductor device, the second electrode layer preferably contains iridium.
(1) A semiconductor device according to the present invention includes:
A substrate,
A barrier layer provided above the substrate;
A lower electrode provided above the barrier layer;
A ferroelectric layer provided above the lower electrode;
An upper electrode provided above the ferroelectric layer,
The lower electrode is formed by laminating a first electrode layer having a predetermined orientation and a second electrode layer.

  The semiconductor device according to the present invention includes a ferroelectric capacitor having a ferroelectric layer having a desired orientation. Therefore, a semiconductor device including a ferroelectric capacitor having good hysteresis characteristics can be provided.

  In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”) is referred to as “B” directly on the A layer. This includes the case where the layer is provided and the case where the B layer is provided on the A layer via another layer.

  The semiconductor device according to the present invention can further take the following aspects.

(2) In the semiconductor device according to the present invention,
And an insulating layer provided above the substrate;
A plug conductive layer penetrating the insulating layer,
The barrier layer may be provided at least above the plug conductive layer.

(3) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a barrier layer above the substrate;
(B) forming a metal layer above the barrier layer;
(C) performing a heat treatment under an inert gas atmosphere to form a first electrode layer having a predetermined orientation on the metal layer;
(D) forming a second electrode layer above the first electrode layer to form a lower electrode;
(E) forming a ferroelectric layer above the lower electrode;
(F) forming an upper electrode above the ferroelectric layer.

  According to the method for manufacturing a semiconductor device of the present invention, the lower electrode is obtained by forming the second electrode layer on the first electrode layer serving as the seed layer. The first electrode layer undergoes the heat treatment in the step (c), whereby atoms can easily move and the orientation can be improved. Since the second electrode layer is formed reflecting the crystal orientation of the first electrode layer, a second electrode layer having a predetermined orientation can be formed. Therefore, a ferroelectric layer can be formed on the lower electrode whose orientation is controlled. Since the ferroelectric layer is deposited reflecting the orientation of the lower electrode, by controlling the crystal orientation of the lower electrode to match the desired orientation of the ferroelectric layer, the ferroelectric layer has a desired orientation. A dielectric layer can be formed. As a result, a semiconductor device including a ferroelectric capacitor having good hysteresis characteristics can be provided.

(4) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a first metal layer containing at least titanium above the substrate;
(B) forming a second metal layer above the barrier layer;
(C) performing a heat treatment in a nitrogen atmosphere to nitride the first metal layer to convert it into a barrier layer, and convert the second metal layer into a first electrode layer having a predetermined orientation; ,
(D) forming a second electrode layer above the first electrode layer to form a lower electrode;
(E) forming a ferroelectric layer above the lower electrode;
(F) forming an upper electrode above the ferroelectric layer.

  According to the semiconductor device manufacturing method of the present invention, it is possible to form a ferroelectric layer having the same advantages as those of the semiconductor device manufacturing method described above. Therefore, a semiconductor device including a ferroelectric capacitor having good hysteresis characteristics can be provided.

  In addition, the manufacturing method of the semiconductor device concerning this invention can take the following aspect further.

(5) In the method for manufacturing a semiconductor device according to the present invention,
The film thickness of the first electrode layer may be 5 nm to 20 nm.

(6) In the method for manufacturing a semiconductor device according to the invention,
The second electrode layer may include iridium.

  An example of an embodiment of the present invention will be described with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device First, the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present embodiment.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a base body 10, an insulating layer 12, a contact portion 30, and a ferroelectric capacitor 40.

  The base 10 is a semiconductor substrate (for example, a silicon substrate). A plurality of transistors (not shown) are formed on the base 10. The transistor includes an impurity region serving as a source region or a drain region, a gate insulating layer, and a gate electrode. An element isolation region (not shown) is formed between the transistors, and electrical insulation between the transistors is achieved. The semiconductor device according to the present embodiment has, for example, a 1T1C type stack structure.

The insulating layer 12 is formed on the base 10. The insulating layer 12 is formed of, for example, at least one of a silicon oxide layer (SiO ₂ layer), a silicon nitride layer (SiN layer), a silicon nitride oxide layer (SiON layer), and an aluminum oxide layer (Al ₂ O ₃ layer). It may be a single layer or a plurality of layers.

  The contact hole 20 penetrates the insulating layer 12. A contact portion 30 having electrical conductivity is formed inside the contact hole 20.

  The contact portion 30 is formed to extend in a direction perpendicular to the surface of the base body 10 and penetrates the insulating layer 12. A transistor (either one of the source region and the drain region) of the base 10 is electrically connected to one end portion of the contact portion 30, and a ferroelectric capacitor 40 is electrically connected to the other end portion. ing. That is, the contact part 30 electrically connects the transistor and the ferroelectric capacitor 40.

  The contact part 30 includes a barrier layer 32 and a plug 34. The barrier layer is provided so as to cover the inner wall of the contact hole 20 (exposed surface of the base body 10 and the insulating layer 12). The plug 34 is provided on the barrier layer 32.

  The ferroelectric capacitor 40 is formed by sequentially laminating a barrier layer 42, a lower electrode 44, a ferroelectric layer 46, and an upper electrode 48. The barrier layer 42 is provided at least on the contact part 30. In the present embodiment, it has a pattern that also covers the contact portion 30 and the surrounding insulating layer 12 when viewed in plan. Thus, the barrier layer 42 (lower electrode 44) is electrically connected to the plug 34. Specifically, the lower electrode 44 of the ferroelectric capacitor 40 is electrically connected to either the source region or the drain region of the transistor. In the ferroelectric memory included in the semiconductor device according to the present embodiment, the lower electrode 44 of the ferroelectric capacitor 40 is electrically connected to the bit line, and the upper electrode 48 of the ferroelectric capacitor 40 is electrically connected to the plate line. The gate electrode of the transistor is electrically connected to the word line.

  The barrier layer 42 is a layer for suppressing the plug 34 from being oxidized in a later step, and for example, TiAlN, TiAl, TiSiN, TiN, TaN, TaSiN can be used. Among these, a layer containing titanium, aluminum, and nitrogen (TiAlN) is more preferable.

  The lower electrode 44 is configured by laminating a first electrode layer 44a and a second electrode layer 44b formed on the first electrode layer 44a. In the first electrode layer 44a, the desired orientation of the ferroelectric layer 46, which will be described later, and the regularity of atomic arrangement are the same. For example, when (111) -oriented PZT is used as the ferroelectric layer, an (111) -oriented Ir film can be used as the first electrode layer 44a.

The second electrode layer 44b is made of, for example, Pt, Ir, Ir oxide (IrO _x ), Ru, Ru oxide (RuO _x ), SrRu composite oxide (SrRuO _x ), or the like. The second electrode 44b may be formed from a single layer or may be formed from a plurality of layers. In particular, when the ferroelectric layer 46 is formed by the MOCVD method, it is preferable to use Ir having thermal stability.

The ferroelectric layer 46 may be formed using a PZT-based ferroelectric made of an oxide containing Pb, Zr, and Ti as constituent elements. Alternatively, Pb (Zr, Ti, Nb) O ₃ (PZTN system) doped with Nb at the Ti site may be applied. Alternatively, the ferroelectric layer 46 is not limited to these materials, and for example, any of SBT, BST, BIT, and BLT systems may be applied.

  The upper electrode 48 can be the same as the second electrode layer 44b.

  The semiconductor device according to the present embodiment includes a ferroelectric capacitor 40 having a ferroelectric layer 46 having a desired orientation. Therefore, a semiconductor device including the ferroelectric capacitor 40 having good hysteresis characteristics can be provided.

1.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 2 to 8 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

  (1) First, as shown in FIG. 2, the insulating layer 12 is formed on the substrate 10. The insulating layer 12 is formed on the surface of the substrate 10 on which a plurality of transistors are formed. The insulating layer 12 can be formed by applying a known technique such as a CVD method.

  (2) Next, as shown in FIG. 3, a contact hole 20 penetrating the insulating layer 12 is formed. In that case, a photolithography technique may be applied. Specifically, a resist layer (not shown) is formed so as to open a part of the insulating layer 12, and the opening from the resist layer is etched to form the contact hole 20 penetrating the insulating layer 12. The base 10 is exposed from the contact hole 20.

  (3) Next, a contact portion 30 (see FIG. 1) is formed in the contact hole 20. In forming the contact portion 30, first, as shown in FIG. 4, a barrier layer (other barrier layer) 31 is formed along the inner surface of the contact hole 20. The barrier layer 31 can be formed by a sputtering method or the like. The barrier layer 31 is formed on the side surface of the contact hole 20 (end surface of the insulating layer 12) and the bottom surface of the contact hole 20 (upper surface of the base body 10). It is also formed on the upper surface. However, the barrier layer 31 is formed so as not to fill the contact hole 20.

  (4) Next, as shown in FIG. 5, a first conductive layer 33 is formed inside the contact hole 20 and on the insulating layer 12. The first conductive layer 33 is formed so as to fill the inside of the contact hole 20 (specifically, the inner side surrounded by the barrier layer 31). In the case of forming the barrier layer 31, the first conductive layer 33 is formed on the barrier layer 31. The first conductive layer 33 can be formed by sputtering, for example.

  (5) Next, as shown in FIG. 6, the first conductive layer 33 is polished. In this embodiment, a part of the first conductive layer 33 and a part of the barrier layer 31 are polished and removed. That is, the first conductive layer 33 (and the barrier layer 31) is polished until the insulating layer 12 serving as a stopper is exposed. In the polishing process, a process by a chemical mechanical polishing (CMP) method can be applied. By this step, the contact part 30 can be formed.

  Next, as shown in FIG. 6, a barrier layer 41 is formed on the insulating layer 12 and the contact portion 30. The barrier layer 41 is patterned in a later step to become the barrier layer 42. As the barrier layer 41, for example, TiAlN can be formed by sputtering. At this time, the barrier layer 41 is preferably a crystalline layer or an amorphous layer having good orientation. Advantages when the barrier layer 41 is an amorphous layer will be described later.

  (6) Next, as shown in FIG. 7, the first electrode layer 43 a is formed on the barrier layer 41. As the first electrode layer 43a, 1.1. The materials described in the section of the semiconductor device can be used. Hereinafter, for example, a case where an Ir film having a predetermined orientation is formed will be described. First, an Ir film (not shown) is formed on the barrier layer 41. There is no particular limitation on the orientation of the Ir film. Next, heat treatment is performed in an inert gas atmosphere. The heat treatment can be performed at 450 ° C. to 725 ° C. As the inert gas, for example, argon or nitrogen can be used. By performing this heat treatment, the atoms easily move and the (111) orientation component, which is a stable atomic arrangement of Ir, can be increased. As a result, the first electrode layer 43a having a predetermined orientation can be formed. At this time, if the barrier layer 41 located under the first electrode layer 43a is an amorphous layer, the influence of the orientation of the barrier layer 41 can be reduced. Therefore, it is possible to easily form a desired orientation when the first electrode layer 43a is subjected to heat treatment. The film thickness of the first electrode layer 43a is preferably 5 nm to 20 nm. When the thickness of the first electrode layer 43a is smaller than 5 nm, a continuous film may not be formed and may not serve as a seed layer. If it exceeds 20 nm, it may be difficult to control the orientation during the heat treatment.

  (7) Next, as shown in FIG. 8, the second electrode layer 43b, the ferroelectric layer 45, and the upper electrode (second electrode) 47 are sequentially stacked on the first electrode layer 43a to form a stacked body. To do.

  As a method for forming the second electrode layer 43b, a sputtering method, a vacuum evaporation method, a CVD method, or the like can be applied. As a method for forming the ferroelectric layer 45, a solution coating method (including sol-gel method, MOD (Metal Organic Decomposition) method, etc.), sputtering method, CVD method, MOCVD (Metal Organic Chemical Vapor Deposition) method, etc. are applied. can do. The upper electrode 47 can be formed by applying the same method as that for the second electrode layer 43b. Next, for example, a resist layer R1 is formed on the stacked body. The resist layer R1 can be formed by applying a photolithography technique.

  (8) Next, as shown in FIG. 1, the portion of the laminate that is not covered with the resist layer R1 is removed. The removal of the stacked body can be performed by applying a known etching technique. After the multilayer body is patterned to form the ferroelectric capacitor 40, annealing is performed in an oxygen atmosphere in order to stabilize the ferroelectric layer 46 (for example, recovery from etching damage).

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

  According to the method of manufacturing a semiconductor device according to the present embodiment, the lower electrode 44 is obtained by forming the second electrode layer 43b on the first electrode layer 43a serving as a seed layer. Therefore, the ferroelectric layer 46 can be formed on the lower electrode 44 whose orientation is controlled. Since the ferroelectric layer 46 is deposited reflecting the orientation of the lower electrode 44, according to the present embodiment, the ferroelectric layer 46 having a desired orientation can be formed. As a result, a semiconductor device including the ferroelectric capacitor 40 having good hysteresis characteristics can be manufactured.

2. Second Embodiment 2.1. Semiconductor Device Next, a semiconductor device according to a second embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view schematically showing a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is an example in which the configuration of the barrier layer 42 is different from that of the first embodiment. In the following description, differences from the first embodiment will be described.

  As shown in FIG. 9, in the semiconductor device according to the second embodiment, the barrier layer 42 is formed by laminating a first barrier layer 42a and a second barrier layer 42b. The barrier layer 42 can suppress the plug 34 from being oxidized in a later step. As the first barrier layer 42a, a metal having self-orientation or a nitride thereof can be used. Here, the self-orientation refers to a property of growing so that a specific orientation component increases. Examples of the first barrier layer 42a include Ti and TiN. The first barrier layer 42a is a layer in which the orientation required for the ferroelectric layer 46 and the regularity of atomic arrangement are the same.

  As the second barrier layer 42b, a material having a higher antioxidant effect than that of the first barrier layer 42a can be used. As the second barrier layer 42b, the material exemplified for the barrier layer 42 described in the first embodiment can be used.

  According to the semiconductor device of the second embodiment, the orientation of the second barrier layer 42b, the lower electrode 44, and the ferroelectric layer 46 stacked thereon is controlled by controlling the orientation of the first barrier layer 42a. Can be controlled. Further, by forming the barrier layer 42 by laminating two or more kinds of layers, it is possible to improve the control of the orientation and prevent the plug from being oxidized.

2.2. Manufacturing Method of Semiconductor Device Next, a semiconductor device according to the second embodiment will be described with reference to FIG. In the following description, differences from the manufacturing method according to the semiconductor device according to the first embodiment will be described.

  The contact part 30 is formed in the same manner as in the steps (1) to (5) of the manufacturing method according to the first embodiment. Next, as shown in FIG. 10, a first barrier layer 41 a is formed on the insulating layer 12 including the contact portion 30. As the first barrier layer 41a, a material having self-orientation is used. Next, the second barrier layer 41b is formed on the first barrier layer 41a. The second barrier layer 41b is the same as the barrier layer 41 in the first embodiment.

  Next, as in the step (6) of the manufacturing method according to the first embodiment, the first electrode layer 43a is formed on the second barrier layer 41b. At this time, the heat treatment for forming the first electrode layer 43a is preferably performed in a nitrogen atmosphere. Thus, there is an advantage that the first barrier layer 41a can be nitrided by performing the heat treatment in a nitrogen atmosphere. For example, when a Ti layer is formed as the first barrier layer 41a, the TiN layer can be formed by a heat treatment in a nitrogen atmosphere, and the prevention of oxidation can be improved.

  Next, the semiconductor device shown in FIG. 9 can be manufactured in the same manner as steps (7) and (8) of the manufacturing method according to the first embodiment.

  According to the method for manufacturing a semiconductor device according to the second embodiment, the barrier layer 42 in which the orientation is controlled and the oxidation resistance is improved can be formed. Therefore, a semiconductor device including the ferroelectric capacitor 40 having good hysteresis characteristics can be manufactured.

3. Third Embodiment Next, a semiconductor device according to a third embodiment will be described. In the following description, differences from the semiconductor device according to the first embodiment will be described.

  The semiconductor device according to the third embodiment is different from the semiconductor device shown in FIG. 1 in the material of the barrier layer 42. In the third embodiment, a TiN layer is used as the barrier layer 42. In the barrier layer 42, atoms are arranged with the same regularity as the desired orientation of the ferroelectric layer 46.

  A method of forming the barrier layer 42 according to the third embodiment will be described with reference to FIG. FIG. 11 is a cross-sectional view schematically showing a part of the manufacturing process according to the third embodiment. As shown in FIG. 11, a metal layer 410 is formed on the insulating layer 12 and the plug 34. As the metal layer 410, for example, a Ti layer is formed. Further, the metal layer 410 is a material having self-orientation that crystallizes and grows preferentially in a predetermined orientation, and if the orientation is the same as the desired orientation of the ferroelectric layer, There is no particular limitation. Next, as shown in FIG. 11, the first electrode layer 43 a is formed on the metal layer 410. Thereafter, a heat treatment is performed in a nitrogen atmosphere when forming the first electrode layer 43a in the step (6) described in the first embodiment, so that the TiN layer can be converted and the barrier layer 41 is formed. The barrier layer 41 is patterned in a later step to become the barrier layer 42.

  According to the third embodiment, the metal layer 410 can contribute to the control of orientation in the step of depositing the film to be the first electrode layer 43, and after being nitrided to become the barrier layer 41, This can contribute to preventing the plug 34 from being oxidized. Therefore, both roles can be fulfilled without laminating a plurality of layers as a barrier layer.

4). Experimental Example Next, an experimental example for confirming the effect of the semiconductor device according to the present embodiment will be described.

4.1. Experimental example 1
First, a transistor was formed on a semiconductor substrate (silicon substrate) 10, and then an insulating layer 12 was stacked on the transistor. Next, a contact hole 20 is formed in the insulating layer 12, and the contact hole 20 is filled with tungsten by a CVD method, and then the tungsten above the surface of the insulating layer 12 is polished by chemical mechanical polishing to thereby form a plug. 34 was formed (see FIG. 1).

  Next, a barrier layer 41 made of TiAlN was formed on the insulating layer 12 and the plug 34 by sputtering. In this film forming process, an atmosphere having a nitrogen partial pressure of 16% was used, and TiAl was selected as a target. The ratio of titanium and aluminum in the target was Ti / Al = 70: 30.

  The barrier layer 41 is deposited under the conditions that the flow rate of argon gas is 50 [sccm], the deposition power is 1.0 [kW], and the substrate temperature is 400 [° C.]. I did it.

  Next, the first electrode layer 43a was formed by a sputtering method. The film formation conditions for the first electrode layer 43a are as follows: the flow rate of argon gas is 199 [sccm], the film formation power is 1.0 [kW], and the substrate temperature is 500 [° C.]. went. Under this condition, the first electrode layer 43a having a thickness of 20 nm was formed. Next, heat treatment was performed to control the orientation. The heat treatment was performed for 2 minutes in an argon atmosphere under the condition of a substrate temperature of 650 [° C.].

  Next, the second electrode layer 43b was formed by a sputtering method. The film formation conditions for the second electrode layer 43b are as follows: the flow rate of argon gas is 199 [sccm], the film formation power is 1.0 [kW], and the substrate temperature is 500 [° C.]. went. The film thickness of the second electrode 43b of argon gas formed under these conditions was 90 nm.

  FIG. 12 shows an XRD (X-ray diffraction) pattern of the second electrode layer 43b formed in this way.

  According to FIG. 12, a peak was observed in the vicinity of 2θ = 41 ° in the second electrode layer 43b obtained in Example 1. This peak is assumed to be caused by an Ir film having a (111) orientation. That is, according to the present embodiment, it was possible to form the lower electrode whose orientation was controlled as described above.

  Next, in order to quantitatively evaluate the crystal orientation of the second electrode layer 43b, the rocking curve of (111) diffraction of the Ir film shown in FIG. 12 was measured. The result is shown in FIG. The full width at half maximum FWHM of the rocking curve shown in FIG. 13 was about 4.90 °. Note that the full width at half maximum FWHM of the rocking curve is a difference between two angles having a peak intensity that is ½ of the maximum peak intensity, as shown in FIG. From the above results, it was confirmed that the second electrode layer 43b has an excellent (111) orientation as shown in FIG.

4.2. Experimental example 2
In Experimental Example 2, the formation of the barrier layer is different from Experimental Example 1. In Experimental Example 2, a Ti layer was first formed as the metal layer 410 by a sputtering method.

  The metal layer 410 was deposited under the conditions that the flow rate of argon gas was 50 [sccm], the deposition power was 1.5 [kW], and the substrate temperature was 150 [° C.]. . The film thickness of the metal layer 410 thus formed was 20 nm.

  Next, a barrier layer 41b made of TiAlN was formed on the metal layer 410 by sputtering. In this film forming process, an atmosphere having a nitrogen partial pressure of 16% was used, and TiAl was selected as a target. The ratio of titanium and aluminum in the target was Ti / Al = 70: 30.

  The film formation conditions for the barrier layer 41b are as follows: the flow rate of argon gas is 50 [sccm], the film formation power is 1.0 [kW], and the substrate temperature is 400 [° C.]. I did it. The thickness of the metal layer 410 thus formed was 100 nm.

  Next, similarly to Experimental Example 1, the first electrode layer 43a and the second electrode layer 43b were formed. In order to quantitatively evaluate the crystal orientation of the second electrode layer 43b thus formed, a rocking curve of a diffraction peak of (111) orientation was measured. The result is shown in FIG. The full width at half maximum FWHM of the rocking curve shown in FIG. 14 was about 2.90 °. From the above results, as shown in FIG. 14, it was confirmed that the first electrode layer 43b has excellent (111) orientation. Furthermore, even when compared with Experimental Example 1, it was confirmed that the second electrode layer 43b with improved crystal orientation could be formed by forming the metal layer 410.

  From the above results, it was confirmed that according to the method for forming the lower electrode 44 according to the present embodiment, the lower electrode 44 with controlled orientation can be formed. Therefore, the ferroelectric layer 46 having a desired orientation can be formed.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning 3rd Embodiment. The figure which shows the XRD pattern of the Ir film | membrane concerning Experimental example 1. The figure which shows the rocking curve of (111) diffraction of the Ir film | membrane shown in FIG. The figure which shows the rocking curve of (111) diffraction of the Ir film | membrane concerning Experimental example 2. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Base | substrate, 12 ... Insulating layer, 20 ... Contact hole, 30 ... Contact part, 31 ... Barrier layer, 33 ... 1st conductive layer, 34 ... Plug, 40 ... Ferroelectric capacitor, 41 ... Barrier layer, 42 ... Barrier layer, 43a, 44a ... first electrode layer, 43b, 44b ... second electrode layer, 44 ... lower electrode, 45, 46 ... ferroelectric layer, 47, 48 ... upper electrode, 410 ... metal layer

Claims (2)

A first step of forming an amorphous barrier layer above the substrate;
Forming a metal layer on the barrier layer and performing a heat treatment in an inert gas atmosphere to convert the metal layer into a first electrode layer having (111) orientation; and on the first electrode layer Forming a second electrode layer and forming a lower electrode, and a second step comprising:
A third step of forming a ferroelectric layer on the lower electrode;
Forming a top electrode on the ferroelectric layer; and
The material of the barrier layer is titanium aluminum nitride,
The material of the metal layer is iridium,
The method of manufacturing a semiconductor device, wherein the material of the second electrode layer is iridium or iridium oxide. In claim 1,
The method for manufacturing a semiconductor device, wherein the film thickness of the first electrode layer is 5 nm to 20 nm.