JP4700992B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that encodes a moving image signal.

  In recent years, digital video cameras and digital televisions have been trending toward high-definition (higher resolution). Then, a high resolution image (HD image) signal is converted into MPEG or H.264. There is a growing demand for high-vision imaging devices that record with a high-efficiency encoding method such as H.264. Further, it is required as a specification that an imaging apparatus for high vision not only records HD images but also can record standard resolution images (SD images).

  When an HD image signal is encoded, the resolution, that is, the number of pixels per screen is larger than that of an SD image signal. Therefore, conventionally, one screen is divided into a plurality of areas and encoded by different processors. (For example, refer to Patent Document 1).

JP 2001-346201 A

  As described above, the HD image signal is conventionally encoded by a plurality of processors. However, when the SD image signal is encoded using the same encoding circuit, a part of the plurality of encoding processors is used. There is a problem that even though it has multiple processors, it cannot be used effectively.

  The present invention has been made in consideration of the above-described circumstances, and can encode an HD image signal and an SD image signal, and an image including a plurality of encoding processors for encoding the HD image signal. An object of the present invention is to provide an image processing apparatus capable of performing higher-quality encoding on an SD image signal in the processing apparatus.

The present invention has been made to solve the above-described problem, and encodes a first moving image signal having a first resolution and a second moving image signal having a resolution higher than the first resolution. A first processing mode for encoding the first moving image signal and an encoding process for the second moving image signal based on an operation of an operation unit. A mode determination means for determining which of the second processing modes is to be executed and a plurality of encoding means capable of encoding the first moving image signal in real time are combined to provide the second moving image signal in real time. An encoding group means capable of encoding; an input means for inputting the first moving image signal or the second moving image signal to the plurality of encoding means; and the mode determining means, When it is determined that the processing mode, Input control means for controlling the input means so as to input the first moving image signal in parallel to each of the encoding means in the number of encoding means, and the mode determination means is the first processing mode. If it is determined, a parameter setting means for setting the motion search service Chieria as each different coding parameter values for the plurality of encoding means, when said mode determining means determines that said first processing mode , sum of absolute differences between the macro block and the encoding target macro block of the reference image in which each coding unit the parameter setting means sets the different motion search service Chieria indicates the motion vector calculated by performing a motion search, respectively And specifying means for specifying the moving image encoded signal output by the encoding means that has calculated the value having the smallest difference absolute value sum, When the mode determining unit determines that the first processing mode is selected, the moving image encoded signal specified by the specifying unit is output as the output target signal from the plurality of moving image encoded signals output from the plurality of encoding units. Output control means for outputting.

An image processing apparatus according to the present invention is an image processing apparatus capable of encoding a first moving image signal having a first resolution and a second moving image signal having a resolution higher than the first resolution. there are, taking into account the amount of motion, it is possible to perform sign-reduction with respect to the first moving image signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
As an image processing apparatus according to the first embodiment of the present invention, a video camera (having an imaging function) capable of capturing HD images (high resolution moving images) and SD images (standard resolution moving images) and recording them on a recording medium. The image processing apparatus will be described below. FIG. 1 is a diagram showing a schematic configuration of a video camera according to the first embodiment of the present invention. As shown in FIG. 1, the video camera (imaging device) according to the present embodiment has an SD core (encoding processor) that is a circuit capable of encoding a moving image signal of an SD image in real time (with no missing frame). ) And N (N is an integer equal to or greater than 2), and an HD imaging signal is recorded and recorded in real time.

  Note that the HD image signal (high-resolution video signal) of this embodiment is, for example, a high-definition video signal, and the SD image signal (standard-resolution video signal) is, for example, a normal television video (NTSC-compliant video). ) Signal. The operation mode of the video camera of the present embodiment includes an HD recording mode in which the captured HD image signal is encoded and recorded on a recording medium, and a recording medium in which the captured SD image signal is encoded. And SD recording mode for recording.

  In FIG. 1, reference numeral 101 denotes an image pickup unit, which includes an optical system and an image pickup device, and outputs an HD image signal or an SD image signal (digital signal). Reference numerals 102 and 103 denote switches, which switch a buffer serving as a transmission destination of an output signal (HD image signal or SD image signal) of the imaging unit 101 in accordance with control of a controller 120 described later.

  Reference numeral 104 denotes a frame buffer. The frame buffer 104 is composed of N storage areas of buffers 105 to 106. In FIG. 1, buffers other than the buffer 105 and the buffer 106 are not shown. Each of the N buffers shown as buffers 105 to 106 is a buffer having a capacity capable of recording one frame of the SD image signal. The storage capacity obtained by adding all the buffers 105 to 106 is a capacity capable of recording one frame of the HD image signal. That is, the HD image signal for one frame is divided and stored in the buffers 105 to 106.

  Reference numeral 107 denotes an HD signal encoding circuit in which N SD cores 108 to 109, which are circuits capable of encoding SD image signals in real time, are arranged. Note that SD cores other than the SD core 108 and the SD core 109 are not shown in the figure. The N SD cores 108 to 109 are installed corresponding to the buffers 105 to 106. By simultaneously using these N SD cores 108 to 109, the HD image signal can be encoded in real time.

  Reference numeral 110 denotes an encoded video signal encoded by the SD core 108. Reference numeral 111 denotes a video encoded signal encoded by the SD core 109. That is, the N SD cores 108 to 109 output the video encoded signal 110 to the video encoded signal 111. In FIG. 1, signals output from SD cores other than the SD core 108 and SD core 109 are not shown because they are omitted.

  Reference numeral 112 denotes a switch, which selects any one of the video encoded signal 110 to the video encoded signal 111 output from the N SD cores 108 to 109 according to the control of the determination circuit 113. Output. Reference numeral 113 denotes a determination circuit that outputs a control signal for controlling the switch 112 in accordance with the control of the controller 120 and the video encoded signal 110 to the video encoded signal 111 and the output signal of the imaging unit 101. For example, the determination circuit 113 uses the video encoded signal 110 to the video encoded signal 111 and the input signal (SD image signal) from the imaging unit 101 to determine the SN ratio of the video encoded signal 110 to the video encoded signal 111. Based on this value, the switch 112 is controlled. Specifically, the determination circuit 113 performs a decoding process on the video encoded signal 110 to the video encoded signal 111 and compares it with the SD image signal that is the source signal to obtain the SN ratio.

  Reference numeral 114 denotes a video stream buffer that temporarily stores a signal output from the switch 112 (any one of the video encoded signal 110 to the video encoded signal 111). Reference numeral 115 denotes a microphone provided in the video camera. An audio signal encoding circuit 116 encodes the audio signal input from the microphone 115 and outputs an audio encoded signal. Reference numeral 117 denotes an audio stream buffer that temporarily stores the audio encoded signal encoded by the audio encoding circuit 116.

  Reference numeral 118 denotes a recording circuit which multiplexes the video encoded signal stored in the video stream buffer 114 and the audio encoded signal stored in the audio stream buffer 117 and records the multiplexed signal on a recording medium 119 such as an optical disk or a magnetic tape.

  A controller 120 controls the entire video camera, the switches 102 and 103, the HD encoding circuit 107, the SD core 108 to the SD core 109, and the determination circuit 113. An operation unit 121 includes a power switch, a setting switch for setting the resolution of an image to be recorded, a trigger switch for instructing start and stop of recording, and the like. The operation unit 121 outputs a signal corresponding to a user operation to the controller 120.

  The video signal encoding method of the video camera of this embodiment is, for example, MPEG or H.264. For example, MPEG audio and AC3, AAC, and the like are preferable. However, the audio signal encoding method is not limited to this, and is a high-efficiency encoding method that efficiently encodes video signals and audio signals. I just need it. That is, the SD cores 108 to 109 set an orthogonal transform unit that outputs an orthogonal transform coefficient (DCT coefficient) by orthogonal transform (DCT) of an SD image signal or an HD image signal, and an orthogonal transform coefficient output by the orthogonal transform unit. And a quantization unit that performs quantization with the quantized step width. In addition, for the SD cores 108 to 109, it is possible to set a target code amount at the time of encoding, a quantization step width, a DCT type, and the like according to encoding parameters.

  Next, video recording processing of the video camera in the first embodiment shown in FIG. 1 will be described. FIG. 2 is a flowchart showing video recording processing of the video camera in the first embodiment shown in FIG. In FIG. 2, a description will be given of an embodiment in which two SD cores (SD core 108 and SD core 109) are used for simplifying the explanatory text and the flowchart, but in reality, N SD cores are used. Yes.

  First, before the processing in FIG. 2, the user operates the operation unit 121 to turn on the power of the video camera, and then determines the resolution of the image to be recorded. As a result, in step S201, the controller 120 determines whether it is the SD recording mode or the HD recording mode during the startup process. If the SD recording mode has been set by operating the operation unit 121, the process proceeds to step S202, and the controller 120 controls the recording mode to the SD recording mode. If the HD recording mode has been set, the process proceeds to step S210, and the controller 120 changes the recording mode to the HD recording mode.

  First, the operation of the present video camera when the recording mode is the SD recording mode will be described. After the recording mode of the video camera becomes the SD recording mode in step S202, the controller 120 enters a recording start waiting state in step S203. Here, when the user performs a recording start operation on the operation unit 121, the controller 120 gives a recording start command to the necessary block, and starts encoding and recording processing of the SD image signal after step S204.

  Next, in step S204, the controller 120 controls and switches the switch 102 and the switch 103 so that the SD image signal input from the imaging unit 101 is stored in the buffers 105 to 106. At this time, the same data (SD image signal for one frame) is stored in the buffers 105 to 106. When the SD recording mode is set, the controller 120 sets different encoding parameter values for the SD cores 108 to 109. The SD image signals stored in the buffers 105 to 106 are input to the SD core 108 to the SD core 109, which are given different encoding parameter values. As a result, the encoded video signal 110 is output from the SD core 108, and the encoded video signal 111 is output from the SD core 109.

Here, encoding parameters given to the respective SD cores 108 to 109 will be described.
The first encoding parameter is a target code amount. The target code amount of GOP for the SD core 108 and the SD core 109 is set to be the same, but the target code amount distribution of each picture (I picture, P picture, B picture) is different between the SD core 108 and the SD core 109. . For example, in the SD core 108, a target code amount obtained as a result of calculating the ratio of the target code amount of each picture using the complexity of the picture as in so-called TM5 (MPEG Test Model 5) is set. In addition, the SD core 109 sets a larger target code amount for the P picture and B picture than the ratio of the target code amount values of the I picture and the P and B pictures in the SD core 108. With the above settings, a large amount of code is required for P and B pictures for a video signal with a large motion. Therefore, image quality can be improved with target code amount distribution like the SD core 109.

  However, when the encoding parameter is set to the target code amount, if the switch 112 is switched in units of pictures, there is a large difference between the target code amount of GOP and the generated code amount of GOP generated by actual encoding. The buffer will be broken. Therefore, when the target code amount is used as an encoding parameter, the switch 112 is switched in units of GOP (Group Of Pictures).

  The second encoding parameter is the quantization step width. For the SD core 108, the quantization step width calculated using the activity is used. The DCT coefficient is quantized using the quantization step width calculated based on the generated code amount multiplied by the activity as the actual quantization step width. Activity refers to the distribution of macroblocks, and has the effect of reducing the quantization step width in flat areas that are easily noticeable to human vision and increasing the quantization step width in texture areas that are inconspicuous to human vision. .

  On the other hand, for the SD core 109, the quantization step width calculated without using the activity is used. The quantization of the DCT coefficient is performed using the quantization step width calculated based on the generated code amount as the actual quantization step width. In this case, it is possible to add or remove sharpness in the screen according to the scene. However, if the sharpness of the frame changes in units of frames, there may be a visual adverse effect. Therefore, the switch 112 is switched in units of several frames or GOPs.

  The third encoding parameter is a parameter that specifies the type of DCT (Discrete Cosine Transform), which is an orthogonal transform method employed in MPEG. The SD core 108 is set to perform DCT when performing frame DCT, and the SD core 109 is configured to perform field DCT when performing DCT. In the present embodiment, the SD image signal is in an interlace format. In the case of field DCT, the DCT process is performed for each frame image of one DCT block. In the case of frame DCT, the frame image of one DCT block is processed. The DCT process is performed for each frame. In this case, since it is effective to use the frame type DCT for a portion with little motion, the output from the SD core 108 is used, and it is effective to use the field type DCT for a portion with little motion. The switch 112 is switched to use the output from the core 109. When the switching timing of the switch 112 is in units of macro blocks, the DCT type can be switched for each macro block according to the SN ratio. Further, when the slice is used as a unit, the DCT type can be switched for each slice according to the SN ratio.

  The encoding parameters listed above are merely examples, and parameters other than those described above may be used as long as they are encoding parameters used for encoding video signals. Further, a method of switching by one parameter alone or a combination of a plurality of encoding parameters may be used.

  Next, in step S205, the encoded video signals 110 to 111 encoded by combining the settings of the encoding parameters and the SD image signal from the imaging unit 101 are input to the determination circuit 113. The determination circuit 113 evaluates image quality degradation using the SD image signal and the video encoded signals 110 to 111 encoded with the above encoding parameters, and selects and outputs the video encoded signal with the least image quality deterioration. The switch 112 is controlled so as to be switched.

  Further, the determination circuit 113 evaluates the generated code amount using the SD image signal and the video encoded signals 110 to 111 encoded by the set values of the respective encoding parameters, and the video code having the smallest generated code amount The switch 112 may be switched so as to output the control signal.

  Furthermore, the determination circuit 113 evaluates the image quality and the generated code amount using the SD image signal and the video encoded signals 110 to 111 encoded with the set values of the respective encoding parameters, and the image quality is less generated. It is also possible to switch the switch 112 so as to output a video encoded signal with a small code amount.

  Note that the determination circuit 113 is currently compared and evaluated in units of pictures, but not limited to units of pictures, slices and macroblocks may be used as units of comparison. The switching timing of the switch 112 is assumed to be a macroblock unit, a slice unit, a picture unit, and a GOP unit.

  Next, when the determination circuit 113 determines in step S205 that the video encoded signal 110 has a higher SN ratio, the process proceeds to step S206, and the video encoded signal is transferred to the video stream buffer 114 by switching the switch 112. 110 is saved. If the determination circuit 113 determines that the video encoded signal 111 has a higher SN ratio in step S205, the video encoded signal 111 is stored in the video stream buffer 114 in step S207.

  Next, in step S <b> 208, the recording circuit 118 multiplexes the video encoded signal stored in the video stream buffer 114 and the audio encoded signal stored in the audio stream buffer 117 and records them on the recording medium 119. To do.

  Next, in step S209, the controller 120 determines whether or not a recording end command has been given to the video camera by the user operating the operation unit 121. If it is determined that a recording end command has not been given, the process returns to step S204 to continue the encoding and recording processing of the SD image signal and audio signal. If it is determined that an instruction to end recording is given, the video camera ends the encoding and recording processing of the SD image signal and the audio signal.

  Next, the operation of this video camera when the recording mode is the HD recording mode will be described. After the HD recording mode is set in step S210, the controller 120 enters a recording start waiting state in step S211. Here, when the user performs a recording start operation on the operation unit 121, the controller 120 gives a recording start command to the necessary block, and starts encoding and recording processing of the HD image signal after step S212.

  First, in step S212, the controller 120 controls and switches the switch 102 and the switch 103 so that the HD image signal input from the imaging unit 101 is stored in the buffers 105 to 106. At this time, each buffer stores one divided data obtained by dividing one frame of the HD image signal into a plurality of areas each having a predetermined size. The divided data stored in the buffer 105 is encoded by the SD core 108 to generate a video encoded signal 110, and the divided data stored in the buffer 106 is encoded by the SD core 109 to generate the video encoded signal 111. Generated. That is, the video encoded signal 110 and the video encoded signal 111 are data obtained by encoding different areas within one frame.

  Next, in step S213, the controller 120 controls the switch 112 via the determination circuit 113 to switch the video stream buffer so that the video encoded signal 110 and the video encoded signal 111 become one video encoded signal. Save to 114.

  The subsequent operation is the same as in the SD recording mode shown in steps S208 to S209. In step S208, the encoded video signal stored in the video stream buffer 114 and the audio code stored in the audio stream buffer 117 are stored. The recording signal is multiplexed by the recording circuit 118 and recorded on the recording medium 119. Then, unless a recording end command is given in step S209, the process returns to step S212, and the HD image signal and audio signal are encoded and recorded. When the recording end command is given, the encoding and recording processing of the HD image signal and the audio signal is ended.

  As described above, in the video camera of the present embodiment, in the SD recording mode, each SD core performs encoding with various encoding parameters, and the SD core determined to have the best image quality by the determination circuit 113. Can be output. As a result, the video camera according to the present embodiment can effectively use a plurality of SD cores for the HD recording mode, and can perform higher-quality encoding on the SD image signal than before.

(Second Embodiment)
Next, a video camera (an image processing apparatus having an imaging function) in the second embodiment will be described. FIG. 3 is a diagram illustrating a schematic configuration of a video camera (imaging device) according to the second embodiment. The components denoted by reference numerals 301 to 312, 314 to 320, and 323 in FIG. 3 are the same as the components 101 to 112, 114 to 120, and 121 in the first embodiment illustrated in FIG. To do. In the video camera of FIG. 3, portions different from the video camera of FIG. 1 are encoded by the SD cores 308 to 309 without the determination circuit 313 using the signals output from the imaging unit 301 and the video encoded signals 310 to 311. The point is that the switch 312 is controlled using the coding information (for example, the value of motion compensation) calculated at the time of conversion.

  Reference numeral 321 denotes encoding information calculated when the SD core 308 performs encoding, and reference numeral 322 denotes encoding information calculated when the SD core 309 performs encoding. In FIG. 3, the encoding information calculated when encoding is performed in the SD core other than the SD core 308 and the SD core 309 is not shown because it is omitted. Similarly to the first embodiment, the video signal encoding method of the video camera in this embodiment is MPEG and H.264. It is assumed that the audio signal encoding method is MPEG audio, AC3, AAC, and the like.

  Since the recording process of the video camera in the second embodiment is the same as that of the first embodiment, it will be described with reference to the flowchart of FIG. However, since the contents of the output determination process in step S205 in FIG. 2 are different between the second embodiment and the first embodiment, this point will be mainly described.

  In step S204, the controller 320 controls the switch 302 and the switch 303 so that the SD image signal input from the imaging unit 301 is stored in the buffers 305 to 306. At this time, the same data is stored in the buffer 305 to the buffer 306. The SD image signals stored in the buffer 305 to the buffer 306 are input to the SD core 308 to the SD core 309 given different encoding parameters, and the video encoded signal 310 is output from the SD core 309 from the SD core 308. A video encoded signal 311 is generated.

  In the present embodiment, for example, when performing a motion search for the SD core 308, the search area is wide and the accuracy is set to be in units of N pixels (N is 1 or more). In other words, when performing a motion search, the search area is narrow and the accuracy is set to be in units of n pixels (n is 1 or less).

  In the setting as described above, the determination circuit 313 has a switch to select the video encoded signal 310 output from the SD core 308 because it is effective to set a wide search area for a portion with a large amount of motion. 312 is controlled and switched. The determination circuit 313 switches the switch 312 so as to select the video encoded signal 310 output from the SD core 309 because it is effective to set a narrow search area and perform a fine search for a portion with a small amount of motion.

  Here, when the switching timing of the switch 312 is in units of macroblocks, a small value is obtained by looking at the sum of absolute differences between the macroblock to be encoded and the macroblock of the reference image indicated by the calculated motion vector for each macroblock. The calculated output signal is used. In addition, when a slice is used as a unit, the output signal for which the smaller value is calculated by using the sum of absolute differences between the macroblock to be encoded and the macroblock of the reference image indicated by the calculated motion vector is used for each slice. To do.

  For example, if it is determined in step S205 that the sum of absolute differences in the SD core 308 is high, the process proceeds to step S206, and the video encoded signal 310 is stored in the video stream buffer 314. If it is determined in step S205 that the sum of absolute differences in the SD core 309 is high, the encoded video signal 311 is stored in the buffer 314.

  As described above, in the second embodiment, an optimally encoded video encoded signal is selected by using the encoding information used in the SD core 308 to the SD core 309. Can do. As a result, the video camera according to the present embodiment can effectively use a plurality of SD cores for the HD recording mode, and can perform higher-quality encoding on the SD image signal than before. In the present embodiment, the case where two SD cores are used has been described for the sake of simplification. However, when N SD cores are used, the setting of the motion compensation search range is not limited to the above.

(Third embodiment)
Next, a video camera (an image processing apparatus having an imaging function) in the third embodiment will be described. FIG. 4 is a diagram illustrating a schematic configuration of a video camera (imaging device) according to the third embodiment. FIG. 5 is a flowchart showing the operation of the video camera shown in FIG.

  4 are the same as the reference numerals 101 to 103, 110 to 112, and 114 to 121 of the first embodiment shown in FIG. It is a component and will not be described. 4 differs from the video camera of FIG. 1 in that the determination circuit 415 uses the signals output from the imaging unit 301 and the video encoded signals 310 to 311 (switch 424 as shown in FIG. 1). It is a point of controlling the SD core 409). Hereinafter, differences from the first embodiment will be mainly described.

  First, the frame buffer 404 includes N storage areas of a buffer 405, a buffer 406, and a buffer 407. The buffer 405 has a sufficiently larger memory area than the buffers 406 to 407 other than the buffer 405. In FIG. 4, buffers other than the buffer 405, the buffer 406, and the buffer 407 are not shown because they are omitted.

  Reference numeral 408 denotes an HD signal encoding circuit having a configuration including N SD cores 409 to SD cores 411 that are circuits capable of encoding SD images. In FIG. 4, the SD cores other than the SD core 409, SD core 410, and SD core 411 are not shown because they are omitted. The N SD cores 409 to SD 411 are installed corresponding to the buffers 405 to 407, respectively.

  Reference numeral 412 denotes an encoded video signal encoded by the SD core 409. Similarly, reference numerals 413 and 414 denote encoded video signals encoded by the SD core 410 and the SD core 411. Signals output from SD cores other than the SD core 409, SD core 410, and SD core 411 are not shown.

  Reference numeral 415 denotes a determination circuit, and in the SD recording mode, the S / N ratio of the video encoded signal 413 to the video encoded signal 414 is calculated using the video encoded signal 413 to the video encoded signal 414 and the input signal from the imaging unit 401. It is a circuit to calculate. The determination circuit 415 obtains an optimal encoding parameter for the current SD image signal based on the calculated SN ratio and the like in the SD recording mode, and outputs the encoding parameter to the SD core 409.

  Reference numeral 424 denotes a switch having a function equivalent to that of the switch 112 shown in FIG. Although omitted in FIG. 4 for the sake of clarity, the switch 424 is connected to the output terminals of the SD cores 409 to 411 similarly to the switch 112 of FIG. The video encoding signals 412 to 414 output from the SD core 411 are selectively output according to the control of the determination circuit 415. Note that the control of the switch 424 in the SD recording mode in the present embodiment is controlled so that the video encoded signal 412 is always selected and output unlike the first embodiment. In the HD recording mode, the output of each SD core is sequentially selected and output.

  Reference numeral 416 denotes a video stream buffer that temporarily stores the encoded video signals 412 to 414. The video signal encoding method of this video camera is similar to that of the first embodiment. H.264 and the like, and the audio signal encoding method is MPEG audio, AC3, AAC, and the like.

  The recording process of the video camera shown in FIG. 4 will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart showing recording processing of the video camera shown in FIG. Note that steps S501 to S503, S508 to S509, and S510 to S513 in FIG. 5 are the same as steps S201 to S203, S208 to S209, and S210 to S213 shown in FIG.

  Following step S503, in step S504, the controller 422 controls and switches the switch 402 and the switch 403 so that the SD image signal input from the imaging unit 401 is stored in the buffers 405 to 407. At this time, the same data (SD image signal for one frame) is stored in the buffers 405 to 407. When the SD recording mode is set, the controller 422 sets different encoding parameter values for the SD cores 410 to 411. The SD image signals stored in the buffer 406 to the buffer 407 are input to the SD core 410 to the SD core 411 given different encoding parameter values. As a result, the encoded video signal 413 is output from the SD core 410 and the encoded video signal 414 is output from the SD core 411. The encoding parameters given to each SD core will be described later in detail.

  Next, in step S505, the video encoded signals 413 to 414 encoded by combining the above encoding parameters and the input signal (SD image signal) from the imaging unit 401 are input to the determination circuit 415. The determination circuit 415 evaluates the image quality degradation using the SD image signal and the video coded signals 413 to 414, and selects the coding parameter used by the SD core that has generated the video coded signal with the least image quality degradation.

  Also, the determination circuit 415 evaluates the generated code amount using the SD image signal and the video encoded signals 413 to 414, and uses the SD core that has generated the video encoded signal with the smallest generated code amount. Select parameters.

  Further, the determination circuit 415 evaluates the image quality deterioration and the generated code amount using the input signal and the encoded signal encoded with the above-described encoding parameters, and generates a video encoded signal with little image quality deterioration and a small generated code amount. The encoding parameter used by the generated SD core is selected.

  The determination circuit 415 is configured to compare the S / N ratio in units of current pictures, but is not limited to units of pictures, and slices or macroblocks may be used as units of comparison. At this time, when a slice is used as a comparison unit, the determination is performed by performing decoding processing on one slice and comparing the SN ratio. Similarly, a macroblock is determined by performing decoding processing with one macroblock and comparing its SN ratio.

  Next, in step S506, the determination circuit 415 sets the selected encoding parameter in the SD core 409. Next, in step S507, the SD core 409 reads out and encodes the SD image signal from the buffer 405 based on the encoding parameter set from the determination circuit 415, and outputs a video encoded signal 412.

  Next, in step S508, the recording circuit 420 multiplexes the video encoded signal and the audio encoded signal and records them on the recording medium 421. The encoding parameters used in the present embodiment are the same as those described in the first embodiment and the second embodiment. However, the present invention is not limited to this, and various encoding parameters used in the encoding process can be used. May be used. Further, the operation of the video camera of the present embodiment when the recording mode is the HD recording mode is the same as the operation of the first embodiment, and therefore will be omitted.

  As described above, in the video camera according to the present embodiment, the determination circuit 415 selects an optimal encoding parameter, and the SD core 409 encodes the SD image signal based on the encoding parameter. Compared to the above, the other SD cores 410 to 411 can be effectively used to generate a high-quality video encoded signal and record it on the recording medium 421.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows schematic structure of the video camera in the 1st Embodiment of this invention. It is a flowchart which shows the video recording process of the video camera in 1st Embodiment shown in FIG. It is a figure which shows schematic structure of the video camera (imaging device) in 2nd Embodiment. It is a figure which shows schematic structure of the video camera (imaging device) in 3rd Embodiment. 5 is a flowchart showing an operation of the video camera shown in FIG.

Explanation of symbols

101, 301, 401 Imaging unit 102, 103, 302, 303, 402, 403 Switch 104, 304, 404 Frame buffer 105, 106, 305, 306, 405, 406, 407 Buffer 107, 307, 408 HD encoding circuit 108 , 109, 308, 309, 409, 410, 411 SD core 110, 111, 310, 311, 412, 413, 414 Video encoded signal 112, 312, 424 Switch 113, 313, 415 Determination circuit 114, 314, 416 Video Stream buffer 120, 320, 422 controller

Claims (3)

An image processing apparatus capable of encoding a first moving image signal having a first resolution and a second moving image signal having a resolution higher than the first resolution,
Based on the operation of the operation unit, either the first processing mode for encoding the first moving image signal or the second processing mode for encoding the second moving image signal is executed. Mode judging means for judging whether or not
Encoding group means capable of encoding the second moving image signal in real time by combining a plurality of encoding means capable of encoding the first moving image signal in real time;
Input means for inputting the first moving image signal or the second moving image signal to the plurality of encoding means;
When the mode determination unit determines that the first processing mode is selected, the input unit is controlled to input the first moving image signal in parallel to each encoding unit in the plurality of encoding units. Input control means for
When the mode determining means determines that said first processing mode, and parameter setting means for setting the motion search service Chieria as each different coding parameter values for each encoding means in said plurality of encoding means ,
When the mode determining means determines that said first processing mode, the reference to each encoding means for said parameter setting means sets the different motion search service Chieria indicates the motion vector calculated by performing a motion search, respectively A specifying means for comparing a difference absolute value sum between a macroblock of an image and an encoding target macroblock, and specifying a moving image encoded signal output by an encoding means that calculates a value having the smallest difference absolute value sum;
When the mode determining unit determines that the first processing mode is selected, the moving image encoded signal specified by the specifying unit is output from the plurality of moving image encoded signals output from the plurality of encoding units. An image processing apparatus comprising: an output control unit that outputs the output as When the mode determination unit determines that the second processing mode is selected, the input control unit outputs a plurality of frames of the second moving image signal for each encoding unit in the plurality of encoding units. Controlling the input means to input one of the divided areas,
When the mode determining means determines that the second processing mode, the parameter setting means sets the same encoding parameter value for each encoding means in the plurality of encoding means,
When the mode determination unit determines that the second processing mode is selected, the output control unit sets the plurality of moving image encoded signals output from the plurality of encoding units as output target signals in the order corresponding to the division. The image processing apparatus according to claim 1, wherein the image processing apparatus is controlled to output.   The image processing apparatus according to claim 1, wherein the input unit includes an imaging unit that captures an image of a subject and outputs the first moving image signal or the second moving image signal.

Images