JP4791057B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a matrix display type plasma display panel (hereinafter referred to as PDP).

  At present, as a thin image display device, a plasma display device on which an AC type (AC discharge type) plasma display panel is mounted has been commercialized (see, for example, FIG. 2 of Patent Document 1).

A PDP 10 as a plasma display panel mounted on such a plasma display device includes column electrodes D _{1 to} D _m as address electrodes, and row electrodes X _{1 to} X _n arranged orthogonal to the column electrodes, and Row electrodes Y _{1 to} Y _n are provided. The PDP 10 has a structure in which a discharge cell corresponding to a pixel is formed at each intersection of a pair of row electrodes X and Y adjacent to each other and a column electrode.

  In this plasma display device, gradation display using the subfield method is performed on the PDP 10 to display an image corresponding to an input video signal (see, for example, FIGS. 3 to 5 of Patent Document 1). That is, in each of the 14 subfields SF1 to SF14 for each one field display period, a pixel data writing process Wc for setting each discharge cell to one of the lighting mode and the extinguishing mode based on the input video signal. Then, the sustain light emission process Ic in which only the discharge cells set in the lighting mode are repeatedly discharged and emitted is performed. Further, the reset process Ic for initializing the states of all the discharge cells is executed only in the first subfield. In the reset process Ic, all discharge cells are initialized to the lighting mode by causing reset discharges to occur in all the discharge cells at once and forming a desired amount of wall charges in each discharge cell. .

  Further, in the pixel data writing step Wc, in order to set each discharge cell to either the lighting mode or the extinguishing mode based on the input video signal, the negative scanning pulse is sequentially applied to each of the row electrodes, and the extinction is performed. A high voltage is applied to the column electrode to which the discharge cell to be set in the mode belongs, and a low voltage pixel data pulse is applied to the column electrode to which the discharge cell to be set in the lighting mode belongs. As a result, only a discharge cell to which a high-voltage pixel data pulse is applied causes a discharge (selective erasure discharge) between the column electrode and the row electrode in the discharge cell. By this selective erasing discharge, wall charges existing in the discharge cell are erased, and the discharge cell is set to the extinguishing mode. On the other hand, since the discharge as described above is not generated in the discharge cell to which the low-voltage pixel data pulse is applied, the state immediately before that is maintained. That is, the discharge cell in which the desired amount of wall charges remains is maintained in the lighting mode and the discharge cell extinction mode in which the wall charge amount is not in the desired amount.

  Here, by causing the selective erasure discharge only in one of the subfields within one field display period, the sustain light emission process of each subfield until the selective erasure discharge is generated. The discharge light emission is continuously performed at Ic, and the luminance corresponding to the total number of the discharge light emission is visually recognized (see, for example, FIG. 5 of Patent Document 1).

  However, in order to set the discharge cell to the extinguishing mode in the pixel data writing process Wc, the selective erasure discharge may not be correctly generated even when a high voltage pixel data pulse is applied to the column electrode to which the discharge cell belongs. It was.

  Therefore, for the discharge cells to be set to the extinguishment mode, the pixel data pulse that causes the selective erasing discharge is repeatedly applied in the pixel data writing process Wc of each successive subfield, whereby the selective erasing discharge opportunity. A driving method has been proposed in which the discharge is surely generated (see, for example, FIG. 29 of Patent Document 1).

However, when a pixel data pulse for causing a selective erasure discharge in each discharge cell is periodically applied to the column electrode, a back substrate (not shown) on which the column electrode is formed and a row electrode are formed. There is a case where a front transparent substrate (not shown) is vibrated, and an unpleasant abnormal sound is generated.
JP 2000-231362 A

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for driving a plasma display panel that can remove abnormal noise caused by vibration of the plasma display panel itself. .

2. The plasma display panel driving method according to claim 1, wherein a discharge cell corresponding to a pixel is formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction crossing each of the row electrode pairs. A method of driving a plasma display panel in which gradation is driven in N (N: an integer greater than or equal to 2) subfields for each unit display period, wherein the plasma display panels are adjacent to each other within the unit display period One or a plurality of subfield groups consisting of M (M: integer less than or equal to N) subfields are provided, and in the subfield group, the first subfield puts all the discharge cells into a lighting mode state. A reset process to be initialized and an address line for setting the discharge cell to either the lighting mode or the extinguishing mode according to the input video signal And a sustain process for sustaining only the discharge cells set in the lighting mode, and the subfields other than the head include the address process and the sustain process, and the input video within the subfield group A first pixel data pulse is applied to the discharge cell to cause a selective discharge that causes the discharge cell to transition to the extinguishing mode in the address process of one subfield corresponding to the luminance level indicated by the signal. Then, a second pixel data pulse for causing the selective discharge is applied to the discharge cell in the address process of a subfield subsequent to the one subfield, and an average luminance level of the input video signal is a predetermined luminance. If the level is lower than the level, the previous subfield group Reducing the number of subfields for applying a pre-Symbol second pixel data pulse to the discharge cells.

According to a fourth aspect of the present invention, there is provided a plasma display panel driving method comprising: a discharge cell corresponding to a pixel at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction crossing each of the row electrode pairs; Is a plasma display panel driving method in which gradation is driven in N (N: an integer greater than or equal to 2) subfields for each unit display period, in the unit display period. One or a plurality of subfield groups consisting of M (M: integers less than or equal to N) subfields adjacent to each other are provided, and in the subfield group, the first subfield includes all the discharge cells in the extinguishing mode. A reset process for initializing the state, and an address for setting the discharge cell to either the lighting mode or the extinguishing mode according to the input video signal. And a sustain process for sustaining only the discharge cells set in the lighting mode, and the subfields other than the head include the address process and the sustain process, and the input is performed within the subfield group. A first pixel data pulse is applied to the discharge cell to cause a selective discharge that causes the discharge cell to transition to a lighting mode in the address process of one subfield corresponding to the luminance level indicated by the video signal. And applying a second pixel data pulse for causing the selective discharge to occur in the address process of a subfield subsequent to the one subfield to the discharge cell, and an average luminance level of the input video signal is predetermined. When it is higher than the luminance level, it is within the subfield group compared to the case where it is lower. Reducing the number of subfields for applying a pre-Symbol second pixel data pulse to the discharge cells.

  The state of the discharge cell by applying the first pixel data pulse to the discharge cell in one subfield corresponding to the luminance level indicated by the input video signal in a subfield group consisting of a plurality of continuous subfields. And a second pixel data pulse for generating the selective discharge again in each of the subfields subsequent to the one subfield is applied to the discharge cells. In the driving for repeatedly sustaining only the discharge cells set in the lighting mode, when the average luminance level of the input video signal is lower than the predetermined luminance level, it is within the subfield group as compared with the case where it is high. To reduce the number of second pixel data pulses to be applied to the discharge cells.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus that drives a plasma display panel (hereinafter referred to as a PDP) to emit light based on a driving method according to the present invention.

In FIG. 1, a PDP 10 as a plasma display panel extends column electrodes D _{1 to} D _m arranged in the vertical direction (vertical direction) of the two-dimensional display screen and extends in the horizontal direction (horizontal direction). Arranged row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n are formed. Note that one display line of the PDP 10 is displayed by a pair of row electrodes X and Y adjacent to each other. A discharge space (not shown) in which a discharge gas is sealed is provided between the row electrodes X _{1 to} X _n and Y _{1 to} Y _n and the column electrodes D _{1 to} D _m. A discharge cell corresponding to a pixel is formed at each intersection of a row electrode and a column electrode including

  The A / D converter 1 samples an analog input video signal, converts it to, for example, 8-bit pixel data PD corresponding to each pixel, and converts this to the average luminance calculation circuit 2 and the pixel drive data generation circuit 3. Supply to each.

  Based on the pixel data PD, the average luminance calculation circuit 2 calculates an average luminance level for each image frame (or one field) based on the input video signal, and drives and controls an average luminance signal APL indicating the average luminance level. Supply to circuit 4.

  The pixel drive data generation circuit 3 performs a multi-gradation process on the pixel data PD, and then sets each discharge cell of the PDP 10 to either the lighting mode or the non-lighting mode for each subfield. Is converted to pixel drive data GD and supplied to the memory 5.

  FIG. 2 is a diagram showing an example of the internal configuration of the pixel drive data generation circuit 3.

In FIG. 2, the multi-gradation processing circuit 31 performs error diffusion processing and dither processing on 8-bit pixel data PD. For example, in the error diffusion process, first, the upper 6 bits of the pixel data PD are regarded as display data, and the remaining lower 2 bits are regarded as error data. Then, the weighted addition of each error data of the pixel data PD corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the multi-gradation processing circuit 31 supplies the upper 4 bits of the dither addition pixel data to the data conversion circuit 32 as the multi-gradation pixel data PD _S.

When a drive mode signal KS indicating the light emission drive pattern A (described later) is supplied, the data conversion circuit 32 drives the multi-gradation pixel data PD _S according to the data conversion table shown in FIG. Convert to data GD. On the other hand, when the driving mode signal KS indicating emission driving pattern B (described later) is supplied, the data conversion circuit 32, the multi-gradation pixel data PD _S to 14 bits according to the data conversion table shown in FIG. 4 To pixel drive data GD. The first to fourteenth bits of the pixel drive data GD correspond to subfields SF1 to SF14, which will be described later, respectively.

The memory 5 sequentially writes the pixel drive data GD in accordance with the write signal supplied from the drive control circuit 4. Then, one screen, the pixel drive data GD ₁₁ words corresponding to the pixels of the first row and the first column, up to the pixel driving data GD _nm corresponding to pixels of the n row and m-th column (n × m) When the writing of the pixel drive data GD is completed, the memory 5 performs the following read operation.

First, in the memory 5, pixel drive data GD _{(1,1) to} GD _{(n, m)} written for one screen is divided into pixel bits for each bit digit (1st bit to 14th bit). It is considered as data bits DB1 to DB14. Then, the memory 5 reads the pixel drive data bits DB1 _{(1,1) to} DB1 _{(n, m)} for each display line and supplies them to the address driver 6 in the address process W of the subfield SF1 described later. Further, in the address process W of the subfield SF2, which will be described later, the memory 5 reads the pixel drive data bits DB2 _{(1,1) to} DB2 _{(n, m)} by one display line and supplies them to the address driver 6. Similarly, the memory 5 reads out the pixel drive data bits DB3 to DB14 for one display line and supplies them to the address driver 6 in each address process W of subfields SF3 to SF14 described later.

  The drive control circuit 4 generates a clock signal to be supplied to the A / D converter 1 and a write and read signal to be supplied to the memory 5 in synchronization with the horizontal and vertical synchronization signals in the input video signal. To do.

  Further, the drive control circuit 4 determines whether or not the average luminance level of one frame (or one field) indicated by the average luminance signal APL supplied from the average luminance calculation circuit 2 is higher than a predetermined luminance level. Determine. At this time, when the luminance level is higher than the predetermined luminance level, the drive control circuit 4 supplies a drive mode signal KS indicating the light emission drive pattern A (described later) to the pixel drive data generation circuit 3. On the other hand, when the average luminance level is smaller than the predetermined luminance level, the drive control circuit 4 supplies a drive mode signal KS indicating the light emission drive pattern B (described later) to the pixel drive data generation circuit 3.

  Further, the drive control circuit 4 generates various timing signals to be displayed by driving based on 14 subfields SF1 to SF14 as shown in FIG. This is supplied to each of the electrode driver 7 and the Y electrode driver 8. Each of the subfields SF1 to SF14 includes only an address process W for setting each discharge cell of the PDP 10 to one of the lighting mode and the extinguishing mode according to the input video signal, and only the discharge cell set to the lighting mode. A sustain process I in which sustain discharge is repeatedly performed and the light emission state associated with the discharge is maintained. Only the first subfield SF1 includes a reset process R for initializing all the discharge cells to the lighting mode state immediately before the address process W.

  Each of the address driver 6, the X electrode driver 7, and the Y electrode driver 8 generates various drive pulses as shown in FIG. 6 in each subfield in response to various timing signals supplied from the drive control circuit 4. Applied to electrodes X and Y. In FIG. 6, only SF1 and SF2 are extracted from the subfields SF1 to SF14.

6, in the reset stage R, the first sustain driver 7 and second sustain driver 8, a reset pulse RP _x and RP _Y with respect PDP10 the row electrodes X ₁ to X _n and Y ₁ to Y _n, respectively at the same time Apply. Depending on the application of the reset pulse RP _x and RP _Y, reset discharge is caused in all the discharge cells of the PDP 10. After the end of the reset discharge, a predetermined amount of wall charges are uniformly formed in each discharge cell, and all the discharge cells in the PDP 10 are initialized to the lighting mode.

In the address process W, the address driver 6 generates a pixel data pulse having a predetermined positive voltage when the pixel drive data bit DB is at logic level 0, and 0 V when the pixel drive data bit DB is at logic level 1. the to the column electrodes D ₁ to D _m by one display line (m bits). For example, in the address step W of the subfield SF1, the address driver 6, first, m pieces of pixel drive data bits DB1 corresponding to the first display line of the PDP10, as shown in FIG. 6 _(1,1) ~DB1 _(1, the m generates pixel data pulses DP1 ₁ according to the logic level of _m) each, simultaneously applied to the respective column electrodes D ₁ to D _m. Then it generates m pixel data pulses DP1 ₂ in accordance with the PDP10 logic level of the second display m pixel drive data bits DB1 corresponding to the line _{(2,1) ~DB1 (2, m} ) of each , And simultaneously applied to the column electrodes D _{1 to} D _m , respectively. In the same manner, the address driver 6 applies pixel drive data bits DB1 _{(3,1) to} DB1 _{(3, m)} , DB1 ₍ corresponding to the third, fourth,..., Nth display lines of the PDP 10. _{4,1) to} DB1 _{(4, m)} ,..., DB1 _{(n, 1) to} DB1 _{(n, m)} m pixel data pulse groups DP1 ₃ , DP1 ₄ , corresponding to the respective logic levels. ..., DP1 _n are sequentially applied to the column electrodes D _{1 to} D _m . During this time, the Y electrode driver 8 generates a negative scan pulse SP as shown in FIG. 6 at the same timing as the application timing of each pixel data pulse group DP, and this is applied to the row electrodes Y ₁ to Y _n . Apply sequentially. At this time, discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the row electrode Y to which the scan pulse SP is applied and the column electrode to which the pixel data pulse having a positive polarity is applied. The wall charge remaining in the cell is erased. Therefore, this discharge cell is set to the extinguishing mode. Note that since the selective erasing discharge is not generated in the discharge cells belonging to the column electrodes to which the pixel data pulse having the positive polarity of the predetermined voltage as described above is not applied, the discharge cells maintain the state just before. That is, a discharge cell in which a predetermined amount of wall charges remains is in the lighting mode, while a discharge cell in which the amount of wall charges is not equal to the predetermined amount remains in the extinguishing mode.

In the sustain process I, the X electrode driver 7 and the Y electrode driver 8 each have the sustain pulses IP _X and IP _{Y as} shown in FIG. 6 as many as the number corresponding to the luminance weighting value assigned to each subfield as follows. the repeatedly applied to the row electrodes X ₁ to X _n and Y ₁ to Y _n.

SF1: 1
SF2: 3
SF3: 5
SF4: 8
SF5: 10
SF6: 13
SF7: 16
SF8: 19
SF9: 22
SF10: 25
SF11: 28
SF12: 32
SF13: 35
SF14: 39
Then, each time the sustain pulses IP _X and IP _Y are applied, only the discharge cells set in the lighting mode are discharged (sustain discharge), and the light emission state associated with the discharge is maintained.

Whether or not each discharge cell is subjected to the sustain discharge in the sustain process I of each of the subfields SF1 to SF14 is determined according to the pixel drive data GD as shown in FIG. 3 or FIG. According to the pixel drive data GD, as shown by the light emission drive pattern A or B in FIG. 3 or FIG. 4, one subfield (indicated by a black circle) corresponding to the level of the luminance gradation to be expressed. In order to cause the first selective erasing discharge, a pixel data pulse having a positive polarity and a predetermined voltage is applied to the column electrode. As a result, the discharge cell transitions to the extinguishing mode, and therefore the discharge cell initialized to the lighting mode in the reset process R of the first subfield SF1 exists until the selective erasing discharge occurs. Each subfield (indicated by white circles) is in the lighting mode state, and sustain discharge is continuously generated in these subfields. In the drive shown in FIGS. 5 and 6, the opportunity to change the discharge cell from the extinguishing mode to the lighting mode within one frame (or one field) display period is the reset process R of the first subfield SF1. Only. Therefore, the discharge cells that have once been subjected to selective erasure discharge and set to the extinguishing mode after SF1 will maintain this extinguishing mode state until the last subfield SF14. At this time, the intermediate luminance corresponding to the total number of sustain discharges generated in each of the subfields SF1 to SF14 is visually recognized. That is, according to 15 types of light emission drive patterns as shown in FIG. 3 or FIG.
{0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150, 182, 217, 255}
The intermediate luminance for 15 tones is expressed.

  Here, in the light emission drive pattern A or B shown in FIG. 3 or FIG. 4, one subfield (indicated by a black circle) corresponding to the level of the luminance gradation to be expressed within one frame (or one field) display period. 1), the first selective erasure discharge is generated. However, this selective erasure discharge may not be correctly generated.

  Therefore, in the light emission drive pattern A shown in FIG. 3, after applying the first pixel data pulse to cause the first selective erasure discharge (indicated by a black circle) in the address process W of one subfield. Also, in the address process W of each subfield up to the last subfield SF14, the second pixel data pulse to be repeatedly generated for the second and subsequent selective erasure discharges (indicated by black triangles) is applied. It is. That is, in preparation for the case where the first selective erasure discharge as described above is not correctly generated, the sub-fields up to the last subfield SF14 after the first selective erasure discharge is performed are also described. Repeatedly in the field, a drive (application of a pixel data pulse having a positive predetermined voltage) to cause the second and subsequent selective erasure discharges is performed.

  However, when a pixel data pulse that should repeatedly cause selective erasure discharge is applied to the column electrode in each successive subfield for the same discharge cell, the front transparent substrate on which the row electrode is formed and the column electrode are formed. There is a case in which the back substrate that vibrates may vibrate, and there arises a problem that unpleasant abnormal sound is generated. In particular, when low-luminance driving is performed, application of a pixel data pulse that should cause the second and subsequent selective erasing discharges (indicated by black triangles in FIG. 3) is more effective than when high-luminance driving is performed. Since the number of subfields to be increased increases, the probability of occurrence of abnormal sounds increases.

  Therefore, in the plasma display device shown in FIG. 1, when the average luminance level of the input video signal is higher than the predetermined luminance level, the driving based on the light emission driving pattern A as shown in FIG. Driving based on the light emission driving pattern B as shown in FIG. 4 is performed. That is, when the average luminance level of the input video signal is low, the number of times that the second and subsequent selective erasure discharges (indicated by black triangles) should be generated is reduced. In other words, even if each successive subfield induces abnormal noise, the number of subfields to which pixel data pulses for causing the second and subsequent selective erasure discharges are applied is reduced. The probability of occurrence of panel vibration (abnormal sound) accompanying application of a typical pixel data pulse decreases.

  The predetermined luminance level is, for example, the average of the video signals input when the video signal having various average luminance levels is input, when abnormal sounds generated when the video signals are input in advance. Use the brightness level. The predetermined level includes the sub-fields SF1 to SF14 in which the front sub-field of at least two consecutive sub-fields in which abnormal sounds are particularly prominent is turned on and the rear sub-field is turned off. It is also possible to use the gradation luminance level at the time. For example, in the case where abnormal sounds remarkably appear in the subfields SF12 and SF13, as shown in FIG. 3 or FIG. 4, it is visually recognized when the sustain discharge is continuously performed in the subfields SF1 to SF12. The luminance “182” is set as the predetermined luminance level.

  In the above embodiment, when the average luminance level of the input video signal is higher than the predetermined luminance level, the second and subsequent selective erasing discharges are performed as indicated by the black triangles of the light emission drive pattern A in FIG. The process is continuously executed up to the last subfield SF14. However, the second and subsequent selective erasure discharges do not necessarily have to be executed continuously until the last subfield is reached. Further, when the average luminance level of the input video signal is lower than the predetermined luminance level, as shown by the black triangle mark of the light emission drive pattern B in FIG. Although the drive that should be caused to occur in the field is performed, the number of times that the second and subsequent selective erasure discharges should be caused is not limited to three.

  In short, when the average luminance level of the input video signal is lower than the predetermined luminance level, it is only necessary to perform driving with a reduced number of times that the second and subsequent selective erasing discharges should occur, compared to the case where the average luminance level is higher. It is. At this time, both the light emission drive patterns A and B are driven so that the second selective erasure discharge is generated at least in the subfield immediately after the first selective erasure discharge is not generated correctly. Should be done.

  Note that, as shown in FIG. 3, the number of times of performing the drive for causing the selective erasure discharge within one frame display period is the largest when the luminance level to be expressed is zero. That is, when each of the subfields SF1 to SF14 has a period for inducing abnormal sounds, the entire screen of the display screen has a luminance level of 0, and the occurrence probability of panel vibration (abnormal sound) is the highest at the time of so-called black display. It can be said that it is expensive.

  Therefore, only when black display is performed, the number of times of driving that should cause the second and subsequent selective erasure discharges may be reduced. That is, the predetermined brightness level is set to a brightness level that is one level higher than the average brightness level when the entire display screen is black.

  In the above embodiment, as a driving method for gray-scale driving the PDP 10, a predetermined amount of wall charges are formed in advance in all the discharge cells and selectively formed in each discharge cell based on the input video signal. The operation in the case where the so-called selective erasure address method for erasing the wall charges is described. However, the wall charges are erased from all the discharge cells (reset process R), and a discharge (selective writing discharge) is selectively generated in each discharge cell based on the input video signal to form a predetermined amount of wall charges. (Address process W) The case where a so-called selective write address method is adopted can be similarly implemented. At this time, the drive control circuit 4 adopts the light emission drive sequence shown in FIG. 7 in place of the light emission drive sequence shown in FIG. 5, and when the average luminance level of the input video signal is lower than the predetermined luminance level, it is shown in FIG. While the driving based on the light emission driving pattern A shown in FIG. 9 is performed, the driving based on the light emission driving pattern B shown in FIG.

  Further, in the above embodiment, the subfield group (SF1 to SF14) for executing the sustain discharge in the subfields continuous by the number corresponding to the gradation luminance level to be expressed is displayed in one frame (one field) display period. However, the present invention is also applicable to the case where a plurality of such subfield groups are provided within one frame (one field) display period.

1 is a diagram illustrating a configuration of a plasma display apparatus for driving a plasma display panel by a driving method according to the present invention. It is a figure which shows the internal structure of the pixel drive data generation circuit 3 shown by FIG. It is a figure which shows the data conversion table corresponding to the light emission drive pattern A, and the drive by the light emission drive pattern A. FIG. It is a figure which shows the data conversion table corresponding to the light emission drive pattern B, and the drive by the light emission drive pattern B. FIG. It is a figure which shows an example of the light emission drive sequence at the time of driving PDP10 shown by FIG. It is a figure which shows the application timing of the various drive pulses applied to PDP10 shown by FIG. It is a figure which shows another example of the light emission drive sequence at the time of driving PDP10 shown by FIG. It is a figure which shows the operation | movement by the light emission drive pattern A employ | adopted when driving by employ | adopting the selective writing address method. It is a figure which shows the operation | movement by the light emission drive pattern B employ | adopted when drive | operating by employ | adopting the selective writing address method.

Explanation of main part codes

2 Average luminance calculation circuit 3 Pixel drive data generation circuit 4 Drive control circuit 10 PDP

Claims (5)

A plasma display panel in which discharge cells corresponding to pixels are formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs is provided for each unit display period. A driving method of a plasma display panel that performs gradation driving in N (N: an integer of 2 or more) subfields,
One or a plurality of subfield groups consisting of M (M: integer less than or equal to N) subfields adjacent to each other within the unit display period are provided. A reset process for initializing the discharge cells to the lighting mode, an address process for setting the discharge cells in one of the lighting mode and the extinguishing mode according to an input video signal, and the discharge set in the lighting mode. A sustain process for sustaining only the cells, and the subfield other than the head includes the address process and the sustain process,
In the subfield group, a first discharge is generated to cause the discharge cell to transition to the extinguishing mode in the address process of one subfield corresponding to the luminance level indicated by the input video signal. Applying a pixel data pulse to the discharge cell, applying a second pixel data pulse to the discharge cell to cause the selective discharge in the addressing step of a subfield subsequent to the one subfield;
The number of subfields average luminance level of the input video signal is to apply a pre-Symbol second pixel data pulse to the discharge cell in the subfield in the group compared is higher if it is lower than a predetermined luminance level A method of driving a plasma display panel, comprising: reducing the number of plasma display panels.   2. The method of driving a plasma display panel according to claim 1, wherein the average luminance level is an average luminance level for one frame or one field in the input video signal.   2. The plasma display panel driving method according to claim 1, wherein the predetermined luminance level is a luminance level that is one level higher than an average luminance level when the entire display screen is black. A plasma display panel in which discharge cells corresponding to pixels are formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in a direction intersecting each of the row electrode pairs is provided for each unit display period. A driving method of a plasma display panel that performs gradation driving in N (N: an integer of 2 or more) subfields,
One or a plurality of subfield groups consisting of M (M: integer less than or equal to N) subfields adjacent to each other within the unit display period are provided. A reset process for initializing the discharge cells to the extinguishing mode, an address process for setting the discharge cells to one of the lighting mode and the extinguishing mode according to an input video signal, and the discharging set to the lighting mode A sustain process for sustaining only the cells, and the subfield other than the head includes the address process and the sustain process,
In the subfield group, a first discharge is generated to cause the discharge cell to transition to the lighting mode in the addressing process of one subfield corresponding to the luminance level indicated by the input video signal. Applying a pixel data pulse to the discharge cell, applying a second pixel data pulse to the discharge cell to cause the selective discharge in the addressing step of a subfield subsequent to the one subfield;
The number of subfields average luminance level of the input video signal is to apply a pre-Symbol second pixel data pulse to the discharge cell in the subfield in groups as compared to the case lower when higher than the predetermined luminance level A method of driving a plasma display panel, comprising: reducing the number of plasma display panels.   5. The method of driving a plasma display panel according to claim 4, wherein the average luminance level is an average luminance level for each frame or field in the input video signal.

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