JP4781373B2 - Storage device - Google Patents

Description

  The present invention relates to a storage device that stores data used in computers and various electronic devices.

  In recent years, a memory card represented by a compact flash (registered trademark; the same applies hereinafter) and a USB memory are widely used as external storage devices for computers. These external storage devices incorporate a flash memory that is a rewritable nonvolatile ROM. There are flash memory types called SLC (Single Level Cell) type and MLC (Multi Level Cell) type (for example, see Patent Document 1 below).

JP 2002-8380 A

  The SLC flash memory is a memory that has been widely used in the past, and is a memory capable of storing 1-bit information per single cell (hereinafter also referred to as “binary memory”). On the other hand, the MLC flash memory is a memory capable of storing information of 2 bits or more per single cell (hereinafter also referred to as “multi-level memory”). MLC-type flash memory has four states: each cell is fully charged, power remains two-thirds, one-third remains, and all cells are discharged. 2 bits of information can be stored per cell.

  In general, the MLC type flash memory has a feature that its operation is slow and the number of rewritable times is small, whereas the storage capacity is larger than that of the SLC type. On the other hand, the SLC type flash memory is characterized in that it operates at high speed and has a large number of rewritable times, but has a smaller storage capacity than the MLC type.

  In view of such problems, the problem to be solved by the present invention is to provide a storage device that takes advantage of the features of both the SLC flash memory and the MLC flash memory.

Based on the above problems, a memory device which is one embodiment of the present invention is configured as follows.
A storage device capable of storing data based on a predetermined file system that records data management information at the beginning of the storage area, having a first storage area, and capable of storing two types of values per unit cell A binary flash memory, a multi-value flash memory having a second storage area wider than the first storage area and capable of storing three or more values per unit cell, and a host connected to the storage device A comparison unit that compares an address designated by the apparatus with a predetermined threshold value determined based on the maximum capacity of the first storage area; and, if the address is within the threshold value, data A control unit that switches the read / write destination to the binary flash memory, and switches the read / write destination to the multi-level flash memory when the address is an address that exceeds the threshold The control unit uses the value of the address as it is even when the read / write destination is switched to either the binary flash memory or the multi-level flash memory, and the binary flash memory or By reading / writing data from / to the multilevel flash memory, the second storage area of the multilevel flash memory is not used for the storage area corresponding to the address within the threshold, A storage area corresponding to an address exceeding a threshold is used, and the control unit returns a storage capacity of the second storage area when receiving an inquiry about the storage capacity of the storage apparatus from the host device. A storage device.
Further, the present invention can be realized as the following aspects.

  That is, a storage device capable of storing data based on a predetermined file system that records data management information at the beginning of the storage area, has a first storage area, and stores two types of values per unit cell A possible binary flash memory, a multi-value flash memory having a second storage area and capable of storing three or more types of values per single cell, and the first storage area arranged in the head area, The gist of the present invention is to include a control unit that logically couples the first storage area and the second storage area and reads and writes data as a combined area that is a single storage area.

  According to the storage device of the above aspect, the first storage area of the binary flash memory is arranged at the head of the combined area. Therefore, data management information such as a file allocation table is written in the binary flash memory. Since the file allocation table is management information that is frequently rewritten when data is written or erased, a binary flash memory that can operate faster than a multi-level flash memory can be placed at the beginning of the combined area. Thus, it becomes possible to store data at a higher speed than a storage device in which all areas are constituted by multi-level flash memories. In addition, binary flash memory is characterized in that it can be rewritten more times than multi-level flash memory, so writing frequently allocated file allocation tables to binary flash memory improves data storage reliability. It becomes possible to make it. As described above, according to the storage device of the above aspect, the storage device is excellent in high-speed operation and reliability by using the binary flash memory while realizing a large capacity by using the multi-level flash memory. It becomes possible to provide.

  In the storage device according to the aspect described above, the control unit is configured to respond to the result of the address conversion, the address conversion unit that performs address conversion between the combined region, the first storage region, and the second storage region. The data read / write destination may be selected from the binary flash memory and the multilevel flash memory. According to such an aspect, it is possible to easily determine the data read / write destination according to the result of the address conversion.

  In the storage device of the above aspect, the control unit transmits a command for reading and writing the data after transmitting the address converted by the address conversion unit to the binary flash memory and the multilevel flash memory. The data may be transmitted to the selected memory.

  In such an aspect, the converted address is transmitted to all the memories, and then the command is transmitted only to the selected memory. According to such an aspect, it is not necessary to select the transmission destination of the converted address from the binary flash memory and the multi-level flash memory, so that the processing speed can be improved.

  In the storage device of the above aspect, the first storage area may be an area that occupies any ratio of 0.5% to less than 100% of the combined area. By setting the first storage area to such an area, management information such as a file allocation table can be reliably stored in the binary flash memory.

  In the storage device of the above aspect, the storage device may be connected to a host device via a predetermined interface, and the control unit may read and write the data in response to an instruction from the host device. . With such an aspect, the storage device can be used as an external storage device or an internal storage device of the host device. As the predetermined interface, for example, an interface such as USB, IEEE 1394, parallel ATA, or serial ATA can be used.

  In the storage device of the above aspect, the control unit may include means for returning the storage capacity of the combined area when receiving an inquiry about the storage capacity of the storage device from the host device. With such an aspect, it becomes possible to notify the host device of the capacity of the entire combined area, not the storage capacity of each flash memory.

  The storage device according to the above aspect includes a plurality of the multi-level flash memories, and the control unit arranges the first storage area in a head area, and the first storage area and the plurality of second storages. The area may be logically coupled. According to such an aspect, since it can be set as the aspect provided with two or more multi-value flash memories, the memory | storage device which has a large capacity | capacitance storage area can be provided.

The present invention can also be applied as a storage device having the following mode. That is, a storage device capable of storing data based on a predetermined file system that records data management information at the beginning of the storage area,
A binary flash memory having a first storage area and capable of storing two types of values per unit cell;
A multi-value flash memory having a second storage area wider than the first storage area and capable of storing three or more values per unit cell;
A comparison unit that compares an address designated by a host device connected to the storage device with a predetermined threshold value determined based on the maximum capacity of the first storage area;
When the address is within the threshold, the data read / write destination is switched to the binary flash memory, and when the address exceeds the threshold, the read / write destination is And a control unit that switches to a value flash memory.

  In the storage device of this aspect, by performing simple control of switching the data read / write destination between the multi-level flash memory and the binary flash memory according to the designated address, the memory having different characteristics can be stored. Data can be read from and written to. As a result, it is possible to provide a storage device that is excellent in high-speed operation and reliability by using a binary flash memory while realizing a large capacity by using a multi-level flash memory.

  In the storage device of the above aspect, the control unit uses the address value as it is even when the read / write destination is switched to either the binary flash memory or the multi-level flash memory. Data reading / writing may be performed on the value flash memory or the multi-value flash memory. According to such an aspect, it is not necessary to convert the address designated by the host device into an address of another system, so that the process can be simplified.

  In the storage device of the above aspect, the control unit may include means for returning the storage capacity of the second storage area when receiving an inquiry about the storage capacity of the storage device from the host device. . The maximum storage capacity of the storage device according to the above-described aspect matches the second storage area. For this reason, the storage capacity of the storage device can be notified to the host device by a simple process of returning the storage capacity of the second storage area as it is.

  Hereinafter, in order to further clarify the operation and effect of the present invention described above, embodiments of the present invention will be described based on examples.

A. First embodiment:
FIG. 1 is an explanatory diagram showing a schematic configuration of a storage device 10 as an embodiment of the present invention. The storage device 10 of this embodiment is connected to a host device 80 represented by a computer via a USB interface, and is used as an external storage device. The host device 80 formats the storage device 10 with a predetermined file system (FAT16, FAT32, etc.) and reads / writes data.

  As shown in the figure, the storage device 10 includes a main controller 20, and is further connected to the main controller 20, each of which has a NAND flash memory, a second memory unit 40, a first memory unit 40, and a second memory unit 40. 3 memory units 50 and a fourth memory unit 60 are provided.

  The first memory unit 30 includes a binary memory 31 that is an SLC (Single Level Cell) type NAND flash memory. The first memory unit 30 also includes a first unit controller 32 that controls the binary memory 31 according to its electrical characteristics. In this embodiment, a general-purpose compact flash memory controller is employed as the first unit controller 32. The first unit controller 32 receives commands and data based on the ATA standard from the main controller 20, and reads / writes data from / to the binary memory 31. In the present embodiment, the first memory unit 30 has a storage area for 1 Gbyte. If one binary memory 31 cannot realize a 1 Gbyte storage area, a plurality of binary memories 31 can be connected to the first unit controller 32 to realize a 1 Gbyte storage area. Good.

  The second memory unit 40 includes a multi-level memory 41 which is an MLC (Multi Level Cell) type NAND flash memory. The multi-value memory 41 of the present embodiment is a memory capable of storing quaternary (2-bit) information. Of course, as the multi-value memory 41, a memory capable of storing information of three values or more can be appropriately adopted. The second memory unit 40 further includes a second unit controller 42 that controls the multi-level memory 41 according to its electrical characteristics. In the present embodiment, as the second unit controller 42, a general-purpose compact flash memory controller is employed as in the first memory unit 30. The third memory unit 50 and the fourth memory unit 60 have the same configuration as the second memory unit 40. In the present embodiment, each of the second memory unit 40, the third memory unit 50, and the fourth memory unit 60 has a storage area of 15 Gbytes. Therefore, the storage device 10 of this embodiment has a storage area for 46 G (1G + 15G + 15G + 15G) bytes as a whole. In addition, when a storage area of 15 Gbytes cannot be realized with one multilevel memory, a storage area of 15 Gbytes may be realized by connecting a plurality of multilevel memories to the unit controller.

  The main controller 20 is an integrated circuit that controls reading and writing of data from and to each of the memory units 30 to 60 in accordance with an instruction from the host device 80 connected via the USB interface. The main controller 20 includes a bus conversion circuit 21 and a unit management circuit 22 as internal circuits.

  The bus conversion circuit 21 has a function of converting a signal based on the USB standard received from the host device 80 into a signal based on the ATA (Advanced Technology Attachment) standard. ATA is a standard communication interface between a computer and a storage device. The signals based on the ATA standard include, for example, three address signals A0 to A2, 16 data signals D00 to D15, and a control signal such as a reset signal.

  The unit management circuit 22 has a function of logically combining the storage areas of the binary memory and the multi-value memory included in each of the memory units 30 to 60 and handling them as a single storage area. The unit management circuit 22 realizes logical connection of the memory units 30 to 60 by performing address conversion based on an LBA (Logical Block Addressing) address of the ATA signal converted by the bus conversion circuit 21. LBA is a system in which serial numbers are assigned to all sectors in a storage area, and sectors to be accessed are designated by the serial numbers. The LBA address is represented by this serial number. The “LBA address” is also called “LBA parameter”.

  FIG. 2 is an explanatory diagram showing the concept of address conversion performed by the unit management circuit 22. On the left side of the figure, storage areas of the memory units 30 to 60 managed by the unit management circuit 22 are shown. As shown in the figure, in this embodiment, the storage area in the first memory unit 30 is represented by LBA addresses from “0” to “W”. The second memory unit 40 is an LBA from “0” to “X”, the third memory unit is from “0” to “Y”, and the fourth memory unit is an LBA from “0” to “Z”. It is represented by an address.

  The right side of FIG. 2 shows the storage area after the storage areas of the memory units 30 to 60 are combined. As shown in the figure, the unit management circuit 22 arranges the storage area of the binary memory 31 included in the first memory unit 30 in the head area, and then the multi-value memories 41 to 41 included in the other memory units 40 to 60. 61 storage areas are arranged. As shown in FIG. 2, the combined storage area is represented by LBA addresses from “0” to “W + X + Y + Z”. When the unit management circuit 22 performs the storage area combination in this way, the host device 80 recognizes the storage area in the storage device 10 as represented by continuous LBA addresses from “0” to “W + X + Y + Z”. It becomes possible. In the following description, the storage area after combination is referred to as “combined area UA”.

  FIG. 3 is a block diagram schematically showing the internal configuration of the unit management circuit 22. The unit management circuit 22 has a function of transferring an ATA command and data issued from the host device 80 to each of the memory units 30 to 60 in addition to the address conversion described above. FIG. 3 shows an internal configuration for realizing this transfer function.

  Each of the unit controllers 32 to 62 included in each of the memory units 30 to 60 includes eight types of registers called command block registers conforming to the ATA standard. The eight types of registers are (1) feature register, (2) sector count register, (3) device / head register, (4) cylinder high register, (5) cylinder low register, and (6) sector number register, respectively. , (7) command register, and (8) data register. The unit controllers 32 to 62 control reading and writing of data with respect to the binary memory and the multivalued memory according to various parameters set in these registers. The host device 80 transmits access signals for these registers to the storage device 10 when reading and writing data.

  When the unit management circuit 22 receives the above-described access signal from the host device 80 via the USB interface and the bus conversion circuit 21, the unit management circuit 22 transfers the access signal to each of the memory units 30 to 60 according to the type of the register to be accessed. Is variable. The unit management circuit 22 includes a register determination circuit 78 in order to determine the type of register to be accessed.

  The register discriminating circuit 78 discriminates the type of register to be accessed based on the ATA standard according to the state of the address signals A0 to A2 input from the bus conversion circuit 21. For example, if the address signal A2 is “0”, the address signal A1 is “0”, and the address signal A0 is “1”, the register determination circuit 78 determines that an access signal to the feature register is input, as shown in the figure. can do.

  When the unit management circuit 22 receives an access signal for the feature register and the sector count register from the host device 80, the unit management circuit 22 directly passes through and transfers the access signal to all the memory units 30-60. This is because these registers are not for directly specifying the position in the combined area UA. Specifically, the feature register is a register used to specify various parameters according to the ATA command, and the sector count register specifies the number of sectors when accessing a plurality of sectors in succession. It is a register to do. For the designation of the “first sector” for continuous access, a device / head register, a cylinder high register, a cylinder low register, and a sector number register, which will be described later, are used.

  The device / head register, the cylinder high register, the cylinder low register, and the sector number register are registers used for designating a position (sector) in the combined area UA. Each of these registers receives a part of an LBA address representing a sector in the combined area UA. Specifically, if the LBA address is a 28-bit parameter, the bit string from the 0th bit to the 7th bit is input to the sector number register, and the bit string from the 8th bit to the 15th bit is input to the cylinder row register. Is entered. Also, a bit string from the 16th bit to the 23rd bit is input to the cylinder high register, and a bit string from the 24th bit to the 27th bit is input to the device / head register. When the unit management circuit 22 receives the access signals for these registers, the unit management circuit 22 once latches the signals in the latch circuits 70 to 73 and stores them.

  The access signal latched by the latch circuits 70 to 73 is input to the address decoder 90. The address decoder 90 has a function of combining the LBA addresses that are discretely stored in the latch circuits 70 to 73 and restoring the LBA address having a 28-bit length. The address decoder 90 also has a function of comparing the restored LBA address with the maximum number of sectors in each memory unit. Details of this function will be described later.

  The command register is a register for designating various commands based on the ATA standard. Examples of such commands include a read sector command for reading data from a designated sector and a write sector command for writing data to a designated sector. When the unit management circuit 22 receives a command signal for the command register, the unit management circuit 22 inputs the signal to the command decoder 91 and the latch circuit 74.

  When a command signal is input, the command decoder 91 determines the type of the input command and outputs the determination result to the address conversion circuit 92 and the unit selector 94. The command signal input to the latch circuit 74 is held in the latch circuit 74 until an output instruction is issued from the unit selector 94.

  As shown in FIG. 2, the address conversion circuit 92 has a function of converting the LBA address for the combined area UA input from the address decoder 90 into an LBA address for each of the memory units 30 to 60. Specifically, the address conversion circuit 92 receives an LBA address from the address decoder 90 and further receives a command type from the command decoder 91. Then, it is determined whether the type of the input command is a command that requires an LBA address. A command that requires an LBA address is generally a command that designates an address (sector) and performs some access to the designated address. For example, a “read sector command”, “write sector command”, There are “read multiple command”, “write multiple command”, “read DMA command”, “write DMA command”, “read verify sector command”, “seek command”, and the like. If the address conversion circuit 92 determines that the type of the input command is a command that requires an LBA address, the address conversion circuit 92 converts the LBA address input from the address decoder 90 into an LBA address for each memory unit (for the conversion method). The LBA address after conversion is transferred to all the memory units 30 to 60. As will be described later, the main controller 20 does not simultaneously transfer an ATA command that requires an LBA address to a plurality of memory units. Therefore, the converted LBA address is transferred to all the memory units 30 to 60. can do. By doing so, the address conversion circuit 92 can omit the process of selecting the transfer destination. Of course, the converted LBA address may be transferred only to the corresponding memory unit.

  If the type of the command input from the command decoder 91 is a command that does not require an LBA address, the address conversion circuit 92 transfers the parameter input from the address decoder 90 to all the memory units 30-60 as it is. This is because, in the case of a command that does not require an LBA address, the access signal input to the device / head register or the like does not always represent the LBA address. A command that does not require an LBA address is a command that performs some operation on the flash memory without specifying an address (sector). For example, an “identify device command”, “set feature command”, “ There are “check power mode command”, “sleep command”, “standby command”, “idle command” and the like. Note that, even when the command type input from the command decoder 91 is a command that does not require an LBA address, the address conversion circuit 92 applies to the memory units 30 to 60 in the same manner as a command that requires an LBA address. It is also possible to send the converted LBA address. This is because a command that does not require an LBA address is a command that is executed regardless of the presence or absence of the LBA address. Of course, it is possible to adopt a configuration in which the conversion is performed but the LBA address after the conversion is not transmitted.

  The unit selector 94 is a circuit that selects a command transfer destination memory unit based on the LBA address input from the address decoder 90. Specifically, the unit selector 94 receives an LBA address from the address decoder 90 and further receives a command type from the command decoder 91. Then, it is determined whether the type of the input command is a command that requires an LBA address. If the command requires an LBA address, the unit selector 94 performs processing to select a command transfer destination memory unit based on the input LBA address. Details of this processing will be described later. When the unit selector 94 selects a transfer destination memory unit, the unit selector 94 controls the first switch circuit 96 to connect the transfer destination memory unit and the latch circuit 74. Then, the command signal held in the latch circuit 74 is transferred to the selected memory unit.

  The timing at which the command signal held in the latch circuit 74 is output to each unit is such that the LBA address after address conversion is transmitted from the address conversion circuit 92 to each memory unit, and the unit selector 94 causes the first switch circuit 96 to The timing is set after the switching is completed. This is because the ATA standard stipulates that the LBA address needs to be set in the register in advance before transmitting a command that requires the LBA address. If the type of the input command is a command that does not require an LBA address, the unit selector 94 controls the first switch circuit 96 so as to connect the latch circuit 74 to all the memory units. In this way, a command that does not require an LBA address can be transferred to all memory units. When the type of the input command is a command that does not require an LBA address, the latch circuit 74 may not delay the output of the command.

  When the unit selector 94 controls the first switch circuit 96 based on the input LBA address, the unit selector 94 also controls the second switch circuit 98 in the same manner. The second switch circuit 98 is a switch for switching an access signal for the data register. When the second switch circuit 98 is switched by the unit selector 94, the data signal is also transferred to the same memory unit to which the command requiring the LBA address is transferred.

  A status storage circuit 79 is connected between the second switch circuit 98 and the register determination circuit 78. The status storage circuit 79 stores a capacity (total number of sectors) of the entire combined area UA and a device ID representing manufacturer information of the storage device 10. Normally, when acquisition of status information is requested from the host device 80, status information is returned from the memory unit selected by the second switch circuit 98. However, for example, when there is an inquiry about the total number of sectors that the storage device 10 has or an inquiry about the device ID by an “identify device” command or the like, the status storage circuit 79 sends a request to the host device 80. Status information is returned. As described above, when the status information can be returned from the status storage circuit 79, the status information relating to the entire storage device 10 that cannot be handled by each memory unit can be accurately transmitted to the host device 80. Become.

  FIG. 4 is a flowchart showing the flow of address conversion processing realized by the address decoder 90 and the address conversion circuit 92 and memory unit selection processing realized by the unit selector 94. Hereinafter, such processing is referred to as “unit management processing” for convenience.

  The address conversion circuit 92 determines whether the command type input from the command decoder 91 is a command that requires an LBA address (step S10). As a result, if the command does not require an LBA address (step S10: No), the address conversion circuit 92 transfers the parameters input to the device head register and the like as they are to all units without performing address conversion. To do. On the other hand, the unit selector 94 selects all the memory units (step S20) and ends the process. By doing so, the same command is transferred to all the memory units. As described above, even if it is determined in step S10 that a command that does not require an LBA address is input, the address conversion circuit 92, as in the case of a command that requires an LBA address, Address conversion may be performed.

  In step S10, if the input command is a command that requires an LBA address (step S10: Yes), the address decoder 90 determines that the input LBA address n is the maximum value W of the LBA address of the first memory unit 30. (Refer to FIG. 2) It is determined whether it is the following (step S30). If the LBA address n is less than or equal to the maximum value W (step S30: Yes), the address conversion circuit 92 sets the converted LBA address m as the LBA address n as it is input from the address decoder 90 (step S40). . In this case, the unit selector 94 selects the first memory unit 30 as a command transfer destination (step S50).

  When it is determined in step S30 that the LBA address n is not less than or equal to the maximum value W of the LBA address of the first memory unit 30 (step S30: No), the address decoder 90 determines that the LBA address n is the first value. It is determined whether the maximum value W of the LBA address of the memory unit 30 is equal to or less than the sum (W + X) of the maximum value X of the LBA address of the second memory unit 40 (step S60). If the LBA address n is less than or equal to the sum (W + X) (step S60: Yes), the address conversion circuit 92 converts the LBA address m after conversion from the LBA address n to the maximum LBA address of the first memory unit 30. The value W is subtracted (step S70). In this case, the unit selector 94 selects the second memory unit 40 as a command transfer destination (step S80).

  If it is determined in step S60 that the LBA address n is not less than the sum (W + X) (step S60: No), the address decoder 90 determines that the LBA address n is the LBA address of the first memory unit 30. It is determined whether the maximum value W is equal to or less than the sum (W + X + Y) of the maximum value W, the maximum value X of the LBA address of the second memory unit 40, and the maximum value Y of the LBA address of the third memory unit 50 (step S90). If the LBA address n is less than or equal to the sum (W + X + Y) (step S90: Yes), the address conversion circuit 92 sets the LBA address m after conversion to a value obtained by subtracting W and X from the LBA address n ( Step S100). In this case, the unit selector 94 selects the third memory unit 50 as a command transfer destination (step S110).

  If it is determined in step S90 that the LBA address n is not less than the sum (W + X + Y) (step S90: No), the address decoder 90 determines that the LBA address n is the LBA address of the first memory unit 30. Less than the sum (W + X + Y + Z) of the maximum value W, the maximum value X of the LBA address of the second memory unit 40, the maximum value Y of the LBA address of the third memory unit 50, and the maximum value Z of the fourth memory unit 60 It is determined whether or not there is (step S120). If the LBA address n is less than or equal to the sum (W + X + Y + Z) (step S120: Yes), the address conversion circuit 92 sets the converted LBA address m to the value obtained by subtracting W, X, and Y from the LBA address n. (Step S130). In this case, the unit selector 94 selects the fourth memory unit 60 as a command transfer destination (step S140).

  If it is determined in step S120 that the LBA address n is not less than the sum (W + X + Y + Z) (step S90: No), an LBA address exceeding the combined area UA is designated. Therefore, in this case, predetermined error processing is executed (step S150). The predetermined error process is, for example, a process of discarding a command currently input. According to the unit management processing described above, it is possible to easily perform address conversion and memory unit selection with only a simple comparison operation.

  The configuration and operation of the storage device 10 according to the present embodiment have been described above. As described above, the storage device 10 according to the present embodiment performs address conversion so that the binary memory 31 that is an SLC flash memory is allocated at the head of the combined area UA. Therefore, when the storage device 10 is formatted by a file system such as FAT16 or FAT32, a file allocation table (hereinafter referred to as “FAT information”), which is data management information, is generated in the binary memory 31. Become. The FAT information is management information that is frequently rewritten when data is written or erased. In this embodiment, an SLC type flash memory having a higher writing speed than the MLC type flash memory (multi-value memories 41 to 61) is arranged in an area where such management information is written. Therefore, according to the present embodiment, by adopting the MLC type flash memory, the capacity can be increased, and the data writing speed is remarkably improved as compared with the storage device constituted only by the MLC type flash memory. It becomes possible to improve. Note that the writing speed of the MLC flash memory is approximately 600 nsec, and the writing speed of the SLC flash memory is approximately 200 nsec.

  Here, a comparative example of the writing speed is shown. As is well known, in FAT16 and FAT32, two pieces of FAT information having the same contents are written in the management information. Then, if the storage device is configured only by the MLC flash memory, it takes 600 nsec to rewrite the first FAT information, 600 nsec to rewrite the second FAT information, and 600 nsec to rewrite the data. Then, it takes 1800 nsec as a whole. On the other hand, in this embodiment, since the SLC type flash memory is used in the area where the FAT information is written, 200 nsec is used for rewriting the first FAT information, 200 nsec is used for rewriting the second FAT information, It takes 600 nsec to rewrite data (in the multi-level memory). As a result, data rewriting is completed in 1000 nsec as a whole. That is, according to this example, it is possible to reduce the data rewrite time by about 45% with respect to the storage device configured only by the MLC flash memory.

  In general, the SLC type flash memory has about 10 to 20 times the number of times data can be rewritten as compared to the MLC type flash memory. Therefore, the reliability of data storage can be greatly improved by arranging the SLC flash memory in an area where management information that is frequently rewritten is written as in this embodiment. As a result, it can be easily used not only as an external storage device but also as a boot drive for an operating system as in a conventional hard disk.

  In this embodiment, a compact flash controller is used as a unit controller for controlling a binary memory or a multi-level memory. In general, the compact flash is highly versatile and can control flash memories having various characteristics. Therefore, if a compact flash controller is provided for each memory unit as in this embodiment, even if a flash memory of a different manufacturer is adopted for each memory unit, the difference in characteristics can be absorbed to operate normally. Is possible. As a result, it is possible to easily configure a storage device in which a binary memory or a multilevel memory is mounted. In this embodiment, a compact flash controller is employed as the unit controller, but an SD memory controller or a multimedia card controller may be used.

  In the present embodiment, the functions of the main controller 20 are configured in hardware. On the other hand, the main controller 20 may be configured as a microcomputer incorporating a CPU, a ROM, and a RAM, thereby realizing the above-described address conversion and unit management functions as software. Alternatively, a RAID chip may be adopted as the main controller 20, and each memory unit may be controlled by causing the RAID chip to perform a spanning operation.

  In the present embodiment, a total of four memory units are provided, but the number is not limited. At least one memory unit including a binary memory and one memory unit including a multi-level memory may be used.

  In this embodiment, the capacity of the binary memory is 1 Gbyte, but this capacity can be determined as follows. For example, assume that the storage device 10 is formatted with FAT32, and the total storage capacity of the storage device 10 is x gigabytes. In FAT32, since the capacity of 4 Kbytes per sector is expressed in many cases, the total number of sectors is (x / 4) mega. Further, in FAT32, a data amount of 4 bytes is required to express one address. Therefore, a capacity of x megabytes (= 4 bytes * (x / 4) mega) per one piece of FAT information is required. As described above, in FAT32, in most cases, two pieces of FAT information are written, so that a management area of (2 * x) megabytes is required in total. As management information, not only FAT information but also information such as a master boot record and a directory entry is recorded, so that a management area larger than that is necessary as a whole. As a specific example, if the total capacity of the storage device 10 is 128 gigabytes, the capacity required for the FAT information is 256 megabytes by the above-described calculation method. Furthermore, if an area for recording a master boot record, a directory entry or the like is added to this, a binary memory having a capacity of about 500 megabytes as a whole is required. In other words, at least 0.5% of the binary memory capacity is required for the entire area of the storage device 10 (the combined area UA). Can be remembered. Of course, since the binary memory has characteristics superior to the multi-level memory in terms of operation speed and reliability, the capacity may exceed 1%.

B. Second embodiment:
FIG. 5 is an explanatory diagram showing a schematic configuration of a storage device as a second embodiment of the present invention. As shown in the figure, the storage device 110 of this embodiment includes a main controller 20, a first memory unit 30 on which a binary memory 31 is mounted, and a second memory unit 40 on which a multi-level memory 41 is mounted. . The main controller 20 includes a bus conversion circuit 21 and a unit management circuit 122 as in the first embodiment. Among these, the unit management circuit 122 according to the present embodiment determines the target of data reading / writing between the first memory unit 30 and the second memory unit 40 in accordance with the address, data, and command designated by the host device 80. It has a function to switch between.

  FIG. 6 is an explanatory diagram showing the concept of memory unit switching control performed by the unit management circuit 122. 6, in order from the left side, the entire storage area UA2 of the storage device 110, the storage area of the first memory unit 30, and the storage area of the second memory unit 40 when the storage device 110 is viewed from the host device 80. It shows.

  In this embodiment, the storage area in the first memory unit 30 is represented by LBA addresses from “0” to “W”. On the other hand, the storage area in the second memory unit 40 is represented by LBA addresses from “0” to “X”. The LBA address “X” is a value larger than the LBA address “W”.

  In this embodiment, when the LBA address from “0” to “W” is designated by the host device 80, the unit management circuit 122 sets the target of data read / write as the first memory unit in which the binary memory 31 is mounted. Switch to 30. On the other hand, when an LBA address exceeding “W” is designated, the unit management circuit 122 switches the data read / write target to the second memory unit 40 in which the multilevel memory 41 is mounted. That is, in this embodiment, the unit management circuit 122 switches the memory unit to be used by comparing the LBA address designated by the host device 80 with the threshold “W”. As a result of performing the switching control as described above, in this embodiment, an unused area (LBA addresses “0” to “W”) is generated in a part of the second memory unit 40.

  FIG. 7 is a block diagram schematically showing the internal configuration of the unit management circuit 122. As shown in the figure, the unit management circuit 122 of this embodiment includes a register determination circuit 178, a switching control circuit 194, a first switch circuit 196, and a second switch circuit 198.

  The register determination circuit 178 is connected to the bus conversion circuit 21 shown in FIG. Similar to the first embodiment, the register determination circuit 178 determines the type of the register to be accessed based on the ATA standard according to the state of the address signals A0 to A2 input from the bus conversion circuit 21. Then, the access signal received from the bus conversion circuit 21 is transferred to the switching control circuit 194 according to the determined register type.

  The switching control circuit 194 selects the memory unit to be accessed based on the type of the register to be accessed determined by the register determination circuit 178 and the address, data, and command specified by the host device 80, as the first memory unit 30. And the second memory unit 40 are controlled to be switched.

  The first switch circuit 196 opens and closes the connection between the bus conversion circuit 21 and the first memory unit 30 based on an instruction from the switching control circuit 194.

  The second switch circuit 198 opens and closes the connection between the bus conversion circuit 21 and the second memory unit 40 based on an instruction from the switching control circuit 194.

  As shown in the figure, the switching control circuit 194 includes an address decoder 190, an address comparison circuit 192, a size register 179, and a command decoder 191.

  The address decoder 190 analyzes the LBA address designated by the host device 80 based on the access signals for the device / head register, cylinder high register, cylinder low register, and sector number register. The command decoder 191 analyzes a command instructed from the host device 80.

  The size register 179 stores a threshold value determined based on the maximum capacity of the first memory unit 30. In this embodiment, the maximum capacity of the first memory unit 30 is 512 Mbytes, and the threshold value stored in the size register 179 is an LBA address indicating a capacity of 480 Mbytes slightly smaller than the maximum capacity. And This is because there are cases where a missing block (bad block) may occur in the flash memory, and all 512 Mbytes may not be used. Of course, the LBA address representing the maximum capacity of the first memory unit 30 may be stored as it is as the threshold value. Note that 480 Mbytes can be expressed as “0000000011110000000000000000” in a binary number according to the LBA method. Therefore, if the threshold is 480 Mbytes, the specified address depends on whether the value of the upper 8 bits of the 28-bit LBA address specified by the host device 80 is “00000000” or more. Can exceed the threshold value (480 Mbytes). That is, the address comparison circuit 192, which will be described later, can easily use the 4-bit device / head register and the upper 4 bits of the 8-bit cylinder high register without using the values of the cylinder low register and the sector number register. It is possible to determine whether or not the threshold value has been exceeded.

  The address comparison circuit 192 compares the LBA address analyzed by the address decoder 190 with the threshold value stored in the size register 179, and, as shown in FIG. The selection is made between the memory unit 30 and the second memory unit 40.

  FIG. 8 is an explanatory diagram showing details of the switching operation performed by the switching control circuit 194. In the figure, “switching” refers to accessing the memory unit selected by the address comparison circuit 192. On the other hand, “simultaneous access” refers to performing the same access to both the first memory unit 30 and the second memory unit 40 regardless of the selection by the address comparison circuit 192. .

  In FIG. 8, “when writing” indicates a situation in which a write command is issued from the host device 80. The write command includes a command write instruction for the command register, a data write instruction for the data register, and a write instruction for various parameters such as an LBA address for other registers. “Reading” indicates a situation in which a read command is issued from the host device 80. The read command includes instructions for reading various statuses and data from the memory unit.

  As shown in FIG. 8, as a general rule, access to the data register and the command register is performed to the memory unit selected by the address comparison circuit 192 both at the time of writing and at the time of reading. On the other hand, access to other registers is performed only on the selected memory unit at the time of reading, and the same access is made to the two memory units at the time of writing. Registers other than the data register and command register are mainly registers for designating addresses. Therefore, as long as data and commands to be written are appropriately transferred to the selected memory unit, the registers of both the first memory unit 30 and the second memory unit 40 are written during writing. This is because there is no problem even if the same address is written.

  Note that “exception 1” in FIG. 8 indicates that the command transferred from the host device 80 as a result of analyzing the command by the command decoder 191 is an operation of the entire memory unit such as an idle command or a standby command. This is a case of a command for switching the state. When such a command is transferred, the switching control circuit 194 exceptionally transfers the command to both the first memory unit 30 and the second memory unit 40.

  8 indicates “exception 2” when the data capacity (total number of sectors) of the storage device 110 is read by an identify device command or the like. In such a case, the switching control circuit 194 exceptionally accesses the second memory unit 40. As shown in FIG. 6, in this embodiment, the data capacity of the storage device 110 is equal to the data capacity of the second memory unit 40.

  As described above, the configuration and operation of the storage device 110 according to the second embodiment have been described. According to the storage device 110 according to the present embodiment, the SLC is placed in the top area of the storage area as in the storage device 10 according to the first embodiment. A type flash memory can be allocated, and an MLC type flash memory can be allocated to other areas. Therefore, frequently rewritten FAT information can be stored in an SLC flash memory having a high number of rewritable times and a high-speed operation. As a result, as in the first embodiment, the data writing speed is higher than that of the storage device configured only by the MLC type flash memory while realizing the large capacity by adopting the MLC type flash memory. The reliability of data storage can be greatly improved.

  Further, according to the storage device 110 of the present embodiment, it is possible to read / write data from / to two types of memory units using the address designated by the host device 80 as it is. As a result, since a circuit that performs complicated address conversion is not required, the circuit scale of the main controller 20 can be reduced. As a result, the manufacturing cost can be reduced.

  As mentioned above, although the various Example of this invention was described, it cannot be overemphasized that this invention is not limited to these Examples, and can take a various structure in the range which does not deviate from the meaning. For example, in the above embodiment, the USB interface is used as an interface for connecting the storage device and the host device, but the type of interface is not limited to this. Various interfaces such as an IEEE 1394 interface, a serial ATA interface, and a parallel ATA interface can be employed.

It is explanatory drawing which shows schematic structure of the memory | storage device as 1st Example. It is explanatory drawing which shows the concept of the address conversion performed by the unit management circuit of 1st Example. It is a block diagram which shows typically the internal structure of the unit management circuit of 1st Example. It is a flowchart of the unit management process in 1st Example. It is explanatory drawing which shows schematic structure of the memory | storage device as 2nd Example. It is explanatory drawing which shows the concept of the switching control of the memory unit performed by the unit management circuit of 2nd Example. It is a block diagram which shows typically the internal structure of the unit management circuit in 2nd Example. It is explanatory drawing which shows the detail of the switching operation performed by the switching control circuit of 2nd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory | storage device 20 ... Main controller 21 ... Bus conversion circuit 22 ... Unit management circuit 30 ... 1st unit 31 ... Binary memory 32 ... 1st unit controller (SLC controller)
40 ... second unit 41, 51, 61 ... multi-value memory 42 ... second unit controller (MLC controller)
DESCRIPTION OF SYMBOLS 50 ... 3rd unit 60 ... 4th unit 70-74 ... Latch circuit 78 ... Register discrimination circuit 79 ... Status memory circuit 80 ... Host apparatus 90 ... Address decoder 91 ... Command decoder 92 ... Address conversion circuit 94 ... Unit selector 96 ... First DESCRIPTION OF SYMBOLS 1 switch circuit 98 ... 2nd switch circuit 110 ... Memory | storage device 122 ... Unit management circuit 178 ... Register discrimination circuit 179 ... Size register 190 ... Address decoder 191 ... Command decoder 192 ... Address comparison circuit 194 ... Switching control circuit 196 ... 1st switch Circuit 198 ... Second switch circuit

Claims (1)

A storage device capable of storing data based on a predetermined file system that records management information of data at the beginning of a storage area,
A binary flash memory having a first storage area and capable of storing two types of values per unit cell;
A multi-value flash memory having a second storage area wider than the first storage area and capable of storing three or more values per unit cell;
A comparison unit that compares an address designated by a host device connected to the storage device with a predetermined threshold value determined based on the maximum capacity of the first storage area;
When the address is within the threshold, the data read / write destination is switched to the binary flash memory, and when the address exceeds the threshold, the read / write destination is A control unit for switching to a value flash memory,
The control unit uses the address value as it is even when the read / write destination is switched to either the binary flash memory or the multilevel flash memory, and the binary flash memory or the multilevel By reading / writing data from / to the flash memory, the second storage area of the multi-level flash memory does not use the storage area corresponding to the address within the threshold value, and exceeds the threshold value. Use the storage area corresponding to the address,
The control unit includes means for returning the storage capacity of the second storage area when receiving an inquiry about the storage capacity of the storage device from the host device.

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