JP4755920B2 - Carrier phase tracking device and pseudo noise code signal tracking device - Google Patents

Description

  The present invention relates to an apparatus for tracking a carrier phase of a carrier signal phase-modulated by data to be superimposed and an apparatus for tracking a pseudo noise code signal modulated for spread spectrum.

  In recent years, GPS receivers have become smaller and have lower power consumption, and are increasingly used in portable devices such as mobile phones. These devices are often used indoors, and the GPS receiver is required to be able to perform positioning even indoors. However, in order to perform positioning, a weak radio signal broadcast from a satellite of 20,000 km above the sky is received indoors, where the S / N ratio deteriorates, and the Doppler frequency and pseudorange are measured. Measurement must be performed, and a dramatic improvement in sensitivity is required compared to conventional receivers. Further, in order to ensure the accuracy of the positioning result even in such a poor environment, it is necessary to improve the accuracy of the so-called observation raw data of the pseudo distance and the Doppler frequency that are information for the positioning calculation.

  As a measure to solve such a problem, a positioning method called assist GPS (A-GPS) was developed by Snaptrack (currently Qualcomm), and KDDI started service in Japan in November 2001. However, in order to perform positioning using the A-GPS method on a mobile phone, it is necessary to communicate with the center station for each positioning request, and communication and positioning service costs are incurred each time. There is a demand for the mobile station (= mobile phone) to be able to perform positioning independently so that KDDI can start positioning with a mobile phone alone since 2003.

  A typical stand-alone GPS receiver that is not the assist GPS has a carrier tracking loop that tracks a carrier and a code tracking loop that tracks a pseudo noise code (PRN code). This carrier tracking loop is executed to perform synchronization with the carrier while maintaining synchronization with the pseudo-noise code in code tracking, and is used to determine the speed of the receiving point by measuring the Doppler shift frequency of the satellite. . On the other hand, the code tracking loop is used for measuring the pseudorange and determining the position of the reception point. Each tracking loop includes an error detector and a loop filter.

  Here, the carrier tracking loop will be described with reference to FIG. In FIG. 1, a carrier NCO 11 is an oscillator that generates a carrier signal at a specified frequency and phase, and a phase error detector 12 calculates a phase difference between the carrier signal (estimated carrier phase) generated by the carrier NCO 11 and an input signal. Ask. The loop filter 13 obtains an appropriate control value for the carrier NCO 11 according to the phase error so that the carrier signal generated by the carrier NCO 11 is synchronized with the carrier phase of the input signal. The phase error detector 12 and the loop filter 13 are actually configured by software processing. In the case of GPS, a 50 bps navigation message is superimposed on the carrier by BPSK (binary phase modulation). Therefore, when the data bit changes from 0 to 1 or from 1 to 0, the phase of the carrier signal changes by 180 °. In order to continue the carrier phase lock even if such a phase jump occurs, a Costas error detector is generally used.

  The phase error detector 12 and the loop filter 13 are largely related to accuracy and sensitivity. In order to improve accuracy and sensitivity, a design policy is conceivable in which the phase error detector 12 improves the S / N ratio of the output with respect to the input error and reduces the noise bandwidth Bn of the loop filter 13. However, the effect of thermal noise can be reduced as Bn is smaller, but the effect of short-term stability of the local oscillator becomes stronger and phase noise increases, so there is a limit to reducing the value of Bn.

  FIG. 2 shows the configuration of the Costas error detector. As described above, the Costas error detector includes the I component multiplier (correlator) 121 and the Q component multiplier (correlator) 122, subtracts each multiplication result by the number of data N, and calculates the product of the two as a phase error. Obtained as θerr. A is a coefficient for gain adjustment.

  As a method for improving the S / N ratio of the phase error detector in order to improve the accuracy and sensitivity described above, it is conceivable to perform smoothing processing by accumulating data used for error detection. However, the GPS L1 band CA code is superimposed with 50 bps data called navigation message in BPSK, and the in-phase signal (I data) in a state where carrier synchronization is maintained is the inversion of bit data of the navigation message ( Hereinafter, the phase is changed by 180 ° simply by “bit inversion”. Therefore, the following problems arise.

  FIG. 3 shows an example of the bit inversion position and period of the navigation message for the I data. Since one bit of the navigation message lasts 20 ms, the polarity of I data is inverted every 20 ms in the shortest cycle. For this reason, for example, when smoothing processing is performed in a 5 ms section, the integrated value in the section including the bit inversion of the navigation message is canceled by the integration of the value with the polarity inverted, and the S / N ratio of the phase error detector deteriorates. The problem arises.

  For the same reason, the integration cannot be performed longer than the time (20 ms) corresponding to one bit of data of the navigation message, and there is a limit to improving the sensitivity of phase error detection.

In order to avoid these problems, in the A-GPS system, the navigation message is transmitted from the base station server to the mobile station, and the mobile station eliminates the effect of bit inversion caused by the navigation message, and the accumulated time Can be extended by 20 ms or more to improve accuracy and sensitivity. Patent Document 1 discloses that the polarity of the pseudo noise code is inverted in accordance with the bit inversion timing of the navigation message.
JP 2005-64983 A

  However, in the spread spectrum signal receiving apparatus disclosed in Patent Document 1, the pseudo noise code generation circuit is configured so that the polarity of the pseudo noise code can be inverted according to the bit inversion timing of the navigation message given from the outside. There is a problem that the circuit configuration becomes complicated.

  Such high-sensitivity GPS can track a signal 15 to 20 dB lower than a classic receiver, but is very unstable at low C / No (Carrier to Noise Ratio), and the Doppler frequency and pseudorange are Although it can be estimated, carrier phase information such as accumulated delta range (ADR) required for applications using carrier phase information such as surveying and RTK cannot be output.

  Accordingly, the first object of the present invention is to use the bit inversion timing information and the phase error detection accuracy and sensitivity without complicating the circuit configuration even when the superimposed data such as the navigation message is not demodulated. It is an object of the present invention to provide a carrier phase tracking device and a pseudo-noise code signal tracking device that improve the frequency.

  The second object is to perform stable carrier phase tracking at low C / No and output the measurement result of carrier phase information.

The carrier phase tracking device according to the present invention inputs a carrier signal generating means for generating a carrier signal, a carrier signal that is binary phase modulated by a bit string of superposition data, and the input based on the carrier signal by the carrier signal generating means to remove the carrier components of the signal, and means for determining the I and Q components of the filtered signal of the carrier component, for said I and Q components, and an integrated value of the predetermined integrated time section, the predetermined integrating period in the obtained integrated value as there is a bit inversion by the phase modulation and, among the product next instruction and obtained as there is no bit reversal in the predetermined integrating period, the larger the integrated value of the values For the effective integration value of the predetermined integration interval, and for the I component and Q component, the effective integration value of the predetermined integration interval Seeking tracking error of the carrier phase based on the integrated value over bits or longer, and means for controlling the phase of the carrier signal generated by said carrier signal generating means in a direction 該追 tail error is reduced.

A pseudo noise code signal tracking device according to the present invention receives a pseudo noise code signal generated by a pseudo noise code signal generating means for generating a pseudo noise code signal and binary phase modulated by a bit string of superimposition data. It said means for obtaining a correlation value between the pseudo noise code signal by the pseudo noise code signal generating means, means for calculating an integrated value of predetermined integrating period component of the correlation values, and the integrated value of the predetermined integrated time section and, said predetermined and the obtained integrated value as there is a bit inversion by the phase modulation in a constant integration interval of the product next instruction and obtained as there is no bit reversal in the predetermined integrating period, the integration of the larger values Based on a value obtained by integrating the effective integration value of the predetermined integration section over a time of 1 bit or more of the superimposition data, and adopting a value as an effective integration value of the predetermined integration section Seeking tracking phase error of the pseudo noise code signal, and means for controlling the phase of the pseudo noise code signal generated by said pseudo noise code signal generating means in a direction 該追 tail phase error is reduced.

Carrier component of the superimposed data by binary phase modulated carrier signal, such as a domestic law message is removed on the basis of the carrier signal generated by the carrier signal generating means, for the I and Q components of the input signal within a predetermined time Of the integrated value obtained with the bit inversion due to the phase modulation of the superimposition data and the integrated value obtained with no bit inversion, the larger integrated value is adopted as the effective integrated value. As a result, even if integration is performed over a time exceeding the time when bit inversion of superimposition data occurs for the I component and Q component, there is no cancellation of the integrated value, and the S / N ratio of the phase error detector can be improved. This improves the accuracy and sensitivity of carrier phase tracking. In addition, the carrier signal generating means does not have to have a function of inverting the polarity of the generated carrier signal, and it is possible to cope with the bit inversion by the arithmetic processing when obtaining the integrated value, so that the apparatus can be complicated. Absent. In addition, since the influence of the 180 ° phase change of the carrier phase due to bit inversion can be removed, tracking by a simple PLL can be performed instead of the Costas loop generally used in the conventional GPS receiver. If a simple PLL is used, the sensitivity can be improved by 6 dB compared to the Costas loop.

A pseudo noise code signal binary phase-modulated by the superimposition of data such as domestic law message, the correlation (integrated) value of the pseudo noise code generated by a pseudo-noise code signal generating means, the predetermined time period of the correlation values The greater of the means for obtaining the integrated value, the integrated value obtained as a result of bit inversion due to phase modulation within a predetermined time of the correlation value, and the integrated value obtained as no bit inversion Is used as the effective integrated value, and the tracking phase error of the pseudo-noise code signal is determined by obtaining the tracking phase error of the pseudo-noise code signal based on the effective integrated value over a time exceeding the time when bit inversion can occur. The S / N ratio is improved, and the tracking accuracy and sensitivity of the pseudo noise code signal can be increased. Moreover, it is not necessary to provide a pseudo noise code signal generating means for inverting and outputting the polarity, and the entire configuration can be simplified.

  A GPS receiving device including a carrier phase tracking device according to a first embodiment of the present invention will be described with reference to each drawing.

  FIG. 4 is a block diagram showing the configuration of the main part of the GPS receiver. In FIG. 4, the AD converter 31 converts the IF signal from the antenna into a digital data string. The IQ separation circuit 32 separates the digital data sequence converted by the AD converter 31 into an I component (in-phase component) and a Q component (90 ° phase difference component). The carrier removal circuit 33 removes the carrier component by multiplying the I signal and the Q signal separated by the IQ separation circuit 32 by the carrier signal generated by the carrier NCO 21, and the amplitude signal of the I signal and the Q signal Is output. The code NCO 37 includes a CA code (P) having a proper (center) phase of the CA code (pseudo noise code signal), a CA code (E) that is 1/2 chip earlier, and a CA code (L) that is 1/2 chip late. Are generated respectively. Multipliers 34IE, 34IP, and 34IL perform multiplication of three CA codes (E), (P), and (L) having different phases from the carrier-removed I signal. Similarly, the multipliers 34QE, 34QP, and 34QL perform multiplication with three CA codes (E), (P), and (L) having different phases from the Q signal from which the carrier is removed.

  The integrator 35 integrates the multiplication results of the six multipliers 34IE, 34IP, 34IL, 34QE, 34QP, and 34QL for, for example, 1 ms to obtain an integrated value.

  The code carrier error detection unit 36 reads the value of the accumulator 35, for example, every 1 ms, and outputs control data to the code tracking loop filter 38 and the carrier tracking loop filter 23, respectively, at a period of several ms. In addition, the carrier phase is tracked and the integrated delta range (ADR) of the carrier phase is output to the outside.

  The carrier tracking loop filter 23 gives estimated carrier frequency data to the carrier NCO 21. As a result, the carrier NCO 21 generates a carrier signal at the estimated carrier frequency and outputs the carrier signal to the carrier removal circuit 33. Further, the code tracking loop filter 38 gives the estimated code phase (the phase of the CA code) to the code NCO 37. As a result, the code NCO 37 generates a CA code at the estimated code phase.

  As will be described later, the code carrier error detection unit 36 obtains control data for the code tracking loop filter 38 and the carrier tracking loop filter 23 in response to bit inversion of the navigation message.

  FIG. 5 is a block diagram showing the correction processing of the integrated value accompanying the bit inversion of the navigation message, which is performed inside the code carrier error detection unit 36 shown in FIG. In the example shown in FIG. 5, a correction pattern in the case where data of a predetermined integration section (for example, a section of 5 ms) of the I signal with the carrier removed is input and bit inversion of the navigation message occurs in the center of the section. Is generated by the correction pattern generation unit 41. The level comparison unit 42 compares the integrated values in the section for the correction pattern generated by the correction pattern generation unit 41 and the input signal I, and calculates the integrated value having the larger value in the section. Obtained as an integrated value.

  For example, as shown in FIG. 6, when a correlation value is obtained in units of 1 ms and an integrated value is obtained every 5 ms, when a bit inversion of a navigation message occurs in 1 ms at the center of a 5 ms section, As shown in (C), the correlation values in the first half 2 ms interval are integrated with the sign inverted.

  This process is expressed as follows.

  Here, Ifirst is the integrated value for the first 2 ms in the 5 ms integration interval shown in FIG. 6B for the I signal, and Isecond is the 3 ms integration value after the 5 ms integration interval. Similarly, Qfirst is the integrated value for the first 2 ms of the Q signal in the 5 ms integration interval, and Qsecond is the 3 ms integration value after the 5 ms integration interval.

  In this way, the integrated values Ifirst and Isecond of the in-phase components of the first half and the second half in a predetermined (5 ms) integration interval are obtained, and the magnitudes of the added value and the subtracted value are compared.

| Ifirst + Isecond | ≧ | Ifirst−Isecond |
As shown in [Equation 1], Ifirst + Isecond is the integrated value I of the in-phase components in the 5 ms integration interval. Similarly, Qfirst + Qsecond is set as the integrated value Q of the in-phase component in the 5 ms integration interval.

If | Ifirst + Isecond | <| Ifirst−Isecond |
In this case, the value of Ifirst-Isecond is I, and similarly, the value of Qfirst-Qsecond is Q.

  As shown in FIG. 6B, if there is a bit inversion of the navigation message from the 2 ms to the 3 ms of the 5 ms integration interval, the polarity of the integration value in the first half (2 ms interval) of the integration interval is inverted and the latter half. By adding to the integrated value of (3 ms section), an integrated value (similar to the case where there is no inversion) is obtained regardless of the inversion of the bit data of the navigation message. Therefore, the integrated value can be obtained over a time exceeding the time at which bit inversion can occur, and high sensitivity can be achieved under a low S / N ratio.

  Then, the phase error Δθ is obtained by the following equation from the values of the integrated values I and Q thus obtained.

  Here, sign () is a sign operator, and sign (I) is a sign of an integrated value I of in-phase components (“1” if positive, “−1” if negative).

The carrier amplitude A is shown in [Equation 2] if Δθ is sufficiently small. A = | I |
Can be obtained.

  Furthermore, if past accumulated values are used successively in succession, the influence of the 180 ° phase change of the carrier phase due to the bit inversion of the navigation message can be eliminated, so this is not a Costas loop generally used in conventional GPS receivers. Tracking with a simple PLL becomes possible. Compared with the Costas loop, the sensitivity can be improved by 6 dB by using a simple PLL.

Here, an example in which past integrated values are successively used will be described with reference to FIG.
FIG. 16A shows an example of the bit inversion position and period of the input signal (navigation message). As shown in this figure, the timing of the processing is performed every 20 ms when the bit inversion of the navigation message can occur, but the data used for the processing is a 20 ms interval only at the first time, and the subsequent processing is a 40 ms interval. That is, in the second and subsequent processes, processing is performed based on the integrated value of the 20 ms section used for the previous process and the integrated value of the new 20 ms section this time.

  FIG. 16B shows the processing timing, input data (data used for processing the input signal), correction data, and post-correction data. As shown in this figure, at processing timing 1, an integrated value of data in the 0 to 20 ms section of the input signal is adopted as correction data. Further, at the processing timing 2, the correction data obtained in the previous time (processing timing 1) is used for the first 20 ms of the 0 to 40 ms section of the input signal, and the correction data is added to the integrated value of the 20 to 40 ms section. A value obtained by adding the correction data to a value obtained by inverting the sign of the integrated value in the 20 to 40 ms section is obtained, and the larger value is used as the corrected data.

  FIG. 16C shows the integrated value after the correction. By integrating the corrected data <1>, <2>, <3>, <4> in this way, the influence of the 180 ° phase change of the carrier phase due to the bit inversion of the navigation message is eliminated. it can.

Next, a GPS receiver including the pseudo noise code signal tracking device according to the second embodiment will be described.
The overall configuration of the GPS receiver is the same as that shown in FIG. Here, a case where the CA code of the L1 band is tracked is taken as an example. The CA code is also performed in the same manner as the carrier phase tracking. This process is expressed as follows.

  Here, Pfirst is the accumulated portion for the first 2 ms in the 5 ms integration section shown in FIG. 6B for the CA code (P) of the appropriate phase of the CA code, and Psecond is the 5 ms integration section. This is the integrated value of 3 ms after. (E−L) first is a difference signal (E−L) between the CA code (E) that is 1/2 chip earlier than the appropriate phase of the CA code and the CA code (L) that is 1/2 chip late. The first 2 ms integration value in the 5 ms integration interval, and (E−L) second is the 3 ms integration value after the 5 ms integration interval.

  In this way, the integrated values Pfirst and Psecond of the appropriate phases of the first and second half CA codes in the predetermined (5 ms) integration interval are obtained, and the magnitudes of the added value and the subtracted value are compared.

| Pfirst + Psecond | ≧ | Pfirst−Psecond |
As shown in [Equation 3], Pfirst + Psecond is set as the integrated value P of the appropriate phase in the 5 ms integration interval. Similarly, (E−L) first + (E−L) second is set as a difference integrated value (E−L) in the 5 ms integration section.

If | Pfirst + Psecond | <| Pfirst−Psecond |
In this case, the value of Pfirst−Psecond is P, and similarly, the value of (E−L) first− (E−L) second is (E−L).

  Then, the CA code phase difference Δτ is obtained by the following equation from the integrated values P and (E−L) thus obtained.

  Here, sign () is a sign operator, and sign (P) is the sign of the integrated value P of the appropriate phase (“1” if positive, “−1” if negative). A is the carrier amplitude.

In this manner, the influence of the 180 ° phase change of the CA code due to bit inversion can be removed also for the CA code. Next, a GPS receiver including the carrier phase tracking device according to the third embodiment will be described.
The first and second embodiments are applied when the bit inversion timing is known. However, in the third embodiment, a means for detecting the bit inversion timing is provided, and integration is performed according to the timing. The processing is performed.

  FIG. 7 is a block diagram showing a loop configuration relating to carrier phase tracking of the GPS receiver shown in FIG. In FIG. 7, a phase error detector 22 detects a phase error between a carrier signal generated by the carrier NCO 21 and an input signal which is a carrier signal to be tracked. The loop filter 23 gives the estimated carrier frequency data to the carrier NCO 21 so that the carrier NCO 21 is controlled in a direction in which the phase error decreases.

  The difference from the conventional carrier tracking loop shown in FIG. 1 is that the phase error detector 22 receives the bit inversion timing information of the navigation message and obtains the phase error by the process described later.

  Even if the navigation message cannot be decoded, if the bit inversion timing is known in this way, the signs of the I and Q components of the carrier signal are inverted and integrated at the bit inversion timing. The manner in which the signs are inverted and added is as shown in FIG.

  8 and 9 are flowcharts and timings for detecting the bit inversion timing of the navigation message.

  Here, the case where the bit inversion timing of the navigation message in which the bit length of one bit is 20 [ms] is detected in the circuit configuration shown in FIG. First, an initial value 0 is substituted into a variable Pmax for obtaining the maximum power value (n1). Also, the integration start timing is initialized (n2). Thereafter, for each 1 [ms], the correlation value of the I component and the correlation value of the Q component obtained by the integrator 35 are sampled and accumulated over 40 [ms], and the integrated value Isum of the correlation value of the I component An integrated value Qsum of correlation values of Q components is obtained. (N2 → n3).

  In FIG. 9, hatching sections indicate sections in which positive integration is performed among the correlation values for 40 [ms]. The remaining section shows a section where negative integration is performed. In the example shown in FIG. 9A, Isum and Qsum are obtained by performing positive integration for 20 [ms] from the beginning and negative integration for the remaining 20 [ms].

Thereafter, the sum of the square of Isum and the square of Qsum is obtained as power P (n4). If this power P is larger than the maximum power value Pmax determined so far, the power P determined this time is updated as Pmax, and the current start timing is stored (n5 → n6 → n7).
Thereafter, the integration start timing is changed, and thereafter the same processing is repeated (n7 → n8 → n9 → n3 →...).

  In this way, as shown in FIGS. 9B to 9C, the interval for performing positive integration and the interval for performing negative integration are sequentially shifted. The start timing at which the power P is maximized is detected as the bit inversion timing.

  FIG. 10 shows an example of the bit inversion timing of the navigation message and the change in the power P when the integration interval of 20 [ms] is changed. As described above, when 20 [ms] from the bit inversion timing of the navigation message to the next inversion timing is positively integrated or negatively integrated, the power P becomes maximum. In addition, the power P is lowest when integration is performed for 20 [ms] before and after the intermediate point from the bit inversion timing to the next bit inversion timing.

  In this way, the signal intensity for the I and Q components of the carrier signal binary-phase-modulated with the superimposition data having a predetermined 1-bit length is set to a 1-bit length from the integration start timing with different integration start timings. The integration start timing at which the integrated value becomes the maximum can be detected as the bit inversion timing.

Next, a GPS receiver including the pseudo noise code signal tracking device according to the fourth embodiment will be described.
In the fourth embodiment, when the bit inversion timing is unknown, the CA code is tracked using the information of the bit inversion timing.

  When the CA code signal is tracked, the integrated value P and (E−L) shown in [Equation 3] are obtained, but when the value of P and (E−L) is obtained, the time other than the bit inversion time is excluded. It is obtained by accumulating the correlation values at the time. FIG. 11 shows this state. In this example, the correlation value is obtained every 1 ms, and the integrated value is obtained every 5 ms. When bit inversion occurs in the center of this 5 ms section (dashed line timing), as shown in (A), the correlation value in the center 1 ms section is 0 for both P and (E−L). Therefore, in other sections excluding such a section where bit inversion occurred, as shown in FIG. 11B, the correlation values after the occurrence of bit inversion are integrated with the sign inverted. In this way, the integrated value P, (E−L) is obtained, and the CA code phase difference Δτ can be obtained by the following equation by the calculation shown in [Expression 4].

  In this way, high sensitivity can be achieved by obtaining the integrated value without using the correlation value in the section where the bit inversion occurs and using the correlation value in the other section.

Next, a GPS receiver including the carrier phase tracking device and the pseudo noise code signal tracking device according to the fifth embodiment will be described.
In the first embodiment, the L1 band CA code is exemplified as the pseudo-noise code. However, the present invention can be similarly applied to an L2C signal obtained by time-division multiplexing a CM code and a CL code. This 2nd Embodiment is related with the GPS receiver provided with the tracking device of the L2C signal.

FIG. 14 is a conceptual diagram showing a code configuration of the L2C signal.
As shown in FIG. 14, the L2C signal has a structure in which a CM code and a CL code are multiplexed on a chip-by-chip basis, and the CM code and the CL code appear alternately in time series. That is, the L2C signal is a time division multiplex code signal.
FIG. 15 is a waveform diagram showing CM (t) corresponding to the CM code and CL (t) corresponding to the CL code.

FIG. 12 is a block diagram showing a carrier phase tracking circuit of the L2C signal tracking device.
This carrier phase tracking circuit includes a carrier phase error calculation unit 1, a carrier NCO2, a carrier loop filter 3, a CM code generator 10a, and a CL code generator 10b. The carrier phase error calculation unit 1 is based on the carrier phase input from the carrier NCO2, the CM code signal input from the CM code generator 10a, and the CL code signal input from the CL code generator 10b. The error is output to the carrier loop filter 3. The carrier loop filter 3 removes unnecessary components accompanying the carrier phase error and outputs the result to the carrier NCO2. The carrier NCO 2 calculates the carrier phase based on the carrier phase error and outputs it to the carrier phase error calculation unit 1. In this way, the carrier phase is tracked by continuously calculating the carrier phase error and the carrier phase in the loop circuit including the carrier phase error calculation unit 1, the carrier loop filter 3, and the carrier NCO2.

  The carrier phase error calculation unit 1 includes a phase rotator (carrier removal circuit) 11, three correlators 12 a to 12 c, a signal conversion circuit 15, and a multiplier / adder 14.

  The phase rotator 11 receives the in-phase component (intermediate I signal) and the quadrature component (intermediate Q signal) of the intermediate frequency L2C signal from the preceding high-frequency processing unit, and also receives the carrier phase from the carrier NCO2. The phase rotator 11 is realized by an LUT (Look-Up-Table) that uses an intermediate I signal, an intermediate Q signal, and a carrier phase as addresses, and in accordance with this LUT, the baseband in-phase component (I signal) and quadrature component (Q Signal). Accordingly, the phase rotator 11 substantially removes the frequency offset and the Doppler frequency component included in the intermediate frequency L2C signal, and outputs a baseband L2C signal.

  The I signal output from the phase rotator 11 is input to the correlator 12a, and the Q signal is input to the correlators 12b and 12c.

  The correlator 12a includes a mixer 121a and an integrator 122a. The mixer 121a mixes the I signal input from the phase rotator 11 and the CM code signal (CM (t) shown in FIG. 11) of the correct timing output from the CM code generator 10a, and the CM code in-phase. The signal is output to the integrator 122a. The accumulator 122a performs correlation processing by accumulating the input CM code in-phase signal according to the period based on the sampling clock input together with the intermediate I signal and the intermediate Q signal from the high frequency processing unit, and performs CM processing. The in-phase correlation signal is output to the signal conversion circuit 15.

  The correlator 12b includes a mixer 121b and an integrator 122b. The mixer 121b mixes the Q signal input from the phase rotator 11 and the CM code signal (CM (t) shown in FIG. 11) of the correct timing output from the CM code generator 10a to obtain a CM code orthogonal signal. Is output to the integrator 122b. The accumulator 122b performs correlation processing by accumulating the input CM code orthogonal signal according to the period based on the sampling clock, and outputs the CM code orthogonal correlation signal to the multiplier / adder.

  The correlator 12c includes a mixer 121c and an integrator 122c. The mixer 121c mixes the Q signal inputted from the phase rotator 11 and the CL code signal (CL (t) shown in FIG. 11) outputted from the CL code generator 10b to obtain a CL code orthogonal signal. Is output to the integrator 122c. The accumulator 122c performs correlation processing by accumulating the input CL code orthogonal signals according to the period based on the sampling clock, and outputs the CL code orthogonal correlation signals to the multiplier / adder 14.

  The signal conversion circuit 15 includes a sigmoid function calculator 150. This sigmoid function is a sign function and takes only a value of “−1” or “+1”.

  The multiplier / adder 14 includes a mixer (multiplier) 141 and an adder 142. The mixer 141 mixes (multiplies) the output signal of the sigmoid function input from the signal conversion circuit 15 and the CM code orthogonal correlation signal input from the correlator 12 b and outputs the CM code correlation signal to the adder 142. . The adder 142 adds the CM code correlation signal input from the mixer 141 and the CL code orthogonal correlation signal input from the correlator 12c and outputs the result. Since this output signal is an addition signal of the CM code correlation signal and the CL code orthogonal correlation signal, it substantially corresponds to the carrier phase error of the L2C signal.

  That is, by using the carrier phase error calculation unit 1 having such a configuration, the carrier phase error can be estimated and calculated by integrating the CM code and the CL code.

  Then, by forming a loop circuit with the carrier phase error calculation unit 1, the carrier NCO2 and the carrier loop filter 3, the CM code and the CL code are integrated and the carrier phase error is continuously estimated and calculated. The carrier phase can be tracked.

  When performing carrier phase tracking of the L2C signal in this way, the carrier phase tracking method shown in the first embodiment is applied to the CM code modulated by the navigation message, and the calculation shown in [Equation 1] is performed. What is necessary is just to obtain | require the value of I component and Q component. That is, the Σ operation of [Equation 1] is applied at the location indicated by [1] in FIG.

FIG. 13 is a block diagram showing the configuration of the code phase tracking circuit of the L2C signal tracking device.
The code phase tracking circuit includes a code phase error calculation unit 5, a code NCO 7, a code loop filter 6, a CM code generator 10a, a CL code generator 10b, and a carrier NCO 2. The code phase error calculator 5 includes a carrier phase input from the carrier NCO2, a CM code signal at a normal timing input from the CM code generator 10a, and a differentiated CM code signal obtained by differentiating the CM code signal at the normal timing. Based on the differential CL code signal obtained by differentiating the CL code signal at the normal timing input from the CL code generator 10b, the code phase error is output to the code loop filter 6. The code loop filter 6 removes unnecessary components accompanying the code phase error and outputs the result to the code NCO 7. The code NCO 7 generates a code enable clock based on the code phase error and outputs it to the CM code generator 10a and the CL code generator 10b. In this way, by continuously calculating the code phase error and the code phase in the loop circuit including the code phase error calculation unit 5, the code loop filter 6, the code NCO 7, the CM code generator 10a, and the CL code generator 10b. Track the code phase. That is, pseudorange observation is continued.

  In the code phase error calculation unit 5, the I signal output from the phase rotator 11 is input to the correlators 12a to 12c, the differential CM code signal from the CM code generator 10a is input to the correlator 12b, and the CL is input to the correlator 12c. A differential CL code signal is input from the code generator 10b. Other configurations are the same as those of the carrier phase error calculation unit 1 shown in FIG.

  Based on the code enable signal input from the code NCO 7, the CM code generator 10a differentiates the normal timing CM code signal CMp (CM (t) shown in FIG. 15) and the normal timing CM code signal CMp. CM code signal CMel is generated, CM code signal CMp at the normal timing is output to correlator 12a, and differential CM code signal CMel is output to correlator 12b. Further, the CL code generator 10b generates a differential CL code signal Clel obtained by differentiating the CL code signal at the normal timing based on the code enable signal input from the code NCO 7, and outputs the differential CL code signal Crel to the correlator 12c. Here, the differential CM code signal and the differential CL code signal are each formed by a difference signal because the code phase error calculation unit 5 performs correlation processing with a digital signal.

  The phase rotator 11 receives the carrier phase locked by the carrier phase tracking process from the carrier NCO 2, and the phase rotator 11 outputs a baseband I signal (and Q signal) based on this carrier phase. That is, the code phase tracking described below is processing in a state where the carrier phase is locked (coherent).

  The mixer 121a of the correlator 12a mixes the I signal input from the phase rotator 11 and the CM code signal CMp of the correct timing output from the CM code generator 10a, and the CM code in-phase signal is integrated into the accumulator 122a. Output to. The accumulator 122 a performs correlation processing by accumulating the input CM code in-phase signal according to the period based on the sampling clock, and outputs the CM code in-phase correlation signal to the signal conversion circuit 15.

  The mixer 121b of the correlator 12b mixes the I signal input from the phase rotator 11 and the differentiated CM code signal CMel output from the CM code generator 10a, and outputs the differentiated CM code in-phase signal to the accumulator 122b. To do. The accumulator 122b performs correlation processing by accumulating the input differential CM code in-phase signal according to the period based on the sampling clock, and outputs the differential CM code in-phase correlation signal to the multiplier / adder 14.

The mixer 121c of the correlator 12c mixes the I signal input from the phase rotator 11 and the differential CL code signal CLel output from the CL code generator 10b, and outputs the differential CL code in-phase signal to the accumulator 122c. To do. The accumulator 122c performs correlation processing by accumulating the input differential CL code in-phase signal according to the period based on the sampling clock, and outputs the differential CL code in-phase correlation signal to the multiplier / adder 14.
The signal conversion circuit 15 includes a sigmoid function calculator 150.

  The mixer 141 of the multiplier / adder 14 mixes (multiplies) the signal input from the signal conversion circuit 15 and the differential CM code in-phase correlation signal input from the correlator 12 b and outputs the mixed signal to the adder 142. The adder 142 adds the CM code correlation signal input from the mixer 141 and the differential CL code in-phase correlation signal input from the correlator 12c and outputs the result.

  By using the code phase error calculation unit 5 having such a configuration, the code phase error can be estimated and calculated by integrating the CM code and the CL code.

  The code phase error calculation unit 5, the code NCO 7, the CM code generator 10a, the CL code generator 10b, and the code loop filter 6 form a loop circuit to integrate the CM code and the CL code. Thus, the code phase error can be tracked by estimating and calculating the code phase error continuously and coherently. That is, the pseudorange can be continuously observed coherently.

  When performing code phase tracking of an L2C signal in this way, the code phase tracking method shown in the second embodiment is applied to the CM code modulated by the navigation message, and the calculation shown in [Equation 1] is performed. What is necessary is just to obtain | require the value of I component and Q component. That is, the Σ operation of [Equation 1] is applied at the position indicated by [1] in FIG.

  The code phase Δτ is obtained by the following equation so as not to be affected by bit inversion when tracking the pseudo noise code signal of the L2C signal shown in FIG.

Here, P _IM is the mean value of an integration interval 5ms for CM code signal CMp the normal timing, (E-L) _IM is for differential CM code signal CMel obtained by differentiating the CM code signal CMp regular timing It is an average value in an integration interval of 5 ms. (E−L) _IL is an average value in an integration section of 5 ms for the differential CL code signal CLel obtained by differentiating the CL code signal CLp at the normal timing. sign (P _IM) is the sign of the P _IM (if positive "1", it is negative "-1"). A is the carrier amplitude.

It is a figure which shows the structure of the conventional general carrier tracking loop. It is a figure which shows the structure of the Costas error detector used conventionally. It is a figure which shows the example of the bit inversion timing of I component data and a navigation message, and a period. It is a block diagram which shows the structure of the principal part of the GPS receiver which concerns on 1st Embodiment. It is a block diagram which shows the correction process of the integrated value accompanying the bit inversion of the navigation message performed inside the phase error detector in the GPS receiver. It is a figure which shows the relationship between a bit inversion timing and an integration area. It is a block diagram which shows the structure of the loop regarding the carrier phase tracking of the GPS receiver. It is a flowchart which shows the process sequence for detecting bit inversion timing. It is a figure which shows the example of a movement of the integration start timing for detecting bit inversion timing. It is a figure which shows the relationship between integration start timing and power. It is a figure which shows the relationship between a bit inversion timing and an integration area. It is a block diagram which shows the structure of the carrier phase tracking circuit of a L2C signal tracking apparatus. It is a block diagram which shows the structure of the code phase tracking circuit of a L2C signal tracking apparatus. It is a conceptual diagram which shows the code structure of a L2C signal. It is a wave form diagram which shows the relationship between CL code and CL (t), and the relationship between CM code and CM (t). It is a figure which shows the relationship etc. of a bit inversion timing, an integration area, and a processing timing.

Explanation of symbols

21-carrier NCO (carrier signal generating means)
37-code NCO (pseudo noise code signal generating means)
34-multiplier 35-accumulator 32-IQ separation circuit 33-carrier removal circuit

Claims (2)

Carrier signal generating means for generating a carrier signal;
A carrier signal that is binary phase modulated by a bit string of superimposition data is input, the carrier component of the input signal is removed based on the carrier signal by the carrier signal generation means, and the I component of the signal from which the carrier component has been removed And means for obtaining the Q component;
Means for obtaining an integrated value of a predetermined integration section of the amplitude of the I component and the Q component;
For said I and Q components, wherein as the accumulated value of the predetermined integrated time section, and the obtained integrated value as there is a bit inversion by the phase modulation in the predetermined integrating period, within the predetermined integrating period of the product next instruction and obtained as there is no bit reversal, and means for employing the integrated value of the larger value as the total effective value of the predetermined integrating period,
For the I component and Q component, the tracking error of the carrier phase is obtained based on the value obtained by integrating the effective integration value of the predetermined integration section over the time of one bit or more of the superimposed data, and the tracking error is reduced. Means for controlling the phase of the carrier signal generated by the carrier signal generating means in the direction;
A carrier phase tracking device. A pseudo noise code signal generating means for generating a pseudo noise code signal;
Means for inputting a pseudo-noise code signal binary-phase-modulated by a bit string of superimposition data and obtaining a correlation value between the pseudo-noise code signal and the pseudo-noise code signal by the pseudo-noise code signal generating means;
Means for obtaining an integrated value for a predetermined integrated section of the correlation value;
And the integrated value before Symbol predetermined integrating period fraction, determined said predetermined and the obtained integrated value as there is a bit inversion by the phase modulation in the constant integration interval, as there is no bit reversal in the predetermined integrating period among the product next instruction and was, it means for employing an integrated value of the larger value as the total effective value of the predetermined integrating period,
A tracking phase error of the pseudo noise code signal is obtained based on a value obtained by integrating the effective integration value of the predetermined integration section over a time corresponding to one bit or more of the superimposition data, and the pseudo noise is reduced in the direction in which the tracking phase error decreases. Means for controlling the phase of the pseudo-noise code signal generated by the code signal generating means;
A pseudo-noise code signal tracking device comprising:

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