JP4617861B2 - Liquid crystal display device - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which a display region that displays light transmitted through a liquid crystal layer as an image and a non-display region that blocks light and does not display an image are formed.

  Liquid crystal display devices have advantages such as thinness, light weight, and low power consumption over CRT (Cathode Ray Tube), and are widely used in electronic devices such as personal computers, digital still cameras, and mobile phones. As a display method of such a liquid crystal display device, an active matrix method is known.

  An active matrix liquid crystal display device displays an image in a display area by selectively applying and driving a scanning signal and a data signal sequentially to pixels formed in a matrix in the display area.

  However, in an active matrix liquid crystal display device, the potential applied to the liquid crystal layer around the display region is not stabilized, and thus image quality may be deteriorated, for example, a spot is generated in the image.

  This is mainly due to the difference in parasitic capacitance generated between the pixel at the extreme end of the display area and the pixel at the other central part or the like. In other words, the pixel at the center or the like is surrounded by another pixel while the pixel at the extreme end of the display area is not surrounded by another pixel. The parasitic capacitance is different from the central portion, and the potential applied to the liquid crystal layer around the display area is not stabilized, so that the image quality is deteriorated.

In order to solve such a problem, a method of forming dummy pixels in a non-display area around the display area of the liquid crystal panel has been proposed (for example, see Patent Document 1).
Japanese Patent Application Laid-Open No. 2004-271587

  5, 6 and 7 are diagrams showing a liquid crystal panel 10a in which dummy pixels are formed in the liquid crystal display device 601a. Here, FIG. 5 is a cross-sectional view showing a configuration of the liquid crystal panel 10a. FIG. 6 is a plan view showing the configuration of the liquid crystal panel 10a. FIG. 7 is a circuit diagram of the liquid crystal panel 10a.

  As shown in FIG. 5, the liquid crystal panel 10a includes an array substrate 11a, a counter substrate 21a, and a liquid crystal layer 31a. In the liquid crystal panel 10a, the array substrate 11a and the counter substrate 21a face each other so as to be spaced apart, and the periphery is bonded using a sealing material 51a so that the space is sandwiched between the array substrate 11a and the counter substrate 21a. A liquid crystal layer 31a is disposed on the surface. In the liquid crystal panel 10a, a display area D that displays light transmitted through the liquid crystal layer 31a as an image and a non-display area N that blocks light and displays no image are formed. The liquid crystal panel 10a transmits light from the array substrate 11a side to the counter substrate 21a side through the liquid crystal layer 31a, and displays an image in the display region D.

  Each part will be described.

  As shown in FIGS. 5, 6, and 7, the array substrate 11 a has a pixel electrode 101, a pixel switching element 102, a storage capacitor element 103, a scanning wiring 201, and a signal wiring 202 so as to correspond to the display area D. And the storage capacitor wiring 203 are formed. The dummy pixel electrode 151, the dummy pixel switching element 152, the dummy storage capacitor element 153, the dummy scanning wiring 401, the dummy signal wiring 402, the dummy storage capacitor wiring 403, and the storage capacitor connection wiring 404 are corresponding to the non-display area N. Are formed. Here, as shown in FIGS. 5 and 6, the dummy pixel electrode 151 is formed in the non-display area N along the periphery of the display area D in which the plurality of pixel electrodes 101 are formed. A storage capacitor connection wiring 404 connected to both the storage capacitor wiring 203 and the dummy storage capacitor wiring 403 is formed in the non-display region N along the periphery of the dummy pixel electrode 151. .

  On the other hand, as shown in FIGS. 5 and 6, a counter electrode 23a is formed on the counter substrate 21 so as to face the plurality of pixel electrodes 101 and the dummy pixel electrodes 151a with the liquid crystal layer 31a interposed therebetween.

  In the liquid crystal panel 10a, when displaying an image in the display region D, the gate driver 301 and the source drivers 302a and 302b supply the scanning signal and the data signal to the pixel switching element 102, respectively. A predetermined potential is applied to the pixel electrode 101. Along with this, a common potential common to each pixel is applied to the counter electrode 23a, and a voltage is applied to the liquid crystal layer 31a between the counter electrode 23a and the pixel electrode 101. Then, the CS driver 303 supplies a signal via the CS line 203 to hold a predetermined potential in the holding capacitor element 103 and keep the voltage applied to the liquid crystal layer 31a. By such an operation, the alignment direction of the liquid crystal layer 31a corresponding to the display area D is changed, so that light transmitted through the liquid crystal layer 31a is modulated, and an image is displayed in the display area D.

  In this image display, in addition to the above operation, the gate driver 301 supplies the scanning signal to the dummy pixel switching element 152 via the dummy scanning wirings 401a and 401b, and the CS driver 303 outputs the dummy signal. A predetermined potential is supplied to the dummy pixel switching element 152 via the wirings 402a and 402b, and the same potential as the potential applied to the counter electrode 23a is applied to the dummy pixel electrode 151. This eliminates a potential difference applied to the liquid crystal layer 31a between the counter electrode 23a and the dummy pixel electrode 151, thereby preventing a DC voltage from being applied to the liquid crystal layer 31a.

  As described above, in the liquid crystal panel 10a described above, by forming the dummy pixels, the parasitic capacitances in the pixels at the extreme end of the display area and the pixels at the other central part are the same. Thus, the image quality is improved by stabilizing the potential applied to the liquid crystal layer around the display area.

  Further, in the liquid crystal panel 10a described above, by eliminating the potential difference applied to the liquid crystal layer 31a between the counter electrode 23a and the dummy pixel electrode 151, it is possible to prevent a DC voltage from being applied to the liquid crystal layer 31a. Yes. The alignment direction of the liquid crystal layer 31a is stably controlled at the boundary between the display area D and the non-display area N to prevent defects such as burn-in and stains, and improve the image quality.

  However, since the dummy pixels are formed on the array substrate 11 in the non-display area N around the display area D as described above, the layout of wiring and circuits is limited, and the area of the non-display area N is reduced. Therefore, it has been difficult to downsize the apparatus.

  Therefore, the present invention realizes an improvement in image quality by preventing the occurrence of burn-in, stains, etc., and the liquid crystal display device that can reduce the area of the non-display area and can be easily downsized. It is to provide.

  In order to achieve the above object, a liquid crystal display device according to the present invention includes a first substrate, a second substrate that is spaced apart from the first substrate, and a space between the first substrate and the second substrate. A liquid crystal layer sandwiched between the liquid crystal layer, and a display region for displaying an image using light transmitted through the liquid crystal layer, and a non-display region for blocking light and displaying no image The first substrate may be provided along a plurality of pixel electrodes formed in a matrix so as to correspond to the display area and a periphery of the display area in which the plurality of pixel electrodes are formed. A conductive layer formed in the non-display region, and the second substrate includes a counter electrode formed to face the plurality of pixel electrodes and the conductive layer through the liquid crystal layer. When displaying an image in the display area, the counter electrode and the The voltage applied to the liquid crystal layer between the element electrode and the electric potential applied to the counter electrode so that the voltage applied to the liquid crystal layer between the counter electrode and the conductor layer is eliminated. The same potential is applied to the conductor layer.

  According to the present invention, an image quality can be improved by preventing the occurrence of burn-in, spots, etc., and the area of the non-display area can be reduced, and the liquid crystal display device can be easily downsized. Can be provided.

  Hereinafter, an example of an embodiment according to the present invention will be described.

  1, FIG. 2 and FIG. 3 are diagrams showing the liquid crystal panel 10 in the liquid crystal display device 601 of the present embodiment. Here, FIG. 1 is a cross-sectional view showing a configuration of the liquid crystal panel 10. FIG. 2 is a plan view showing the configuration of the liquid crystal panel 10. FIG. 3 is a circuit diagram of the liquid crystal panel 10.

  The liquid crystal display device 601 of this embodiment is an active matrix system, and the liquid crystal panel 10 in the liquid crystal display device 601 includes an array substrate 11, a counter substrate 21, and a liquid crystal layer 31, as shown in FIG.

  In the liquid crystal panel 10, the array substrate 11 and the counter substrate 21 face each other with a space therebetween, and the periphery is bonded by a sealing material 51. A liquid crystal layer 31 is disposed so as to be sandwiched between the array substrate 11 and the counter substrate 21. And in the liquid crystal panel 10, the display area D which displays the light which permeate | transmitted the liquid crystal layer 31 as an image, and the non-display area N which light-shields and does not display an image are formed. The liquid crystal panel 10 is, for example, a combined type in which a transmission type and a reflection type are used together. For example, light from the outside such as sunlight or light from an illumination unit such as a backlight (not shown) passes through the liquid crystal layer 31. The image is displayed in the display area D by the light transmitted through the liquid crystal layer 31 from the array substrate 11 side to the counter substrate 21 side.

  Each part of the liquid crystal panel 10 will be described.

  The array substrate 11 is, for example, an insulating substrate that transmits light, and is made of quartz. As shown in FIGS. 1, 2, and 3, the array substrate 11 includes a pixel electrode 111, a pixel switching element 112, a storage capacitor element 113, a scanning wiring 211, a signal wiring 212, and a storage capacitor wiring 213. Are formed so as to correspond to the display area D. A dummy scanning wiring 411, a storage capacitor connection wiring 414, and a dummy wiring electrode 501 are formed so as to correspond to the non-display area N. Details of each part will be described later.

  Similar to the array substrate 11, the counter substrate 21 is, for example, an insulating substrate that transmits light and is made of quartz. As shown in FIGS. 1 and 2, a counter electrode 23 is formed on the counter substrate 21 so as to face the plurality of pixel electrodes 111 and the dummy wiring electrodes 501 through the liquid crystal layer 31. . The counter electrode 23 is integrally formed on the entire surface of the counter substrate 21 facing the plurality of pixel electrodes 111 and the dummy wiring electrodes 501 using, for example, ITO (Indium Tin Oxide). The counter electrode 23 is connected to a common potential application unit (not shown), and a common potential Vcom is applied from the common potential application unit.

  The liquid crystal layer 31 is disposed so as to be sandwiched between the pixel electrode 111 of the array substrate 11 and the counter electrode 23 of the counter substrate 21. The liquid crystal layer 31 is, for example, a twisted nematic type, and is aligned by alignment films (not shown) formed on the array substrate 11 and the counter substrate 21, respectively. The liquid crystal layer 31 changes its alignment state based on the voltage applied by the pixel electrode 111 and the counter electrode 23, changes its optical characteristics, and controls light to display an image.

  Each part formed in the array substrate 11 will be described sequentially.

  A plurality of pixel electrodes 111 are formed on the array substrate 11 in a matrix so as to correspond to the display region D. Specifically, the pixel electrodes 111 are formed at intervals so that a plurality of pixel electrodes 111 are arranged in a row direction x and a column direction y orthogonal to the row direction x. The pixel electrode 111 is formed using, for example, ITO and transmits light. As shown in FIG. 2, the pixel electrodes 111 are m in the row direction x and in the column direction so as to correspond to the regions separated by the scanning wirings 211 and the signal wirings 212 formed to cross each other. n is formed for each y. As shown in FIG. 3, the pixel switching elements 112 are formed so as to correspond to the plurality of pixel electrodes 111 and are connected to the drain electrodes of the thin film transistors (TFTs) that are the pixel switching elements 112. The pixel electrode 111 applies a potential based on the data signal supplied from the signal wiring 212 to the liquid crystal layer 31 through the pixel switching element 112 that is turned on by the supply of the scanning signal.

  As shown in FIG. 3, a plurality of pixel switching elements 112 are formed in the display area D of the array substrate 11 in a matrix so as to correspond to each of the plurality of pixel electrodes 111, and the pixel electrodes 111 are subjected to switching control. To do. The pixel switching element 112 is, for example, a bottom-gate TFT whose channel region is formed of a polycrystalline silicon semiconductor, and is formed in m pieces in the row direction x and n pieces in the column direction y. The pixel switching element 112 has a gate electrode connected to the scanning wiring 211, and a driving operation is controlled by a scanning signal input from the gate driver 311 to the gate electrode via the scanning wiring 211. The pixel switching element 112 has a source electrode connected to the signal wiring 212, and a data signal is supplied from the source driver 312 to the pixel switching element 112 via the signal wiring 212. Further, the pixel switching element 112 has a drain electrode connected to the pixel electrode 111 and applies a data signal received from the source electrode to the pixel electrode 111 when the gate is on.

  As shown in FIG. 3, the storage capacitor element 113 is formed in a matrix in the display region D so as to correspond to each of the plurality of pixel electrodes 111, and holds the potential applied to the pixel electrode 111. . Specifically, a plurality of storage capacitor elements 113 are formed, m in the row direction x and n in the column direction y. The storage capacitor element 113 is configured to sandwich a dielectric film (not shown) between a first electrode (not shown) and a second electrode (not shown). The storage capacitor element 113 has one electrode connected to the drain electrode of the pixel switching element 112 and the other electrode connected to the storage capacitor wiring 213. The storage capacitor element 113 is formed in parallel with the electrostatic capacitance of the liquid crystal layer 31, and holds charge due to a data signal applied to the liquid crystal layer 31.

  As shown in FIG. 3, the scanning wiring 211 extends in the row direction x along the plurality of pixel switching elements 112 arranged in the row direction x in the plurality of pixel switching elements 112. Is formed. Each of the plurality of scanning wirings 211 is connected to each of the pixel switching elements 112 arranged in the row direction x, and supplies a scanning signal to the pixel switching elements 112 arranged in the row direction x. Further, as shown in FIG. 2, each of the plurality of scanning wirings 211 is formed so as to be arranged at intervals from one end to the other end in the column direction y of the display region D. Here, as shown in FIG. 3, the plurality of scanning wirings 211 are formed side by side in the column direction y so as to have an equal interval. Specifically, n scanning wirings 211 are formed so as to correspond to n pixel electrodes 111 arranged in the column direction y. The first scanning wiring 211a, the second scanning wiring 211b,. -1 scan wiring 211n-1 and the nth scan wiring. Each of the plurality of scanning wirings 211 is connected to the gate driver 311, and supplies a scanning signal from the gate driver 311 to the pixel switching element 112 so as to sequentially select the rows of the pixel electrodes 111. That is, the pixel electrodes 111 arranged from one end to the other end in the column direction y are sequentially selected from the one end to the other end, and scanning signals are sequentially supplied to the pixel switching elements 112 arranged in the row direction x. . For example, the first scanning wiring 211a in the first row supplies a scanning signal to each of the pixel switching elements 112 in the first row to which the first scanning wiring 211a itself is connected, and the pixel switching elements 112 are supplied with pixels. The switching is controlled. Here, from one end in the column direction y of the display region D, the first scanning line 211a, the second scanning line 211b,..., The n-1th scanning line 211n-1, the nth scanning line in this order. Scan signals are sequentially supplied to the other end.

  As shown in FIG. 3, the signal wiring 212 extends along the plurality of pixel switching elements 112 arranged in the column direction y in the plurality of pixel switching elements 112, and a plurality of signal lines 212 are formed in the display region D. . The signal wiring 212 is connected to each of the plurality of pixel switching elements 112 arranged in the column direction y, and supplies a data signal to the pixel electrode 111 via the plurality of pixel switching elements 112 arranged in the column direction y. Then, m signal lines 212 are formed side by side in the row direction x so as to correspond to the m pixel switching elements 112 arranged in the row direction x. Specifically, as shown in FIG. 3, the signal wiring 212 includes a first signal wiring 212a, a second signal wiring 212b,..., An m−1th signal wiring 212m−1 and an mth signal wiring 212m. Each signal wiring 212 supplies a data signal to the pixel electrode 111 via the pixel switching element 112 to which the scanning signal is supplied.

  As shown in FIG. 3, the storage capacitor line 213 extends along the plurality of pixel electrodes 111 arranged in the row direction x in the plurality of pixel electrodes 111, and a plurality of storage capacitor lines 213 are formed in the display region D. Each of the plurality of storage capacitor wirings 213 is connected to each of the pixel electrodes 111 arranged in the row direction x. Further, n storage capacitor lines 213 are provided so as to correspond to n storage capacitor elements 113 arranged in the column direction y, and each of them is formed side by side in the column direction y with an interval. Specifically, as shown in FIG. 3, the storage capacitor line 213 includes a first storage capacitor line 213a, a second storage capacitor line 213b,..., An (n-1) storage capacitor line 213n-1, an nth storage capacitor. A wiring 213n is included. Each storage capacitor line 213 is connected to the CS driver 313 via the storage capacitor connection line 414. Based on the signal from the CS driver 313, the storage capacitor element 113 stores charges, and the row direction The potential difference between the pixel electrode 111 and the counter electrode 23 arranged in x is held.

  As shown in FIG. 2, the dummy scanning wiring 411 extends in the row direction x along the nth scanning wiring 211 n located at the other end in the column direction y of the display region D in the plurality of scanning wirings 211. The non-display area N is formed. The dummy scanning wiring 411 is supplied with a scanning signal sequentially supplied to each of the plurality of scanning wirings 411 next to the nth scanning wiring 211n.

  The dummy scanning wiring 411 includes a first parasitic capacitance C1 generated in the pixel switching element 112 and the pixel electrode 111 connected to the nth scanning wiring 211n in the plurality of pixel switching elements 112 and the plurality of pixel electrodes 111. It is arranged in the non-display area N so as to be the same as the second parasitic capacitance C2 generated in the pixel switching element 112 and the pixel electrode 111 connected to the scanning wiring 211 other than the nth scanning wiring 211n. Among the plurality of pixel switching elements 112 and the plurality of pixel electrodes 111, each of the pixel switching element 112 and the pixel electrode 111 connected to the nth scanning wiring 211n, the nth scanning wiring 211n, and the dummy scanning wiring 411 A first parasitic capacitance C1 is generated between them. On the other hand, for example, each of the pixel switching element 112 and the pixel electrode 111 connected to the n-1th scanning wiring 211n-1 other than the nth scanning wiring 211n, and the pixel switching element and the pixel electrode are connected to the nth- Between each of the (n-2) th scanning wiring 211n-2 and the (n-1) th scanning wiring 211n-1 formed so as to be sandwiched between the first scanning wiring 211n-1, a second parasitic capacitance C2 is present. appear. For this reason, the dummy scanning wiring 411 is formed side by side in the column direction y so that the plurality of scanning wirings 211 are equally spaced from each other so that the first parasitic capacitance C2 and the second parasitic capacitance C2 are substantially the same. Similarly, the non-display area D is formed so that the same interval as the plurality of scan lines 211 is separated from the n-th scan line 211n.

  As shown in FIG. 2, the storage capacitor connection wiring 414 is integrally formed in a strip shape in the non-display area N along the periphery of the display area D. The storage capacitor connection wiring 414 is connected to the plurality of storage capacitor wirings 213 and is connected to the storage capacitor element 113 via the storage capacitor wiring 213.

  FIG. 4 is an enlarged cross-sectional view showing a portion where the storage capacitor connection wiring 414 is formed.

  As shown in FIG. 4, the storage capacitor connection wiring 414 is formed in the non-display region D so as to face the dummy wiring electrode 501 with the interlayer insulating layer 13 interposed therebetween. Here, the storage capacitor connection wiring 414 is formed so as to be sandwiched between the dummy wiring electrode 501 and the array substrate 11.

  The dummy wiring electrode 501 is formed in the non-display area N along the periphery of the display area D where the plurality of pixel electrodes 111 are formed, like the storage capacitor connection wiring 414. The dummy wiring electrode 501 is integrally formed so as to surround the display area D in a strip shape. Here, the dummy wiring electrode 501 is formed using ITO which is the same conductive material as the pixel electrode 111. The dummy wiring electrode 501 is formed along the periphery of the display region D so as to have a width equal to or smaller than the width of the pixel electrode 111 formed along the periphery of the display region D. For example, the dummy wiring electrode 501 is formed with a width of 40 μm.

  Specifically, as shown in FIG. 2, the dummy wiring electrode 501 extends in the column direction y so as to be parallel to each other in close proximity to each of the first signal wiring 212a and the nth signal wiring 212n. It is formed in the non-display area N in a band shape. Here, each of the first signal wiring 212a and the nth signal wiring 212n has the same width as the width extending in the column direction y, and the dummy wiring electrode 501 extends in the column direction y. Along with this, the non-display region N is formed in a strip shape so as to extend in the row direction x alongside and parallel to the first scanning line 211a and the nth scanning line 211n. Here, each of the first scanning wiring 211a and the n-th scanning wiring 211n has the same width as the width extending in the row direction x, and the dummy wiring electrode 501 extends in the row direction x. That is, the dummy wiring electrode 501 is provided so as to form a rectangle with a width corresponding to the size of the pixel electrode 111 and surrounding the border of the rectangular display region D in a strip shape. When an image is displayed in the display area D, the counter electrode is generated by the scanning signal from the gate driver 311, the data signal from the source drivers 312 a and 312 b, and the common potential Vcom applied by the common potential applying unit. The voltage applied to the liquid crystal layer 23 between the pixel electrode 111 and the pixel electrode 111 is controlled, but the dummy electrode 501 does not have the voltage applied to the liquid crystal layer 23 between the counter electrode 23 and the counter electrode. The same potential as the common potential Vcom applied to 23 is applied. In the present embodiment, the dummy wiring electrode 501 is connected to the common potential application unit similarly to the counter electrode 23, and the common potential Vcom is applied by the common potential application unit.

  In addition, in the liquid crystal display device 601 of this embodiment, polarizing plates (not shown) are provided on both surfaces of the liquid crystal panel 10. Further, a backlight (not shown) is provided on the opposite side of the array substrate 11 from the side where the liquid crystal layer 31 is disposed via a polarizing plate.

In the present embodiment, the array substrate 11 corresponds to the first substrate of the present invention. Further, the counter substrate 21 of the present embodiment corresponds to a second substrate of the present invention. Further, the counter electrode 23 of the present embodiment corresponds to the counter electrode of the present invention. Further, the liquid crystal layer 31 of the present embodiment corresponds to the liquid crystal layer of the present invention. Further, the pixel electrode 111 of this embodiment corresponds to the pixel electrode of the present invention. Further, the pixel switching element 112 of the present embodiment corresponds to the pixel switching element of the present invention. Further, the storage capacitor element 113 of this embodiment corresponds to the storage capacitor element of the present invention. Further, the scanning wiring 211 of this embodiment corresponds to the scanning wiring of the present invention. Further, the signal wiring 212 of this embodiment corresponds to the signal wiring of the present invention. In addition, the nth scanning wiring 211n of the present embodiment corresponds to the first scanning wiring of the present invention. Further, the dummy scanning wiring 411 of this embodiment corresponds to the dummy scanning wiring of the present invention. Further, the storage capacitor connection wiring 414 of the present embodiment corresponds to the storage capacitor connection wiring of the present invention. Further, the dummy wiring electrode 501 of the present embodiment corresponds to a conductor layer of the present invention. Further, the liquid crystal display device 601 of the present embodiment corresponds to the liquid crystal display device of the present invention. Further, the display area D of the present embodiment corresponds to the display area of the present invention. Further, the non-display area N of the present embodiment corresponds to the non-display area of the present invention. Further, the first parasitic capacitance C1 of the present embodiment corresponds to the first parasitic capacitance of the present invention. The second parasitic capacitance C2 of the present embodiment corresponds to the second parasitic capacitance of the present invention.

  An operation when driving the liquid crystal display device 601 will be described.

  When driving the liquid crystal display device 601, the gate driver 311 supplies a scanning signal to the pixel switching element 112 via the scanning wiring 211, and the source drivers 312 a and 312 b receive the data signal via the signal wiring 212. The pixel switching element 112 is supplied. At this time, the common potential applying unit applies the common potential Vcom to the counter electrode 23 to generate a potential difference in the liquid crystal layer 23 between the counter electrode 23 and the pixel electrode 111. As a result, the optical characteristics of the liquid crystal layer 31 change, and an image is displayed.

  Specifically, the gate driver 311 supplies the scanning signals to the plurality of scanning wirings 211 arranged in the column direction y by time-dividing and sequentially scanning the pixel switching element 112. Here, the scanning electrodes are sequentially supplied to the scanning wirings 211 arranged in the column direction so that the pixel electrodes 111 arranged from one end to the other end in the column direction y are sequentially selected from the one end to the other end. . For example, from the one end to the other end in the column direction y of the display region D, as in the order of the first scan line 211a, the second scan line 211b,..., The (n-1) th scan line 211n-1, and the nth scan line. The scanning signal is sequentially supplied. Further, here, a scanning signal is supplied to the dummy scanning wiring 411 after the nth scanning wiring.

  In synchronization with the supply timing of the scanning signal, the source driver 312 supplies the data signal to the signal wiring 202 and applies the data signal to the pixel electrode 111 through the pixel switching element 112 in the on state. As a result, a potential difference is generated in the liquid crystal layer 23 between the counter electrode 23 and the pixel electrode 111. That is, a voltage is applied to the liquid crystal layer 31. As a result, the alignment direction of the liquid crystal layer 31 is changed, the optical characteristics such as light transmittance are changed, and an image is displayed.

  As described above, when an image is displayed in the display area D, the scanning signal from the gate driver 311, the data signal from the source drivers 312 a and 312 b, and the common potential Vcom applied by the common potential application unit, The voltage applied to the liquid crystal layer 23 between the counter electrode 23 and the pixel electrode 111 is controlled.

  On the other hand, when displaying an image in the display area D, the same potential as the common potential Vcom applied to the counter electrode 23 is applied to the dummy wiring electrode 501, and the gap between the dummy wiring electrode 501 and the counter electrode 23 is applied. The potential difference applied to the liquid crystal layer 23 is eliminated. Here, the common potential applying unit applies a common potential similar to that of the counter electrode 23 to the dummy wiring electrode 501.

  As described above, in the present embodiment, the dummy wiring electrode 501 is formed in the non-display area N along the periphery of the display area D where the plurality of pixel electrodes 111 are formed. When an image is displayed in the display area D, the voltage applied to the liquid crystal layer 31 between the counter electrode 23 and the pixel electrode 111 is controlled, and the same potential as the potential applied to the counter electrode 23 is set as a dummy. The potential difference applied to the liquid crystal layer 31 between the counter electrode 23 and the dummy wiring electrode 501 is eliminated by being applied to the wiring electrode 501. In this way, the present embodiment prevents a DC voltage from being applied to the liquid crystal layer 31 and stabilizes the alignment direction of the liquid crystal layer 31 at the boundary between the display region D and the non-display region N. For this reason, it is possible to prevent the occurrence of defects such as burn-in and stains at the time of image display, and to improve the image quality. Further, since the dummy wiring electrode 501 prevents the application of a DC voltage to the liquid crystal layer 31 without forming a dummy switching element or the like for driving the dummy pixel as described above, wiring, a driving circuit, etc. Since the degree of freedom in layout increases, the area occupied by the non-display area can be reduced, and the apparatus can be easily downsized. In addition, since the configuration is simplified, it can be easily manufactured and the manufacturing efficiency can be improved.

  In this embodiment, the dummy wiring electrode 501 is made of the same conductive material as that of the pixel electrode 111. For this reason, since the dummy wiring electrode 501 and the pixel electrode 111 can be formed in the same process, manufacturing efficiency can be improved.

  Further, in the present embodiment, the dummy wiring electrode 501 is formed along the periphery of the display region D so as to have a width equal to or smaller than the width of the pixel electrode 111 formed along the periphery of the display region D. Yes. For this reason, it is possible to adjust the parasitic capacitance generated in the pixel at the extreme end of the display area D and the other pixel at the center to be the same, and problems such as burn-in and stain occur at the time of image display. Can be prevented and the image quality can be improved.

  In the present embodiment, the storage capacitor connection wiring 414 is formed in the non-display region D so as to face the dummy wiring electrode 501 with the interlayer insulating film 13 interposed therebetween. For this reason, this embodiment can reduce the area occupied by the non-display region, and can easily reduce the size of the apparatus. In addition, the parasitic capacitance between the storage capacitor connection wiring 414 and the dummy wiring electrode 501 causes the parasitic capacitance generated in the pixel at the extreme end of the display area to be the same as the pixel at the other central portion or the like. Therefore, it is possible to prevent the occurrence of defects such as burn-in and stains at the time of image display, and to improve the image quality.

  Further, in the present embodiment, the dummy scanning wiring 411 extends in the row direction x along the nth scanning wiring 211n located at the other end in the column direction y of the display region D in the plurality of scanning wirings 211. Is formed in the non-display area N. The pixel electrodes 111 arranged from one end to the other end in the column direction y of the display region D are sequentially supplied to the plurality of scanning wirings 211 so as to be sequentially selected from the one end to the other end. The scanning signals sequentially supplied to the plurality of scanning wirings are supplied to the dummy scanning wiring 411 next to the nth scanning wiring 211n. Here, the dummy scanning wiring 411 has a first parasitic capacitance C1 generated in the pixel switching element 112 and the pixel electrode 111 connected to the nth scanning wiring 211n, for example, the nth scanning wiring 211n. -1 is formed in the non-display region D so as to be the same as the second parasitic capacitance C2 generated in the pixel switching element 112 and the pixel electrode 111 connected to the scanning wiring 211n-1. For this reason, the dummy scanning wiring 411 can be adjusted so that the parasitic capacitance generated in the pixel at the extreme end of the display area and the pixel at the other central part is the same. It is possible to prevent the occurrence of problems such as and improve the image quality.

  In implementing the present invention, the present invention is not limited to the above-described embodiment, and various modifications can be employed.

FIG. 1 is a cross-sectional view showing a configuration of a liquid crystal panel in a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a plan view showing the configuration of the liquid crystal panel in the liquid crystal display device according to the embodiment of the present invention. FIG. 3 is a circuit diagram of a liquid crystal panel in the liquid crystal display device according to the embodiment of the present invention. FIG. 4 is an enlarged cross-sectional view showing a portion where the storage capacitor connection wiring is formed in the liquid crystal display device according to the embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a configuration of an active matrix liquid crystal panel. FIG. 6 is a plan view showing a configuration of an active matrix liquid crystal panel. FIG. 7 is a circuit diagram of an active matrix liquid crystal panel.

Explanation of symbols

10: Liquid crystal panel 11: Array substrate (first substrate)
21: Counter substrate (second substrate)
23: Counter electrode (counter electrode)
31: Liquid crystal layer (liquid crystal layer)
111: Pixel electrode (pixel electrode),
112: Pixel switching element (pixel switching element),
113: Retention capacitive element (retention capacitive element),
211: Scanning wiring (scanning wiring)
212: signal wiring (signal wiring),
213: Retention capacitance wiring 411: Dummy scanning wiring (dummy scanning wiring)
414: Retention capacitance connection wiring (retention capacitance connection wiring),
501: Dummy wiring electrode (conductor layer)
601: Liquid crystal display device (liquid crystal display device)
D: Display area (display area)
N: non-display area (non-display area)
C1: first parasitic capacitance (first parasitic capacitance))
C2: second parasitic capacitance second parasitic capacitance)

Claims (5)

A first substrate; a second substrate disposed at a distance from the first substrate; and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the liquid crystal layer A liquid crystal display device in which a display region that displays an image using light transmitted through the light source and a non-display region that blocks light and does not display an image are formed,
The first substrate is
A plurality of pixel electrodes formed in a matrix so as to correspond to the display region;
A conductor layer formed in the non-display area so as to extend around the display area in which the plurality of pixel electrodes are formed;
A plurality of storage capacitor elements that are formed in the display region in a matrix so as to be connected to each of the plurality of pixel electrodes, and that hold a potential applied to the pixel electrodes;
A storage capacitor connection wiring connected to the plurality of storage capacitor elements ,
The second substrate is
A counter electrode formed to face the plurality of pixel electrodes and the conductor layer via the liquid crystal layer,
The storage capacitor connection wiring is formed in the non-display region so as to face the conductor layer through an insulating layer,
When displaying an image in the display region, the voltage applied to the liquid crystal layer between the counter electrode and the pixel electrode is controlled, and the same potential as the potential applied to the counter electrode is controlled by the conductor. Liquid crystal display device applied to the layer. The liquid crystal display device according to claim 1, wherein the conductor layer is formed of the same conductive material as that of the pixel electrode. The liquid crystal according to claim 2 , wherein the conductor layer is formed along the periphery of the display region so as to have a width equal to or smaller than the width of the pixel electrode formed along the periphery of the display region. Display device. The first substrate is
A plurality of pixel switching elements that are formed in the display region in a matrix so as to correspond to each of the plurality of pixel electrodes, and that perform switching control of the pixel electrodes;
The plurality of pixel switching elements are formed in the display region so as to extend along a plurality of pixel switching elements arranged in a row direction, and connected to each of the plurality of pixel switching elements arranged in the row direction, A plurality of scanning lines for supplying a scanning signal to a plurality of pixel switching elements arranged in a row direction;
The plurality of pixel switching elements are formed in the display region so as to extend along the plurality of pixel switching elements arranged in the column direction, and connected to each of the plurality of pixel switching elements arranged in the column direction, A plurality of signal lines for supplying data signals to the pixel electrodes via a plurality of pixel switching elements arranged in a column direction;
Have
The plurality of scanning lines are formed so as to be arranged at an interval from one end to the other end in the column direction, and the pixel electrodes arranged from the one end to the other end are arranged from the one end to the other. Supplying the scanning signal to sequentially select the end,
The plurality of signal wirings are formed so as to be arranged at intervals in the row direction,
Furthermore, in the non-display area of the first substrate,
A dummy scanning line is formed so as to extend in the row direction along a first scanning line located at the other end in the column direction of the display region in the plurality of scanning lines,
The liquid crystal display device according to claim 3 , wherein the scanning signal sequentially supplied to the plurality of scanning wirings is supplied to the dummy scanning wiring next to the first scanning wiring. The dummy scanning line has a first parasitic capacitance generated in the first pixel switching element and the first pixel electrode connected to the first scanning line in the plurality of pixel switching elements and the plurality of pixel electrodes, The same as the second parasitic capacitance generated in the second pixel switching element and the second pixel electrode connected to the second scanning wiring other than the first scanning wiring in the plurality of pixel switching elements and the plurality of pixel electrodes. The liquid crystal display device according to claim 4 , wherein the liquid crystal display device is formed in the non-display area.

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