JP4604239B2 - Meander line type Josephson junction array - Google Patents
Meander line type Josephson junction array Download PDFInfo
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- JP4604239B2 JP4604239B2 JP2004316047A JP2004316047A JP4604239B2 JP 4604239 B2 JP4604239 B2 JP 4604239B2 JP 2004316047 A JP2004316047 A JP 2004316047A JP 2004316047 A JP2004316047 A JP 2004316047A JP 4604239 B2 JP4604239 B2 JP 4604239B2
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- josephson junction
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Description
本願発明は、バイアス電流とマイクロ波の印加により一定電圧を発生するジョセフソン接合の多数個を直列接続したジョセフソン接合アレーで構成される電圧標準装置に関する。 The present invention relates to a voltage standard device composed of a Josephson junction array in which a large number of Josephson junctions that generate a constant voltage by applying a bias current and a microwave are connected in series.
ジョセフソン電圧標準装置は、周波数を正確に電圧に変換できる交流ジョセフソン効果という物理法則に基づいている。シリコンなどを材料とするチップ上のジョセフソン接合にマイクロ波を供給するためにはマイクロ波伝送線路が用いられる。マイクロ波伝送線路としては、準平面型導波路(Coplanar Waveguide: CPW) が利用されてきた(下記非特許文献1参照)。
The Josephson voltage standard is based on the physical law of AC Josephson effect that can accurately convert frequency to voltage. A microwave transmission line is used to supply microwaves to a Josephson junction on a chip made of silicon or the like. As a microwave transmission line, a quasi-planar waveguide (CPW) has been used (see Non-Patent
図1には、誘電体基板1の一面に信号導体配線2と接地導体(外部導体)3が設けられた配線構造である準平面型導波路が示されている。信号配線が接地導体にはさまれた構造になっており、誘電体の一面のみを使って信号伝送ができるため、回路の特性評価や他の回路との接続が容易である。
FIG. 1 shows a quasi-planar waveguide having a wiring structure in which a signal conductor wiring 2 and a ground conductor (external conductor) 3 are provided on one surface of a
電圧標準で用いられるジョセフソン接合アレーは、超伝導体の下部電極4と常伝導体の中間層5と超伝導体の上部電極6から構成されるジョセフソン接合を多数個直列に接続したものである。
The Josephson junction array used in the voltage standard is a series of a large number of Josephson junctions composed of a superconductor
図2に示すように、すべての接合に均一にマイクロ波を印加するために、ジョセフソン接合7アレーも接合の両側に接地導体3を配置し、準平面型の伝送線路を形成したものも知られている(非特許文献2参照)。
ここで問題となるのは、大きな出力電圧を得ようとする場合、多くのジョセフソン接合を直列に接続する必要があり、ジョセフソン接合アレーが非常に長くなり、チップのサイズの大型化を招くことである。また、チップサイズが大きくなれば製造コストの増加を招いてしまう。 The problem here is that when a large output voltage is to be obtained, it is necessary to connect many Josephson junctions in series, and the Josephson junction array becomes very long, leading to an increase in chip size. That is. Further, if the chip size is increased, the manufacturing cost is increased.
ジョセフソン接合アレーをメアンダライン(蛇行)型にすることにより、同じ長さのアレーであれば2倍のジョセフソン接合を配置できる。ところが、メアンダライン型にすると、アレーのインダクタンスが増加するため、アレーの特性インピーダンスを例えば50オームに保とうとすると、アレーと外部導体とのキャパシタンスを大きくする必要があるため、アレーと接地導体の距離を非常に小さくする必要がある。しかし、アレーと外部導体のギャップを小さくすることは、パーティクルによる短絡故障を招きかねない。そこで、下部電極のみ幅を広げ、絶縁膜(誘電体膜)を介して接地導体とキャパシタンスを確保すれば、下部電極と接地導体は絶縁膜(誘電体膜)で絶縁されているため、アレーと接地導体の短絡故障の危険を減らすことができる。 By making the Josephson junction array into a meander line (meander) type, twice as many Josephson junctions can be arranged as long as the array has the same length. However, if the meander line type is used, the inductance of the array increases. Therefore, if the characteristic impedance of the array is kept at, for example, 50 ohms, it is necessary to increase the capacitance between the array and the external conductor. Need to be very small. However, reducing the gap between the array and the outer conductor can lead to short circuit failures due to particles. Therefore, if only the lower electrode is widened and the ground conductor and capacitance are secured via the insulating film (dielectric film), the lower electrode and the ground conductor are insulated by the insulating film (dielectric film). The risk of a short circuit failure of the ground conductor can be reduced.
ジョセフソン接合アレーをメアンダライン型にすることで2倍のジョセフソン接合を集積でき、アレーの下部電極とマイクロ波伝送線路の外部導体の間に絶縁膜をはさむことにより、アレーと外部導体が電気的に完全に絶縁されるため、ごみや不純物による絶縁性能の劣化または短絡故障の可能性が小さくなる。以上の効果は、チップサイズを小型化、またはチップサイズを大型化せずに大きな出力電圧を得ることが可能になり、作製の歩留まりを向上させ電圧標準チップの製造コストを下げるために有効である。 By making the Josephson junction array a meander-line type, double Josephson junctions can be integrated, and by sandwiching an insulating film between the lower electrode of the array and the outer conductor of the microwave transmission line, the array and the outer conductor are electrically connected. Therefore, the possibility of a deterioration in insulation performance or a short-circuit failure due to dust or impurities is reduced. The above effects are effective for reducing the chip size or obtaining a large output voltage without increasing the chip size, improving the production yield, and reducing the manufacturing cost of the voltage standard chip. .
以下に、発明を実施するための最良の形態を示す。 The best mode for carrying out the invention will be described below.
図3に示されるように、従来のジョセフソン接合アレーにおいては、下部電極4上に2個のジョセフソン接合7を配置し、上部電極6で2個のジョセフソン接合を接続し、両側に接地導体3を配置してアレーを形成している。
As shown in FIG. 3, in the conventional Josephson junction array, two Josephson
アレーのインダクタンスをL、アレーと接地導体3のキャパシタンスをCとすると、アレーの特性インピーダンスZはZ=√(L/C)で与えられる。特性インピーダンスは常に一定の値、典型的には50オームでなければならないので、アレーと接地導体の間隔を調節してインピーダンスをあわせる必要がある。
When the inductance of the array is L and the capacitance of the array and the
図4に示されるように、図3に示されるジョセフソン接合と同じ長さで、接合の数を2倍にするには、下部電極4と上部電極6をメアンダライン(蛇行)状にしてジョセフソン接合7を2列にすれば、2倍のジョセフソン接合が配置できる。アレーのインダクタンスLは大幅に増加するため、下部電極4の大きさを大きくし、接地導体3に近づける。
As shown in FIG. 4, in order to double the number of junctions with the same length as the Josephson junction shown in FIG. 3, the
図5は、図4のAA面における断面図であるが、下部電極4と接地導体3がゴミや不純物による短絡故障が起こらないように、下部電極4と接地導体3は絶縁膜8により絶縁する構成としている。作製を容易にするためには、上部電極6と接地導体3は同一レイヤーの導体膜を用いることもできる。
FIG. 5 is a cross-sectional view taken along the plane AA of FIG. It is configured. In order to facilitate the production, the
本願発明にかかるジョセフソン接合アレー構造体は、デジタル−アナログ変換機に用いることができる。また、該デジタル−アナログ変換機を用いて、プログラマブルジョセフソン電圧標準用接合アレーとすることができる。
さらに、該プログラマブルジョセフソン電圧標準用接合アレーをチップ状として、ジョセフソン電圧標準用チップとすることができ、該ジョセフソン電圧標準用チップを用いて、ジョセフソン電圧発生装置とすることができる。
The Josephson junction array structure according to the present invention can be used for a digital-analog converter. Moreover, it can be set as the programmable Josephson voltage standard junction array using this digital-analog converter.
Further, the programmable Josephson voltage standard junction array can be formed into a chip shape to form a Josephson voltage standard chip, and the Josephson voltage standard chip can be used as a Josephson voltage generator.
1:基板
2:信号配線導体
3:接地導体
4:下部電極
5:中間層
6:上部電極
7:ジョセフソン接合
8:絶縁膜
1: Board
2: Signal wiring conductor
3: Ground conductor
4: Bottom electrode
5: Middle layer
6: Upper electrode
7: Josephson junction
8: Insulating film
Claims (9)
上記ジョセフソン接合アレーは、メアンダライン形状に配置されており、かつ下部電極、中間層及び上部電極から構成され、
上記下部電極は絶縁膜を介して上記外部導体とキャパシタンスを有し、
上記ジョセフソン接合アレーのインダクタンスと上記キャパシタンスとで与えられる特性インピーダンスが一定であることを特徴とするジョセフソン接合アレー構造体。 A Josephson junction array structure in which a Josephson junction array on a substrate and a quasi-planar microwave transmission line in which outer conductors are arranged on both sides of the array are formed ,
The Josephson junction array is arranged in a meander line shape and includes a lower electrode, an intermediate layer, and an upper electrode.
The lower electrode has a capacitance with the outer conductor through an insulating film ,
A Josephson junction array structure characterized in that a characteristic impedance given by the inductance and the capacitance of the Josephson junction array is constant .
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JP2004316047A JP4604239B2 (en) | 2004-10-29 | 2004-10-29 | Meander line type Josephson junction array |
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JP4604239B2 true JP4604239B2 (en) | 2011-01-05 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03204982A (en) * | 1988-12-09 | 1991-09-06 | Canon Inc | Superconductive electromagnetic wave mixer and superconductive wave mixing device provided therewith |
JPH04207403A (en) * | 1990-11-30 | 1992-07-29 | Nippon Telegr & Teleph Corp <Ntt> | Superconducting device and production thereof |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH03204982A (en) * | 1988-12-09 | 1991-09-06 | Canon Inc | Superconductive electromagnetic wave mixer and superconductive wave mixing device provided therewith |
JPH04207403A (en) * | 1990-11-30 | 1992-07-29 | Nippon Telegr & Teleph Corp <Ntt> | Superconducting device and production thereof |
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