JP4683761B2 - Method for manufacturing semiconductor device - Google Patents

Description

【００１８】
図１（Ｂ）のような結果が得られるのは、下地絶縁膜が熱容量として働くことで温度勾配が発生するからである。図１（Ａ）のＢ領域は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷却する。逆にＣ領域は、Ｂ領域からＣ領域直下の下地絶縁膜に逃げてくる熱があるため、温度が下がりにくくなっている。したがって、Ｂ領域とＣ領域、または、Ｂ領域とＡ領域とでは温度勾配が生じる。温度勾配が生じることによって、温度の低いＢ領域から結晶成長が始まり、温度の高いＣ領域またはＡ領域へと固液界面が移動するので、大粒径の結晶粒を得ることができる。
【００１９】
つまり、従来のガラス基板上に作製されたＴＦＴで使われている構造、すなわちガラス基板上に下地絶縁膜を形成し、前記下地絶縁膜上に半導体膜を形成する構造と同じ構造であるが、特願平１１−３５１０６０号では下地絶縁膜に対して所望の位置にエッチングを行なって段差を設けている。このようなサンプルに対し、基板の表面側からレーザビームを照射すると、前記下地絶縁膜の段差の形状に対応して半導体膜内部に温度分布が発生し、ラテラル成長の発生場所、方向を制御することができる。
【００２０】
R. Ishihara氏らの方法により形成された半導体膜を活性層としてトップゲート型のＴＦＴを作製することは構造的には可能である。しかしながら、半導体膜と高融点金属膜との間に設けられた酸化珪素膜により寄生容量が発生するので、消費電力が増加し、ＴＦＴの高速動作を実現することは困難となる。一方、高融点金属膜をゲート電極とすることにより、ボトムゲート型または逆スタガ型のＴＦＴに対しては有効に適用でき得ると考えられる。しかし、基板上に酸化珪素膜を形成し、前記酸化珪素膜上に高融点金属膜を形成し、前記高融点金属膜上に非晶質珪素膜を形成する構造において、非晶質珪素膜の膜厚を除いて考えたとしても、高融点金属膜と酸化珪素膜の膜厚は、結晶化工程において適した膜厚と、ＴＦＴ素子としての電気的特性において適した膜厚とは必ずしも一致しないので、結晶化工程における最適設計と素子構造の最適設計とを両方同時に満足することができない。
【００２１】
また、透光性のない高融点金属膜をガラス基板の全面に形成すると、透過型の液晶表示装置を作製することは不可能になってしまう。高融点金属材料として使用されるクロム（Ｃｒ）膜やチタン（Ｔｉ）膜は内部応力が高いので、ガラス基板との密着性に問題が生じる可能性が高い。さらに、内部応力の影響はこの上層に形成する半導体膜へも及び、形成された結晶質半導体膜に歪みを与える力として作用する可能性が高い。
【００２２】
一方、ＴＦＴにおいて重要なパラメータである閾値電圧（以下、Ｖthと記す。）を所定の範囲内に制御するためには、チャネル形成領域の荷電子制御のほかに、活性層に密接して絶縁膜で形成する下地膜やゲート絶縁膜の荷電欠陥密度を低減させることや、その内部応力のバランスを考慮する必要がある。このような要求に対して、酸化珪素膜や酸化窒化珪素膜などの珪素を構成元素として含む材料が適していた。したがって、基板と下地膜との間に高融点金属膜を設けることは、そのバランスを崩してしまうことが懸念される。
【００２３】
また、ＳＬＳ法は、マスクと基板との相対的な位置決めの技術にミクロン単位での精密な制御が必要であり、通常のレーザ照射装置と比較して複雑な装置になってしまう。さらに、大面積領域を有する液晶ディスプレイに適用されるＴＦＴの作製に用いるにはスループットに問題がある。
【００２４】
本発明はこれらのような問題点を解決するための技術であり、結晶粒の位置とその大きさを制御した結晶質半導体膜を作製し、さらに前記結晶質半導体膜をＴＦＴのチャネル形成領域に用いることにより、高速動作が可能なＴＦＴを実現する。さらにそのようなＴＦＴを透過型の液晶表示装置やエレクトロルミネッセンス材料を用いた表示装置などのさまざまな半導体装置に適用できる技術を提供することを目的とする。
【００２５】
【課題を解決するための手段】
合成石英ガラス基板上に窒化珪素膜を形成し、前記窒化珪素膜上に窒化酸化珪素膜（Ａ−ｔｙｐｅ）を形成し、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）上に膜厚５５ｎｍの非晶質珪素膜を形成する第２のサンプルを用いて、シミュレーションを行なう。前記第２のサンプルに対し、基板の裏面側からレーザビームを照射し、非晶質珪素膜に対する前記レーザビームの反射率の計算を行なった結果を図２〜図３に示す。図２（ａ）は窒化珪素膜の膜厚を５０ｎｍに固定した場合の窒化酸化珪素膜（Ａ−ｔｙｐｅ）膜厚依存の計算結果を示し、図２（ｂ）は窒化酸化珪素膜（Ａ−ｔｙｐｅ）膜厚を１００ｎｍに固定した場合の窒化珪素膜の膜厚依存の計算結果を示している。計算を行なう際、レーザビームの波長は３０８ｎｍとし、その他のパラメータについては表１に示したものを用いた。
【００２６】
図２（ａ）より、同じレーザビームの照射エネルギーであっても窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を変化させることによって、非晶質珪素膜に対する反射率が周期的に変化していることが分かる。また、図２（ｂ）より、同じレーザビームの照射エネルギーであっても窒化珪素膜の膜厚を変化させることによって、非晶質珪素膜に対する反射率が周期的に変化していることが分かる。
【００２７】
次に、前記第２のサンプルに対して、レーザビームの波長を５３２ｎｍにして計算した結果を図３に示す。図３（ａ）は窒化珪素膜の膜厚を５０ｎｍに固定した場合の窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚依存の計算結果を示し、図３（ｂ）は窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を１００ｎｍに固定した場合の窒化珪素膜の膜厚依存の計算結果を示している。また、計算を行なう際に用いたパラメータについては表２に示す。
【００２８】
【表２】

【００２９】
図３（ａ）より、同じレーザビームの照射エネルギーであっても窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を変化させることによって、非晶質珪素膜に対する反射率が周期的に変化していることが分かる。また、図３（ｂ）より、窒化珪素膜の膜厚を変化させることによって、非晶質珪素膜に対する反射率が周期的に変化していることが分かる。
【００３０】
つまり、基板の裏面側からレーザビームを照射する場合、屈折率の異なる複数の下地絶縁膜のうち、少なくとも１層の下地絶縁膜の膜厚を変化させることによって、前記非晶質珪素膜に対する前記レーザビームの実効的な照射強度を変化させることが出来ることがわかる。さらに、前記非晶質珪素膜に対する反射率の周期的な変化はレーザビームの波長を変えても現れることが分かる。但し、反射率の変化の周期はレーザビームの波長、下地絶縁膜の膜厚等によって異なる。
【００３１】
次に、合成石英ガラス基板上に下層窒化酸化珪素膜を形成し、前記下層窒化酸化珪素膜上に膜厚１００ｎｍの窒化酸化珪素膜（Ａ−ｔｙｐｅ）を形成し、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）上に膜厚５５ｎｍの非晶質珪素膜を形成する第３のサンプルを用いて、シミュレーションを行なう。なお、下層窒化酸化珪素膜とは、窒化酸化珪素膜（Ａ−ｔｙｐｅ）や窒化酸化珪素膜（Ｂ−ｔｙｐｅ）と差別化するために用いており、このシミュレーションにおいて下層窒化酸化珪素膜の組成比を変えることで、前記下層窒化酸化珪素膜の屈折率を変えている。このような第３のサンプルに対し、基板の裏面側から波長３０８ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率を図１０（ａ）に示す。図１０（ａ）より、前記下層窒化酸化珪素膜の屈折率の変化に伴って、非晶質珪素膜に対する反射率も変化していることがわかる。
【００３２】
一方、合成石英ガラス基板上に膜厚１００ｎｍの窒化酸化珪素膜（Ａ−ｔｙｐｅ）を形成し、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）上に膜厚５５ｎｍの非晶質珪素膜を形成する第４のサンプルに、波長３０８ｎｍのレーザビームを照射したときの非晶質半導体膜に対する反射率は、図２（ｂ）の窒化珪素膜の膜厚が０ｎｍの場合を読み取れば、４２．５％であることが分かる。つまり、下層窒化酸化珪素膜の組成比における窒素の割合を増やして、前記下層窒化酸化珪素膜の膜質を窒化酸化珪素膜（Ａ−ｔｙｐｅ）に近付けると、非晶質珪素膜に対するレーザビームの反射率は、下地絶縁膜を下層窒化酸化珪素膜と窒化酸化珪素膜（Ａ−ｔｙｐｅ）の積層にした場合と、窒化酸化珪素膜（Ａ−ｔｙｐｅ）のみの場合と同程度になる。つまり、屈折率が近い下地絶縁膜を積層にして、前記下地絶縁膜のうちの１層に段差を設けて膜厚に段階をつけても、半導体膜におけるレーザビームの強度分布が生じず、積層にした意味があまりないことがわかる。
【００３３】
続いて、第３のサンプルに波長５３２ｎｍのレーザビームを基板の裏面側から照射し、下層窒化酸化珪素膜の組成比を変えることで、前記下層窒化酸化珪素膜の屈折率を変化させ、非晶質珪素膜に対する反射率を変化させている。その結果を図１０（ｂ）に示す。一方、前記第４のサンプルに波長５３２ｎｍのレーザビームを照射したときの非晶質半導体膜に対する反射率は、図３（ｂ）の窒化珪素膜膜厚が０ｎｍのところから読み取れば、１０％であることが分かる。波長５３２ｎｍのレーザビームの場合でも、下層窒化酸化珪素膜の組成比を変化させて、前記下層窒化酸化珪素膜の膜質を窒化酸化珪素膜（Ａ−ｔｙｐｅ）に近付けると、非晶質珪素膜に対する反射率は下地絶縁膜を下層窒化酸化珪素膜と窒化酸化珪素膜（Ａ−ｔｙｐｅ）の積層にした場合と、窒化酸化珪素膜（Ａ−ｔｙｐｅ）のみの場合と同程度になる。つまり、波長５３２ｎｍのレーザビームを用いた場合でも、屈折率が近い下地絶縁膜を積層にして、前記下地絶縁膜のうちの１層に段差を設けて膜厚に段階をつけても、非晶質珪素膜においてレーザビームの実効的な強度分布が生じず、積層にした意味があまりないことがわかる。
【００３４】
また、表２より、窒化酸化珪素膜（Ａ−ｔｙｐｅ）、コーニング社製１７３７基板、および合成石英ガラス基板は波長５３２ｎｍに対する屈折率が同程度になっている。そこで、基板として１７３７ガラス基板や合成石英ガラス基板を用い、前記基板上に段差を設けて膜厚に段階をつけた窒化酸化珪素膜（Ａ−ｔｙｐｅ）を形成し、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）上に非晶質珪素膜を形成し、前記基板の裏面側からレーザビームを照射する。しかしながら、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）に設けた段差よりも前記基板の表面の凹凸の方が粗いため、前記基板の裏面側からレーザビームを照射しても、前記非晶質珪素膜において実効的なレーザビームの強度分布がほとんど生じない。つまり、用いるレーザビームの波長に対して、基板上に成膜する下地絶縁膜は、前記基板と同程度の屈折率では意味がなく、前記基板とは屈折率の異なるものにする必要があることがわかる。
【００３５】
このように、非晶質半導体膜に対する反射率が変化するのは、積層した複数の下地絶縁膜の薄膜の干渉効果によるものであり、積層した複数の下地絶縁膜の膜厚と屈折率の組み合わせで、任意のレーザビームの強度分布を得ることができる。以上のことから、本発明は、複数の下地絶縁膜を用い、かつ、前記複数の下地絶縁膜のうち少なくとも１層は段差を設けて膜厚に段階を付けることによって、大粒径で、しかも位置制御された結晶粒を有する結晶質半導体膜を形成することを可能とする。但し、複数の下地絶縁膜は屈折率の異なる少なくとも２種類の絶縁膜を用いるものとし、レーザビームの照射は基板の裏面側から、または基板の表面側と裏面側の両側から行なうものとする。
【００３６】
【発明の実施の形態】
［実施形態１］
本実施形態を図４を用いて説明する。図４（ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。例えば、コーニング社製の７０５９ガラスや１７３７ガラスなどを好適に用いることが出来る。
【００３７】
前記基板１００１の上に第１の下地絶縁膜１００２を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝２７％、Ｎ＝２４％、Ｈ＝１７％）などで形成する。本実施形態では、プラズマＣＶＤ法を用い、窒化珪素膜を５０ｎｍ形成する。
【００３８】
この上に前記第１の下地絶縁膜１００２と屈折率の異なる第２の下地絶縁膜１００３を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により酸化珪素膜、酸化窒化珪素膜などで形成する。本実施形態では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１３０〜１５０ｎｍ形成する。
【００３９】
第２の下地絶縁膜１００３を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が１３０〜１５０ｎｍの部分と７８〜９８ｎｍの部分を有する第３の下地絶縁膜１００４を得る（図４（ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００４０】
前記第３の下地絶縁膜１００４を２段階の膜厚にするのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ａ）において周期的に現れる非晶質珪素膜に対する反射率の最大値６２．５％程度に相当する膜厚が１３０〜１５０ｎｍであり、前記非晶質珪素膜に対する最小値２２．７％程度に相当する膜厚が７８〜９８ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第３の下地絶縁膜１００４の２段階の膜厚の差は、この後に形成される非晶質半導体膜の膜厚より小さい方が望ましい。また、第２の下地絶縁膜１００４の段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保するのが望ましい。
【００４１】
図４（ｂ）に示す非晶質半導体膜１００５を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに、段差を持つ第３の下地絶縁膜１００４に沿って形成する。本実施形態では非晶質珪素膜を５５ｎｍの膜厚で形成する。但し、前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【００４２】
図４（ｃ）は裏面側からレーザビームを照射する結晶化工程を説明する図であり、図４（ｄ）では基板の表面側と裏面側の両側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、いずれかの方法を用いることとする。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【００４３】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【００４４】
前述のいずれかのレーザ発振器を用いて、図４（ｃ）または（ｄ）のいずれかの照射方法で前記非晶質半導体膜の結晶化を行なう。既に述べたように、第３の下地絶縁膜１００４の膜厚が２段階になっているため、裏面側からレーザビームが照射されると、前記非晶質半導体膜１００５に対する前記レーザビームの反射率は領域Ａでは２２．７％程度、領域Ｂでは６２．５％程度になっており、レーザビームの実効的な強度が異なっている。
【００４５】
さらに、図４（ｃ）または図４（ｄ）の第３の下地絶縁膜１００４における段差端（領域Ａと領域Ｂの境界）は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第２の下地絶縁膜における段差端上の半導体膜から固相化が始まり、結晶核１００６が発生する。この結晶核が結晶成長の中心となり、温度が高く溶融状態の領域Ａまたは領域Ｂに向かって結晶成長が進行する。但し、領域Ａの方が領域Ｂよりレーザビームの吸収率が高いため、結晶核は１００７で示す方向へ成長するので、領域Ａの半導体膜にはより大粒径の結晶粒が形成される。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。（図４（ｅ））
【００４６】
レーザビームを照射した後、前記結晶質半導体膜は、３〜１００％の水素を含む雰囲気中で３００〜４５０℃の加熱処理、あるいは、プラズマによって生成された水素を含む雰囲気中で２００〜４５０℃の加熱処理によって、残留する欠陥を中和することができる。このようにして作製された結晶質半導体膜の領域Ａをチャネル形成領域として、ＴＦＴを作製することにより、前記ＴＦＴの電気的特性を向上させることができる。
【００４７】
［実施形態２］
本実施形態を図５を用いて説明する。図５（ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。例えば、コーニング社製の７０５９ガラスや１７３７ガラスなどを好適に用いることが出来る。
【００４８】
前記基板１００１の上に第１の下地絶縁膜１００９を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝２７％、Ｎ＝２４％、Ｈ＝１７％）などで形成する。本実施形態では、プラズマＣＶＤ法を用い、窒化珪素膜を５５〜８５ｎｍ形成する。
【００４９】
前記第１の下地絶縁膜１００９を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が５５〜８５ｎｍの部分と２５〜４５ｎｍの部分を有する第２の下地絶縁膜１０１０を得る（図５（ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００５０】
この上に前記第２の下地絶縁膜１０１０と屈折率の異なる第３の下地絶縁膜１０１１を公知の手段（ＬＰＣＶＤ法、またはプラズマＣＶＤ法等）により酸化珪素膜、酸化窒化珪素膜などで形成する。本実施形態では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１００ｎｍ形成する。
【００５１】
前記第２の下地絶縁膜１０１０を２段階の膜厚にしているのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ｂ）において周期的に現れる非晶質珪素膜に対する反射率の最大値４２．５％程度に相当する膜厚が５５〜８５ｎｍであり、前記非晶質珪素膜に対する最小値２０％程度に相当する膜厚が２５〜４５ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第２の下地絶縁膜１０１０の２段階の膜厚の差は、この後に形成される非晶質半導体膜の膜厚より小さい方が望ましい。また、第２の下地絶縁膜１０１０の段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保するのが望ましい。
【００５２】
図５（ｂ）に示す非晶質半導体膜１０１２を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに第３の下地絶縁膜１０１１に沿って形成する。本実施形態では、非晶質珪素膜を５５ｎｍ形成する。但し、前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【００５３】
図５（ｃ）は裏面側からレーザビームを照射する結晶化工程を説明する図であり、図５（ｄ）では基板の表面側と裏面側の両側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、いずれかの方法を用いることとする。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【００５４】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【００５５】
前述のいずれかのレーザ発振器を用いて、図５（ｃ）または（ｄ）のいずれかの照射方法で非晶質半導体膜の結晶化を行なう。既に述べたように、第２の下地絶縁膜１０１０の膜厚が２段階になっているため、裏面側からレーザビームが照射されると、前記非晶質半導体膜１０１２に対する前記レーザビームの反射率は領域Ａでは２０％程度、領域Ｂでは４２．５％程度になっており、レーザビームの実効的な強度が異なっている。
【００５６】
さらに、図５（ｃ）または図５（ｄ）の第２の下地絶縁膜１０１０における段差端（領域Ａと領域Ｂの境界）は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第２の下地絶縁膜における段差端上の半導体膜から固相化が始まり、結晶核１００６が発生する。この結晶核が結晶成長の中心となり、温度が高く溶融状態の領域Ａまたは領域Ｂに向かって結晶成長が進行する。但し、領域Ａの方が領域Ｂよりレーザビームの吸収率が高いため、結晶核は１００７で示す方向へ成長するので、領域Ａの半導体膜にはより大粒径の結晶粒が形成される。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。（図５（ｅ））
【００５７】
レーザビームを照射した後、前記結晶質半導体膜は、３〜１００％の水素を含む雰囲気中で３００〜４５０℃の加熱処理、あるいは、プラズマによって生成された水素を含む雰囲気中で２００〜４５０℃の加熱処理によって、残留する欠陥を中和することができる。このようにして作製された結晶質半導体膜の領域Ａをチャネル形成領域として、ＴＦＴを作製することにより、前記ＴＦＴの電気的特性を向上させることができる。
【００５８】
［実施形態３］
本実施形態を図６を用いて説明する。図６（ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。例えば、コーニング社製の７０５９ガラスや１７３７ガラスなどを好適に用いることが出来る。
【００５９】
前記基板１００１の上に第１の下地絶縁膜１０１６を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝２７％、Ｎ＝２４％、Ｈ＝１７％）などで形成する。本実施形態では、プラズマＣＶＤ法を用い、窒化珪素膜を５０ｎｍ形成する。
【００６０】
この上に前記第１の下地絶縁膜１０１６と屈折率の異なる第２の下地絶縁膜１０１７を公知の手段（ＬＰＣＶＤ法、またはプラズマＣＶＤ法等）により酸化珪素膜、酸化窒化珪素膜などで形成する。本実施形態では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を７８〜９８ｎｍ形成する。
【００６１】
第２の下地絶縁膜１０１７を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が２５〜４５ｎｍの部分と７８〜９８ｎｍの部分を有する第３の下地絶縁膜１０１８を得る（図６（ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００６２】
前記第３の下地絶縁膜１０１８を２段階の膜厚にするのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ａ）において周期的に現れる非晶質珪素膜に対する反射率の最大値６２．５％程度に相当する膜厚が２５〜４５ｎｍであり、前記非晶質珪素膜に対する最小値２２．７％程度に相当する膜厚が７８〜９８ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第３の下地絶縁膜１０１８の２段階の膜厚の差は、この後に形成される非晶質半導体膜の膜厚より小さい方が望ましい。また、第３の下地絶縁膜１０１８の段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保するのが望ましい。
【００６３】
図６（ｂ）に示す非晶質半導体膜１０１９を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに、段差を持つ第３の下地絶縁膜１０１８に沿って形成する。本実施形態では非晶質珪素膜を５５ｎｍ形成する。但し、前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【００６４】
図６（ｃ）は裏面側からレーザビームを照射する結晶化工程を説明する図であり、図６（ｄ）では基板の表面側と裏面側の両側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、いずれかの方法を用いることとする。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【００６５】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【００６６】
前述のいずれかのレーザ発振器を用いて、図６（ｃ）または（ｄ）のいずれかの照射方法で前記非晶質半導体膜の結晶化を行なう。既に述べたように、第３の下地絶縁膜１０１８の膜厚が２段階になっているため、裏面側からレーザビームが照射されると、前記非晶質半導体膜１０１９対する前記レーザビームの反射率は領域Ａでは２２．７％程度、領域Ｂでは６２．５％程度になっており、レーザビームの実効的な強度が異なっている。
【００６７】
さらに、図６（ｃ）または図６（ｄ）の第３の下地絶縁膜１０１８における段差端（領域Ａと領域Ｂの境界）は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第３の下地絶縁膜における段差端上の半導体膜から固相化が始まり、結晶核１００６が発生する。この結晶核が結晶成長の中心となり、温度が高く溶融状態の領域Ａまたは領域Ｂに向かって結晶成長が進行する。但し、領域Ａの方が領域Ｂよりレーザビームの吸収率が高いため、結晶核は１００７で示す方向へ成長するので、領域Ａの半導体膜にはより大粒径の結晶粒が形成される。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。（図６（ｅ））
【００６８】
レーザビームを照射した後、前記結晶質半導体膜は、３〜１００％の水素を含む雰囲気中で３００〜４５０℃の加熱処理、あるいは、プラズマによって生成された水素を含む雰囲気中で２００〜４５０℃の加熱処理によって、残留する欠陥を中和することができる。このようにして作製された結晶質半導体膜の領域Ａをチャネル形成領域として、ＴＦＴを作製することにより、前記ＴＦＴの電気的特性を向上させることができる。
【００６９】
【実施例】
［実施例１］
ここでは、本発明のシミュレーション結果について図７〜８を用いて説明する。
【００７０】
図７（ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。本実施例では合成石英ガラス基板を用いている。
【００７１】
前記基板１００１の上に第１の下地絶縁膜１０２３を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、窒化珪素膜を５０ｎｍ形成した。
【００７２】
前記第１の下地絶縁膜１０２３上に前記第１の下地絶縁膜と屈折率の異なる第２の下地絶縁膜１０２４を公知の手段（ＬＰＣＶＤ法、またはプラズマＣＶＤ法等）により酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１４０ｎｍ形成した。
【００７３】
前記第２の下地絶縁膜１０２４を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が１４０ｎｍの部分と８８ｎｍの部分を有する第３の下地絶縁膜１０２５を得る（図７（ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００７４】
前記第３の下地絶縁膜１０２５を２段階の膜厚にするのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ａ）において周期的に現れる非晶質珪素膜に対する反射率の最大値６２．５％に相当する膜厚が１４０ｎｍであり、前記非晶質珪素膜に対する最小値２２．７％に相当する膜厚が８８ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第３の下地絶縁膜１０２５の２段階の膜厚の差は、この後に形成される半導体膜の膜厚より小さい方が望ましい。また、第３の下地絶縁膜１０２５の段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保する。
【００７５】
図７（ｂ）に示す非晶質半導体膜１０２６を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに段差を持つ第３の下地絶縁膜１０２５に沿って形成する。本実施例では、プラズマＣＶＤ法を用い、非晶質珪素膜を５０ｎｍ形成する。前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【００７６】
図７（ｃ）は裏面側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、基板の裏面側からの照射、または基板の表面側と裏面側の両側からの照射のいずれかの方法を用いるが、本実施例では、基板の裏面側から照射した。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【００７７】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【００７８】
本実施例ではエキシマレーザ（波長３０８ｎｍ、パルス幅３０ｎｓ）を用いて、図７（ｃ）の照射方法で非晶質珪素膜の結晶化を行なった。既に述べたように、第３の下地絶縁膜１０２５の膜厚が２段階になっているため、裏面側からレーザビームが照射されると、非晶質珪素膜に対する前記レーザビームの反射率は領域Ａでは２２．７％程度、領域Ｂでは６２．５％程度になっており、レーザビームの実効的な強度が異なっている。
【００７９】
さらに、図７（ｃ）の第３の下地絶縁膜１０２５における段差端（領域Ａと領域Ｂの境界）は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第３の下地絶縁膜１０２５における段差端から固相化が始まり、結晶核１００６が発生する。この結晶核が結晶成長の中心となり、温度が高く溶融状態の領域Ａまたは領域Ｂに向かって結晶成長が進行する。但し、領域Ａの方が領域Ｂよりレーザビームの吸収率が高いため、結晶核は１００７で示す方向へ成長するので、領域Ａの半導体膜にはより大粒径の結晶粒が形成される。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。
【００８０】
比較のため、合成石英ガラス基板上に窒化酸化珪素膜（Ａ−ｔｙｐｅ）を形成し、前記窒化酸化珪素膜（Ａ−ｔｙｐｅ）に膜厚５５ｎｍの非晶質珪素膜を形成したサンプルに対して、シミュレーションを行い、固相化開始時間の比較を図８に示す。但し、窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚は本実施例で既に示したように、８８ｎｍと１４０ｎｍの２段階の膜厚を持つ。図８は下地段差端（図７（ｃ）の領域Ａと領域Ｂの境界）から領域Ａへの距離と固相開始時間との関係を示している。図８から、例え段差を有する下地膜を用いても、下地膜が１層である場合より、本発明の構成での結晶化は、レーザビームの照射後の半導体膜の固相化がゆっくり進むので、大粒形の結晶粒を得ることができることがわかる。
【００８１】
レーザビームを照射した後、前記結晶質半導体膜は、３〜１００％の水素を含む雰囲気中で３００〜４５０℃の加熱処理、あるいは、プラズマによって生成された水素を含む雰囲気中で２００〜４５０℃の加熱処理によって、残留する欠陥を中和することができる。このようにして作製された結晶質半導体膜の領域Ａをチャネル形成領域として、ＴＦＴを作製することにより、前記ＴＦＴの電気的特性を向上させることができる。
【００８２】
［実施例２］
ここでは、本発明の構成を用い、非晶質珪素膜を熱処理によって部分的に結晶化させたのち、レーザアニールを行なう方法について説明する。図９（ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。本実施例では合成石英ガラス基板を用いている。
【００８３】
前記基板１００１の上に第１の下地絶縁膜１０２８を公知の手段（ＬＰＣＶＤ法、またはプラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、窒化珪素膜を５０ｎｍ形成した。
【００８４】
この上に前記第１の下地絶縁膜１０２８と屈折率の異なる第２の下地絶縁膜１０２９を公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１４０ｎｍ形成した。
【００８５】
前記第２の下地絶縁膜１０２９を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が１４０ｎｍの部分と８８ｎｍの部分を有する第３の下地絶縁膜１０３０を得る（図９（ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００８６】
前記第３の下地絶縁膜１０３０を２段階の膜厚にするのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ａ）において周期的に現れる非晶質珪素膜に対する反射率の最大値６２．５％に相当する膜厚が１４０ｎｍであり、前記非晶質珪素膜に対する最小値２２．７％に相当する膜厚が８８ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第３の下地絶縁膜１０３０の２段階の膜厚の差は、この後に形成される半導体膜の膜厚より小さい方が望ましい。また、第３の下地絶縁膜１０３０の段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保する。
【００８７】
図９（ｂ）に示す非晶質半導体膜１０３１を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに段差を持つ第３の下地絶縁膜１０３０に沿って形成する。本実施例では、プラズマＣＶＤ法を用い、非晶質珪素膜を５０ｎｍ形成する。前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【００８８】
次に、特開平７−１８３５４０号公報に記載されている方法により、前記非晶質珪素膜を部分的に結晶化させる。ここで、前記方法を簡単に説明する。まず、非晶質半導体膜にニッケルまたは、パラジウム、または鉛等の元素を微量に添加する。添加の方法は、プラズマ処理法や蒸着法、イオン注入法、スパッタ法、溶液塗布法等を利用すればよい。前記添加の後、例えば５５０℃の窒素雰囲気に４時間、非晶質半導体膜を置くと、電気的特性の良好な結晶質半導体膜が得られる。結晶化に最適な加熱温度や加熱時間等は、前記元素の添加量や、非晶質半導体膜の状態による。例えば、前記溶液塗布法を適用し、溶液に酢酸ニッケル溶液を用いるなら、重量換算で濃度１０ｐｐｍのものを５ｍｌ、スピンコート法により膜上全面に塗布して金属含有層１０３２を形成する。（図９（ｂ））次に、基板に対し、温度５００℃の窒素雰囲気に１時間、更に連続的に、温度５５０℃の窒素雰囲気に４時間の加熱を行って、部分的に結晶化した第１の結晶質珪素膜１０３３を得る。（図９（ｃ））
【００８９】
図９（ｄ）は裏面側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、基板の裏面側からの照射、または基板の表面側と裏面側の両側からの照射のいずれかの方法を用いるが、本実施例では、基板の裏面側から照射した。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【００９０】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【００９１】
本実施例ではエキシマレーザ（波長３０８ｎｍ、パルス幅３０ｎｓ）を用いて、図９（ｄ）の照射方法で非晶質珪素膜の結晶化を行なった。既に述べたように、第３の下地絶縁膜１０３０の膜厚が２段階になっているため、裏面側からレーザビームが照射されると、前記レーザビームの反射率は領域Ａでは２２．７％程度、領域Ｂでは６２．５％程度になっており、前記第１の結晶質珪素膜１０３３に対するレーザビームの実効的な強度が異なっている。
【００９２】
さらに、図９（ｄ）の第３の下地絶縁膜１０３０における段差端（領域Ａと領域Ｂの境界）は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第３の下地絶縁膜１０３０における段差端から半導体膜の固相化が始まり、結晶核１００６が発生する。この結晶核が結晶成長の中心となり、温度が高く溶融状態の領域Ａまたは領域Ｂに向かって結晶成長が進行する。但し、領域Ａの方が領域Ｂよりレーザビームの吸収率が高いため、結晶核は１００７で示す方向へ成長するので、領域Ａの半導体膜にはより大粒径の結晶粒が形成される。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。
【００９３】
レーザビームを照射した後、前記結晶質半導体膜は、３〜１００％の水素を含む雰囲気中で３００〜４５０℃の加熱処理、あるいは、プラズマによって生成された水素を含む雰囲気中で２００〜４５０℃の加熱処理によって、残留する欠陥を中和することができる。このようにして作製された結晶質半導体膜の領域Ａをチャネル形成領域として、ＴＦＴを作製することにより、前記ＴＦＴの電気的特性を向上させることができる。
【００９４】
［実施例３］
ここでは、同一基板上に画素部と、画素部の周辺に設ける駆動回路のＴＦＴ（ｎチャネル型ＴＦＴ及びｐチャネル型ＴＦＴ）を同時に作製する方法について詳細に図１１〜図１３を用いて説明する。
【００９５】
図１１（Ａ）において基板１００１にはバリウムホウケイ酸ガラスやアルミノホウケイ酸ガラスなどの無アルカリガラス基板や合成石英ガラス基板を用いる。本実施例では合成石英ガラス基板を用いている。
【００９６】
前記基板１００１の上に第１の下地絶縁膜１００ａを公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により窒化珪素膜、酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、窒化珪素膜を５０ｎｍ形成した。
【００９７】
この上に前記第１の下地絶縁膜と屈折率の異なる第２の下地絶縁膜１００ｂを公知の手段（ＬＰＣＶＤ法、プラズマＣＶＤ法等）により酸化窒化珪素膜などで形成する。本実施例では、プラズマＣＶＤ法を用い、酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）を１４０ｎｍ形成した。
【００９８】
前記第２の下地絶縁膜を形成した後フォトリソグラフィーの技術を用いレジストマスクを形成し、不要な部分をエッチングして、膜厚が１４０ｎｍの部分と８８ｎｍの部分を有する第３の下地絶縁膜１００ｃを得る（図１１（Ｂ））。前記エッチングにはフッ素系のガスを用いたドライエッチング法を用いても良いし、フッ素系の水溶液を用いたウエットエッチング法を用いても良い。前記ウエットエッチング法を選択する場合には、例えば、フッ化水素アンモニウム（ＮＨ₄ＨＦ₂）を７．１３％とフッ化アンモニウム（ＮＨ₄Ｆ）を１５．４％含む混合液（ステラケミファ社製、商品名ＬＡＬ５００）でエッチングしても良い。
【００９９】
前記第３の下地絶縁膜１００ｃを２段階の膜厚にするのは、半導体膜に対するレーザビームの実効的な強度分布を形成するためである。図２（ａ）において周期的に現れる非晶質珪素膜に対する反射率の最大値６２．５％に相当する膜厚が１４０ｎｍであり、前記非晶質珪素膜に対する最小値２２．７％に相当する膜厚が８８ｎｍとなっている。既に述べたように、前記非晶質珪素膜に対する反射率は周期性を持っているので、前記非晶質珪素膜に対する反射率の最大値程度と最小値程度に相当する膜厚であれば、前述の膜厚に限らない。但し、前記第３の下地絶縁膜１００ｂの２段階の膜厚の差は、この後に形成される半導体膜の膜厚より小さい方が望ましい。また、第３の下地絶縁膜１００ｂの段差における側壁の角度は、基板１００１に対して、５°以上８５°未満（好ましくは３０°〜６０°）となるようにテーパー状にエッチングしてこの上に積層させる膜のステップカバレージを確保する。
【０１００】
図１１（Ｃ）に示す非晶質半導体膜１０１を、プラズマＣＶＤ法やスパッタ法などの公知の方法で２５〜２００ｎｍ（好ましくは３０〜１００ｎｍ）の厚さに段差を持つ第３の下地絶縁膜１００ｃに沿って形成する。本実施例では、プラズマＣＶＤ法を用い、非晶質珪素膜を５０ｎｍ形成する。前記非晶質半導体膜としては、非晶質半導体膜や微結晶半導体膜があり、非晶質珪素ゲルマニウム膜などの非晶質構造を有する化合物半導体膜を適用しても良い。
【０１０１】
図１１（Ｃ）は裏面側からレーザビームを照射する結晶化工程を説明する図である。本発明においては、基板の裏面側からの照射、または基板の表面側と裏面側の両側からの照射のいずれかの方法を用いるが、本実施例では、基板の裏面側から照射した。レーザアニール法による結晶化は、まず非晶質半導体膜が含有する水素を放出させておくことが望ましく、４００〜５００℃で窒素雰囲気に１時間程度曝して、含有する水素量を５atom％以下にしておくと良い。これにより、膜の耐レーザ性が著しく向上する。
【０１０２】
レーザアニール法において用いるレーザ発振器について説明する。エキシマレーザは大出力で、現状で３００Ｈｚ程度の高繰り返しのパルスを発振出来るため、良く用いられている。また、パルス発振のエキシマレーザだけでなく、連続発振のエキシマレーザや、Ａｒレーザ、ＹＡＧレーザ、ＹＶＯ₄レーザ、ＹＬＦレーザ等も用いることが出来る。
【０１０３】
本実施例ではエキシマレーザ（波長３０８ｎｍ、パルス幅３０ｎｓ）を用いて、図１１（Ｃ）の照射方法で非晶質珪素膜の結晶化を行なった。既に述べたように、第３の下地絶縁膜１００ｃの膜厚が２段階になっているため、裏面側からレーザビームが照射されると、非晶質半導体膜に対する前記レーザビームの反射率は領域Ａでは６２．５％程度、領域Ｂでは２２．７％程度になっており、レーザビームの実効的な強度が異なっている。
【０１０４】
さらに、図１１（Ｃ）の第３の下地絶縁膜における段差端は、熱の逃げる場所として、▲１▼直下の下地絶縁膜と▲２▼横方向に存在する下地絶縁膜の両方があるため、他の場所と比較して早く冷める。そのため、最初に温度の下がる前記第３の下地絶縁膜１００ｃにおける段差端上の半導体膜から固相化が始まり、結晶の核が発生する。この核が結晶成長の中心となり、温度が高く溶融状態の領域に向かって結晶成長が進行する。このようにして、大粒径で、位置制御された結晶粒を持つ結晶質半導体膜を形成することができる。
【０１０５】
レーザビームを照射した後、結晶質半導体膜をフォトリソグラフィー法を用いたパターニング処理によって、半導体層１０２〜１０６を形成した。
【０１０６】
また、半導体層１０２〜１０６を形成した後、ＴＦＴのしきい値を制御するために微量な不純物元素（ボロンまたはリン）のドーピングを行ってもよい。
【０１０７】
次いで、半導体層１０２〜１０６を覆うゲート絶縁膜１０７を形成する。ゲート絶縁膜１０７はプラズマＣＶＤ法またはスパッタ法を用い、厚さを４０〜１５０ｎｍとして珪素を含む絶縁膜で形成する。本実施例では、プラズマＣＶＤ法により１１０ｎｍの厚さで酸化窒化珪素膜（組成比Ｓｉ＝３２％、Ｏ＝５９％、Ｎ＝７％、Ｈ＝２％）で形成した。勿論、ゲート絶縁膜は酸化窒化珪素膜に限定されるものでなく、他の珪素を含む絶縁膜を単層または積層構造として用いても良い。
【０１０８】
また、酸化珪素膜を用いる場合には、プラズマＣＶＤ法でＴＥＯＳ（Tetraethyl Orthosilicate）とＯ₂とを混合し、反応圧力４０Ｐａ、基板温度３００〜４００℃とし、高周波（１３．５６MHz）電力密度０．５〜０．８Ｗ／ｃｍ²で放電させて形成することができる。このようにして作製される酸化珪素膜は、その後４００〜５００℃の熱アニールによりゲート絶縁膜として良好な電気的特性を得ることができる。
【０１０９】
次いで、図１１（Ｄ）に示すように、ゲート絶縁膜１０７上に膜厚２０〜１００ｎｍの第１の導電膜１０８と、膜厚１００〜４００ｎｍの第２の導電膜１０９とを積層形成する。本実施例では、膜厚３０ｎｍのＴａＮ膜からなる第１の導電膜４０８と、膜厚３７０ｎｍのＷ膜からなる第２の導電膜１０９を積層形成した。ＴａＮ膜はスパッタ法で形成し、Ｔａのターゲットを用い、窒素を含む雰囲気内でスパッタした。また、Ｗ膜は、Ｗのターゲットを用いたスパッタ法で形成した。その他に６フッ化タングステン（ＷＦ₆）を用いる熱ＣＶＤ法で形成することもできる。いずれにしてもゲート電極として使用するためには低抵抗化を図る必要があり、Ｗ膜の抵抗率は２０μΩｃｍ以下にすることが望ましい。Ｗ膜は結晶粒を大きくすることで低抵抗率化を図ることができるが、Ｗ膜中に酸素などの不純物元素が多い場合には結晶化が阻害され高抵抗化する。従って、本実施例では、高純度のＷ（純度９９．９９９９％）のターゲットを用いたスパッタ法で、さらに成膜時に気相中からの不純物の混入がないように十分配慮してＷ膜を形成することにより、抵抗率９〜２０μΩｃｍを実現することができた。
【０１１０】
なお、本実施例では、第１の導電膜１０８をＴａＮ、第２の導電膜１０９をＷとしたが、特に限定されず、いずれもＴａ、Ｗ、Ｔｉ、Ｍｏ、Ａｌ、Ｃｕ、Ｃｒ、Ｎｄから選ばれた元素、または前記元素を主成分とする合金材料若しくは化合物材料で形成してもよい。また、リン等の不純物元素をドーピングした結晶質珪素膜に代表される半導体膜を用いてもよい。また、ＡｇＰｄＣｕ合金を用いてもよい。また、第１の導電膜をタンタル（Ｔａ）膜で形成し、第２の導電膜をＷ膜とする組み合わせ、第１の導電膜を窒化チタン（ＴｉＮ）膜で形成し、第２の導電膜をＷ膜とする組み合わせ、第１の導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２の導電膜をＡｌ膜とする組み合わせ、第１の導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２の導電膜をＣｕ膜とする組み合わせとしてもよい。
【０１１１】
次に、フォトリソグラフィー法を用いてレジストからなるマスク１１０〜１１５を形成し、電極及び配線を形成するための第１のエッチング処理を行なう。第１のエッチング処理では第１及び第２のエッチング条件で行なう。本実施例では第１のエッチング条件として、ＩＣＰ（Inductively Coupled Plasma：誘導結合型プラズマ）エッチング法を用い、エッチング用ガスにＣＦ₄とＣｌ₂とＯ₂とを用い、それぞれのガス流量比を２５／２５／１０（ｓｃｃｍ）とし、１Ｐａの圧力でコイル型の電極に５００ＷのＲＦ（13.56MHz）電力を投入してプラズマを生成してエッチングを行った。ここでは、松下電器産業（株）製のＩＣＰを用いたドライエッチング装置（Model Ｅ６４５−□ＩＣＰ）を用いた。基板側（試料ステージ）にも１５０ＷのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。この第１のエッチング条件によりＷ膜をエッチングして第１の導電層の端部をテーパー形状とする。
【０１１２】
この後、レジストからなるマスク１１０〜１１５を除去せずに第２のエッチング条件に変え、エッチング用ガスにＣＦ₄とＣｌ₂とを用い、それぞれのガス流量比を３０／３０（ｓｃｃｍ）とし、１Ｐａの圧力でコイル型の電極に５００ＷのＲＦ（13.56MHz）電力を投入してプラズマを生成して約３０秒程度のエッチングを行った。基板側（試料ステージ）にも２０ＷのＲＦ（13.56MHz）電力を投入し、実質的に負の自己バイアス電圧を印加する。ＣＦ₄とＣｌ₂を混合した第２のエッチング条件ではＷ膜及びＴａＮ膜とも同程度にエッチングされる。なお、ゲート絶縁膜上に残渣を残すことなくエッチングするためには、１０〜２０％程度の割合でエッチング時間を増加させると良い。
【０１１３】
上記第１のエッチング処理では、レジストからなるマスクの形状を適したものとすることにより、基板側に印加するバイアス電圧の効果により第１の導電層及び第２の導電層の端部がテーパー形状となる。このテーパー部の角度は１５〜４５°となる。こうして、第１のエッチング処理により第１の導電層と第２の導電層から成る第１の形状の導電層１１７〜１２２（第１の導電層１１７ａ〜１２２ａと第２の導電層１１７ｂ〜１２２ｂ）を形成する。１１６はゲート絶縁膜であり、第１の形状の導電層１１７〜１２２で覆われない領域は２０〜５０ｎｍ程度エッチングされ薄くなった領域が形成される。
【０１１４】
そして、レジストからなるマスクを除去せずに第１のドーピング処理を行い、半導体層にｎ型を付与する不純物元素を添加する。（図１２（Ａ））ドーピング処理はイオンドープ法、若しくはイオン注入法で行なえば良い。イオンドープ法の条件はドーズ量を１×１０¹³〜５×１０¹⁵ａｔｏｍｓ／ｃｍ²とし、加速電圧を６０〜１００ｋｅＶとして行なう。本実施例ではドーズ量を１．５×１０¹⁵ａｔｏｍｓ／ｃｍ²とし、加速電圧を８０ｋｅＶとして行った。ｎ型を付与する不純物元素として１５族に属する元素、典型的にはリン（Ｐ）または砒素（Ａｓ）を用いるが、ここではリン（Ｐ）を用いた。この場合、導電層１１７〜１２１がｎ型を付与する不純物元素に対するマスクとなり、自己整合的に高濃度不純物領域１２３〜１２７が形成される。高濃度不純物領域１２３〜１２７には１×１０²⁰〜１×１０²¹ａｔｏｍｓ／ｃｍ³の濃度範囲でｎ型を付与する不純物元素を添加する。
【０１１５】
次いで、レジストからなるマスクを除去せずに第２のエッチング処理を行なう。ここでは、エッチングガスにＣＦ₄とＣｌ₂とＯ₂とを用い、Ｗ膜を選択的にエッチングする。この時、第２のエッチング処理により第１の導電層１２８ｂ〜１３３ｂを形成する。一方、第２の導電層１１７ａ〜１２２ａは、ほとんどエッチングされず、第２の導電層１２８ａ〜１３３ａを形成する。次いで、第２のドーピング処理を行って図１２（Ｂ）の状態を得る。ドーピングは第２の導電層１１７ａ〜１２２ａを不純物元素に対するマスクとして用い、第１の導電層のテーパー部下方の半導体層に不純物元素が添加されるようにドーピングする。こうして、第１の導電層と重なる不純物領域１３４〜１３８を形成する。この不純物領域へ添加されたリン（Ｐ）の濃度は、第１の導電層のテーパー部の膜厚に従って緩やかな濃度勾配を有している。なお、第１の導電層のテーパー部と重なる半導体層において、第１の導電層のテーパー部の端部から内側に向かって若干、不純物濃度が低くなっているものの、ほぼ同程度の濃度である。また、第１の不純物領域１２３〜１２７にも不純物元素が添加され、不純物領域１３９〜１４３を形成する。
【０１１６】
次いで、レジストからなるマスクを除去せずに第３のエッチング処理を行なう。この第３のエッチング処理では第１の導電層のテーパー部を部分的にエッチングして、半導体層と重なる領域を縮小するために行われる。第３のエッチングは、エッチングガスにＣＨＦ₃を用い、反応性イオンエッチング法（ＲＩＥ法）を用いて行なう。第３のエッチングにより、第１の導電層１４４〜１４９が形成される。この時、同時に絶縁膜１１６もエッチングされて、絶縁膜１５０ａ〜１５０ｅ、１５１が形成される。
【０１１７】
上記第３のエッチングによって、第１の導電層１４４〜１４８と重ならない不純物領域（ＬＤＤ領域）１３４ａ〜１３８ａが形成される。なお、不純物領域（ＧＯＬＤ領域）１３４ｂ〜１３８ｂは、第１の導電層１４４〜１４８と重なったままである。
【０１１８】
このようにすることで、本実施例は、第１の導電層１４４〜１４８と重なる不純物領域（ＧＯＬＤ領域）１３４ｂ〜１３８ｂにおける不純物濃度と、第１の導電層１４４〜１４８と重ならない不純物領域（ＬＤＤ領域）１３４ａ〜１３８ａにおける不純物濃度との差を小さくすることができ、信頼性を向上させることができる。
【０１１９】
次いで、レジストからなるマスクを除去した後、新たにレジストからなるマスク１５２〜１５４を形成して第３のドーピング処理を行なう。この第３のドーピング処理により、ｐチャネル型ＴＦＴの活性層となる半導体層に前記一導電型とは逆の導電型を付与する不純物元素が添加された不純物領域１５５〜１６０を形成する。第２の導電層１２８ａ〜１３２ａを不純物元素に対するマスクとして用い、ｐ型を付与する不純物元素を添加して自己整合的に不純物領域を形成する。本実施例では、不純物領域１５５〜１６０はジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法で形成する。この第３のドーピング処理の際には、ｎチャネル型ＴＦＴを形成する半導体層はレジストからなるマスク１５２〜１５４で覆われている。
第１のドーピング処理及び第２のドーピング処理によって、不純物領域１５５〜１６０にはそれぞれ異なる濃度でリンが添加されているが、そのいずれの領域においてもｐ型を付与する不純物元素の濃度を２×１０²⁰〜２×１０²¹atoms/cm³となるようにドーピング処理することにより、ｐチャネル型ＴＦＴのソース領域およびドレイン領域として機能するために何ら問題は生じない。本実施例では、ｐチャネル型ＴＦＴの活性層となる半導体層の一部が露呈しているため、不純物元素（ボロン）を添加しやすい利点を有している。
【０１２０】
以上までの工程でそれぞれの半導体層に不純物領域が形成される。
【０１２１】
次いで、レジストからなるマスク１５２〜１５４を除去して第１の層間絶縁膜１６１を形成する。この第１の層間絶縁膜１６１としては、プラズマＣＶＤ法またはスパッタ法を用い、厚さを１００〜２００ｎｍとして珪素を含む絶縁膜で形成する。本実施例では、プラズマＣＶＤ法により膜厚１５０ｎｍの酸化窒化珪素膜を形成した。勿論、第１の層間絶縁膜１６１は酸化窒化珪素膜に限定されるものでなく、他の珪素を含む絶縁膜を単層または積層構造として用いても良い。
【０１２２】
次いで、図１３（Ｂ）に示すように、それぞれの半導体層に添加された不純物元素を活性化処理する工程を行なう。この活性化工程はファーネスアニール炉を用いる熱アニール法で行なう。熱アニール法としては、酸素濃度が１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下の窒素雰囲気中で４００〜７００℃、代表的には５００〜５５０℃で行なえばよく、本実施例では５５０℃、４時間の熱処理で活性化処理を行った。なお、熱アニール法の他に、レーザアニール法、またはラピッドサーマルアニール法（ＲＴＡ法）を適用することができる。
【０１２３】
なお、本実施例では、上記活性化処理と同時に、結晶化の際に触媒として使用したニッケルが高濃度のリンを含む不純物領域１３９、１４１、１４２、１５５、１５８にゲッタリングされ、主にチャネル形成領域となる半導体層中のニッケル濃度が低減される。このようにして作製したチャネル形成領域を有するＴＦＴはオフ電流値が下がり、結晶性が良いことから高い電界効果移動度が得られ、良好な電気的特性を達成することができる。
【０１２４】
また、第１の層間絶縁膜を形成する前に活性化処理を行っても良い。ただし、用いた配線材料が熱に弱い場合には、本実施例のように配線等を保護するため層間絶縁膜（珪素を主成分とする絶縁膜、例えば窒化珪素膜）を形成した後で活性化処理を行なうことが好ましい。
【０１２５】
さらに、３〜１００％の水素を含む雰囲気中で、３００〜５５０℃で１〜１２時間の熱処理を行い、半導体層を水素化する工程を行う。本実施例では水素を約３％の含む窒素雰囲気中で４１０℃、１時間の熱処理を行った。この工程は層間絶縁膜に含まれる水素により半導体層のダングリングボンドを終端する工程である。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素を用いる）を行っても良い。
【０１２６】
また、活性化処理としてレーザアニール法を用いる場合には、上記水素化を行った後、エキシマレーザやＹＡＧレーザ等のレーザビームを照射することが望ましい。
【０１２７】
次いで、第１の層間絶縁膜１６１上に無機絶縁膜材料または有機絶縁物材料から成る第２の層間絶縁膜１６２を形成する。本実施例では、膜厚１．６μｍのアクリル樹脂膜を形成したが、粘度が１０〜１０００ｃｐ、好ましくは４０〜２００ｃｐのものを用い、表面に凸凹が形成されるものを用いた。また、第２の層間絶縁膜１６２として表面が平坦化する膜を用いてもよい。
【０１２８】
本実施例では、鏡面反射を防ぐため、表面に凸凹が形成される第２の層間絶縁膜を形成することによって画素電極の表面に凸凹を形成した。また、画素電極の表面に凹凸を持たせて光散乱性を図るため、画素電極の下方の領域に凸部を形成してもよい。その場合、凸部の形成は、ＴＦＴの形成と同じフォトマスクで行なうことができるため、工程数の増加なく形成することができる。なお、この凸部は配線及びＴＦＴ部以外の画素部領域の基板上に適宜設ければよい。こうして、凸部を覆う絶縁膜の表面に形成された凸凹に沿って画素電極の表面に凸凹が形成される。
【０１２９】
そして、駆動回路において、各不純物領域とそれぞれ電気的に接続する配線１６３〜１６７を形成する。なお、これらの配線は、膜厚５０ｎｍのＴｉ膜と、膜厚５００ｎｍの合金膜（ＡｌとＴｉとの合金膜）との積層膜をパターニングして形成する。
【０１３０】
また、画素部においては、画素電極１７０、ゲート配線１６９、接続電極１６８を形成する。（図１３（Ｃ））この接続電極１６８によりソース配線（１４３ｂと１４９の積層）は、画素ＴＦＴと電気的な接続が形成される。また、ゲート配線１６９は、画素ＴＦＴのゲート電極と電気的な接続が形成される。また、画素電極１７０は、画素ＴＦＴのドレイン領域と電気的な接続が形成され、さらに保持容量を形成する一方の電極として機能する半導体層１５８と電気的な接続が形成される。また、画素電極１７０としては、ＡｌまたはＡｇを主成分とする膜、またはそれらの積層膜等の反射性の優れた材料を用いることが望ましい。
【０１３１】
以上の様にして、ｎチャネル型ＴＦＴ５０１とｐチャネル型ＴＦＴ５０２からなるＣＭＯＳ回路、及びｎチャネル型ＴＦＴ５０３を有する駆動回路５０６と、画素ＴＦＴ５０４、保持容量５０５とを有する画素部５０７を同一基板上に形成することができる。こうして、アクティブマトリクス基板が完成する。
【０１３２】
駆動回路５０６のｎチャネル型ＴＦＴ５０１はチャネル形成領域１７１、ゲート電極の一部を構成する第１の導電層１４４と重なる低濃度不純物領域１３４ｂ（ＧＯＬＤ領域）、ゲート電極の外側に形成される低濃度不純物領域１３４ａ（ＬＤＤ領域）とソース領域またはドレイン領域として機能する高濃度不純物領域１３９を有している。このｎチャネル型ＴＦＴ５０１と電極１６６で接続してＣＭＯＳ回路を形成するｐチャネル型ＴＦＴ５０２にはチャネル形成領域１７２、ゲート電極と重なる不純物領域１５７、ゲート電極の外側に形成される不純物領域１５６、ソース領域またはドレイン領域として機能する高濃度不純物領域１５５を有している。また、ｎチャネル型ＴＦＴ５０３にはチャネル形成領域１７３、ゲート電極の一部を構成する第１の導電層１４６と重なる低濃度不純物領域１３６ｂ（ＧＯＬＤ領域）、ゲート電極の外側に形成される低濃度不純物領域１３７ａ（ＬＤＤ領域）とソース領域またはドレイン領域として機能する高濃度不純物領域１４１を有している。
【０１３３】
画素部の画素ＴＦＴ５０４にはチャネル形成領域１７４、ゲート電極の一部を構成する第１の導電層１４７と重なる低濃度不純物領域１３７ｂ（ＧＯＬＤ領域）、ゲート電極の外側に形成される低濃度不純物領域１３７ａ（ＬＤＤ領域）とソース領域またはドレイン領域として機能する高濃度不純物領域１４２を有している。また、保持容量５０５の一方の電極として機能する半導体層１５８〜１６０には、それぞれｐ型を付与する不純物元素が添加されている。保持容量５０５は、絶縁膜１５１を誘電体として、電極（１４８と１３２ｂの積層）と、半導体層１５８〜１６０とで形成している。
【０１３４】
また、本実施例の画素構造は、ブラックマトリクスを用いることなく、画素電極間の隙間が遮光されるように、画素電極の端部をソース配線と重なるように配置形成する。
【０１３５】
本実施例で作製するアクティブマトリクス基板の画素部の上面図を図１４に示す。なお、図１１〜図１３に対応する部分には同じ符号を用いている。図１３中の鎖線Ａ−Ａ’は図１４中の鎖線Ａ―Ａ’で切断した断面図に対応している。また、図１３中の鎖線Ｂ−Ｂ’は図１４中の鎖線Ｂ―Ｂ’で切断した断面図に対応している。
【０１３６】
また、本実施例で示す工程に従えば、アクティブマトリクス基板の作製に必要なフォトマスクの数を５枚とすることができる。その結果、工程を短縮し、製造コストの低減及び歩留まりの向上に寄与することができる。
【０１３７】
［実施例４］
本実施例では、実施例３で作製したアクティブマトリクス基板から、反射型液晶表示装置を作製する工程を以下に説明する。説明には図１５を用いる。
【０１３８】
まず、実施例３に従い、図１３（ｃ）の状態のアクティブマトリクス基板を得た後、図１３（ｃ）のアクティブマトリクス基板上、少なくとも画素電極１７０上に配向膜４７０を形成しラビング処理を行なう。なお、本実施例では配向膜４７０を形成する前に、アクリル樹脂膜等の有機樹脂膜をパターニングすることによって基板間隔を保持するための柱状のスペーサ（図示しない）を所望の位置に形成した。また、柱状のスペーサに代えて、球状のスペーサを基板全面に散布してもよい。
【０１３９】
次いで、対向基板４７１を用意する。次いで、対向基板４７１上に着色層４７２、４７３、平坦化膜４７４を形成する。赤色の着色層４７２と青色の着色層４７３とを重ねて、遮光部を形成する。また、赤色の着色層と緑色の着色層とを一部重ねて、遮光部を形成してもよい。
【０１４０】
本実施例では、実施例３に示す基板を用いている。従って、実施例３の画素部の上面図を示す図１４では、少なくともゲート配線１６９と画素電極１７０の間隙と、ゲート配線１６９と接続電極１６８の間隙と、接続電極１６８と画素電極１７０の間隙を遮光する必要がある。本実施例では、それらの遮光すべき位置に着色層の積層からなる遮光部が重なるように各着色層を配置して、対向基板を貼り合わせた。
【０１４１】
このように、ブラックマスク等の遮光層を形成することなく、各画素間の隙間を着色層の積層からなる遮光部で遮光することによって工程数の低減を可能とした。
【０１４２】
次いで、平坦化膜４７４上に透明導電膜からなる対向電極４７５を少なくとも画素部に形成し、対向基板の全面に配向膜４７６を形成し、ラビング処理を施した。
【０１４３】
そして、画素部と駆動回路が形成されたアクティブマトリクス基板と対向基板とをシール材４７７で貼り合わせる。シール材４７７にはフィラーが混入されていて、このフィラーと柱状スペーサによって均一な間隔を持って２枚の基板が貼り合わせられる。その後、両基板の間に液晶材料４７８を注入し、封止剤（図示せず）によって完全に封止する。液晶材料４７８には公知の液晶材料を用いれば良い。このようにして図１５に示す反射型液晶表示装置が完成する。そして、必要があれば、アクティブマトリクス基板または対向基板を所望の形状に分断する。さらに、対向基板のみに偏光板（図示しない）を貼りつけた。そして、公知の技術を用いてＦＰＣを貼りつけた。
【０１４４】
以上のようにして作製される液晶表示パネルは各種電子機器の表示部として用いることができる。
【０１４５】
［実施例５］
本発明を実施して形成されたＣＭＯＳ回路や画素部は様々な電気光学装置（アクティブマトリクス型液晶ディスプレイ、アクティブマトリクス型ＥＣディスプレイ、アクティブマトリクス型ＥＬディスプレイ）に用いることが出来る。即ち、それら電気光学装置を表示部に組み込んだ電子機器全てに本発明を実施出来る。
【０１４６】
その様な電子機器としては、ビデオカメラ、デジタルカメラ、プロジェクター（リア型またはフロント型）、ヘッドマウントディスプレイ（ゴーグル型ディスプレイ）、カーナビゲーション、カーステレオ、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話または電子書籍等）などが挙げられる。それらの一例を図１６、図１７及び図１８に示す。
【０１４７】
図１６（Ａ）はパーソナルコンピュータであり、本体３００１、画像入力部３００２、表示部３００３、キーボード３００４等を含む。本発明を画像入力部３００２、表示部３００３やその他の信号制御回路に適用することが出来る。
【０１４８】
図１６（Ｂ）はビデオカメラであり、本体３１０１、表示部３１０２、音声入力部３１０３、操作スイッチ３１０４、バッテリー３１０５、受像部３１０６等を含む。本発明を表示部３１０２やその他の信号制御回路に適用することが出来る。
【０１４９】
図１６（Ｃ）はモバイルコンピュータ（モービルコンピュータ）であり、本体３２０１、カメラ部３２０２、受像部３２０３、操作スイッチ３２０４、表示部３２０５等を含む。本発明は表示部３２０５やその他の信号制御回路に適用出来る。
【０１５０】
図１６（Ｄ）はゴーグル型ディスプレイであり、本体３３０１、表示部３３０２、アーム部３３０３等を含む。本発明は表示部３３０２やその他の信号制御回路に適用することが出来る。
【０１５１】
図１６（Ｅ）はプログラムを記録した記録媒体（以下、記録媒体と呼ぶ）を用いるプレーヤーであり、本体３４０１、表示部３４０２、スピーカ部３４０３、記録媒体３４０４、操作スイッチ３４０５等を含む。なお、このプレーヤーは記録媒体としてＤＶＤ（Ｄｉｇｔｉａｌ Ｖｅｒｓａｔｉｌｅ Ｄｉｓｃ）、ＣＤ等を用い、音楽鑑賞や映画鑑賞やゲームやインターネットを行なうことが出来る。本発明は表示部３４０２やその他の信号制御回路に適用することが出来る。
【０１５２】
図１６（Ｆ）はデジタルカメラであり、本体３５０１、表示部３５０２、接眼部３５０３、操作スイッチ３５０４、受像部（図示しない）等を含む。本願発明を表示部３５０２やその他の信号制御回路に適用することが出来る。
【０１５３】
図１７（Ａ）はフロント型プロジェクターであり、投射装置３６０１、スクリーン３６０２等を含む。本発明は投射装置３６０１の一部を構成する液晶表示装置３８０８やその他の信号制御回路に適用することが出来る。
【０１５４】
図１７（Ｂ）はリア型プロジェクターであり、本体３７０１、投射装置３７０２、ミラー３７０３、スクリーン３７０４等を含む。本発明は投射装置３７０２の一部を構成する液晶表示装置３８０８やその他の信号制御回路に適用することが出来る。
【０１５５】
なお、図１７（Ｃ）は、図１７（Ａ）及び図１７（Ｂ）中における投射装置３６０１、３７０２の構造の一例を示した図である。投射装置３６０１、３７０２は、光源光学系３８０１、ミラー３８０２、３８０４〜３８０６、ダイクロイックミラー３８０３、プリズム３８０７、液晶表示装置３８０８、位相差板３８０９、投射光学系３８１０で構成される。投射光学系３８１０は、投射レンズを含む光学系で構成される。本実施例は三板式の例を示したが、特に限定されず、例えば単板式であってもよい。また、図１７（Ｃ）中において矢印で示した光路に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するためのフィルム、ＩＲフィルム等の光学系を設けてもよい。
【０１５６】
また、図１７（Ｄ）は、図１７（Ｃ）中における光源光学系３８０１の構造の一例を示した図である。本実施例では、光源光学系３８０１は、リフレクター３８１１、光源３８１２、レンズアレイ３８１３、３８１４、偏光変換素子３８１５、集光レンズ３８１６で構成される。なお、図１７（Ｄ）に示した光源光学系は一例であって特に限定されない。例えば、光源光学系に実施者が適宜、光学レンズや、偏光機能を有するフィルムや、位相差を調節するフィルム、ＩＲフィルム等の光学系を設けてもよい。
【０１５７】
ただし、図１７に示したプロジェクターにおいては、透過型の電気光学装置を用いた場合を示しており、反射型の電気光学装置での適用例は図示していない。
【０１５８】
図１８（Ａ）は携帯電話であり、本体３９０１、音声出力部３９０２、音声入力部３９０３、表示部３９０４、操作スイッチ３９０５、アンテナ３９０６等を含む。本願発明を音声出力部３９０２、音声入力部３９０３、表示部３９０４やその他の信号制御回路に適用することが出来る。
【０１５９】
図１８（Ｂ）は携帯書籍（電子書籍）であり、本体４００１、表示部４００２、４００３、記憶媒体４００４、操作スイッチ４００５、アンテナ４００６等を含む。本発明は表示部４００２、４００３やその他の信号回路に適用することが出来る。
【０１６０】
図１８（Ｃ）はディスプレイであり、本体４１０１、支持台４１０２、表示部４１０３等を含む。本発明は表示部４１０３に適用することが出来る。本発明のディスプレイは特に大画面化した場合において有利であり、対角１０インチ以上（特に３０インチ以上）のディスプレイには有利である。
【０１６１】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子機器に適用することが可能である。また、本実施例の電子機器は実施例１〜４のどのような組み合わせからなる構成を用いても実現することが出来る
【０１６２】
【発明の効果】
本発明の構成を採用することにより、以下に示すような基本的有意性を得ることが出来る。
（ａ）従来のＴＦＴの作製プロセスに完全に適合した、簡単な構造である。
（ｂ）下地絶縁膜の膜厚と屈折率は、簡単に、かつ精密に制御することが可能である。そのため、レーザビームの強度分布も、精密に位置制御しやすい。
（ｃ）スリットなどの位置決めのために、レーザ照射装置に特別なミクロンオーダーでの精密な位置決め技術は不要であり、通常のレーザ照射装置をそのまま利用できる。
（ｄ）以上の利点を満たした上で、位置制御した大粒径の結晶粒を作製できる方法である。
【図面の簡単な説明】
【図１】（Ａ）本発明者らが特願平１１−３５１０６０号で開示した発明の一例を示す図。
（Ｂ）（Ａ）の各点における温度履歴を示す図。
【図２】（ａ）窒化珪素膜の膜厚を固定し窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を変化させて、第２のサンプルに対し、基板の裏面側から波長３０８ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
（ｂ）窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を固定し窒化珪素膜の膜厚を変化させて、第２のサンプルに対し、基板の裏面側から波長３０８ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
【図３】 （ａ）窒化珪素膜の膜厚を固定し窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を変化させて、第２のサンプルに対し、基板の裏面側から波長５３２ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
（ｂ）窒化酸化珪素膜（Ａ−ｔｙｐｅ）の膜厚を固定し窒化珪素膜の膜厚を変化させて、第２のサンプルに対し、基板の裏面側から波長５３２ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
【図４】 本発明が開示する下地膜形成とレーザビームの照射の例を示す図。
【図５】 本発明が開示する下地膜形成とレーザビームの照射の例を示す図。
【図６】 本発明が開示する下地膜形成とレーザビームの照射の例を示す図。
【図７】 本発明が開示する下地膜形成とレーザビームの照射の例を示す図。
【図８】 本発明が開示する構成と特願平１１−３５１０６０号で開示した発明の一例における固相結晶化開始時間の比較を示す図。
【図９】 本発明が開示する下地膜形成とレーザビームの照射の例を示す図。
【図１０】（ａ）下層窒化酸化珪素膜の屈折率を変化させ、第３のサンプルに対し、基板の裏面側から波長３０８ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
（ｂ）下層窒化酸化珪素膜の屈折率を変化させ、第３のサンプルに対し、、基板の裏面側から波長５３２ｎｍのレーザビームを照射したときの非晶質珪素膜に対する反射率と吸収率を示す図。
【図１１】 画素ＴＦＴ、駆動回路のＴＦＴの作製工程を示す断面図。
【図１２】 画素ＴＦＴ、駆動回路のＴＦＴの作製工程を示す断面図。
【図１３】 画素ＴＦＴ、駆動回路のＴＦＴの作製工程を示す断面図。
【図１４】 画素部の画素を示す上面図。
【図１５】 アクティブマトリクス型液晶表示装置の作製工程を示す断面図。
【図１６】 半導体装置の例を示す図。
【図１７】 半導体装置の例を示す図。
【図１８】 半導体装置の例を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electric apparatus in which the electro-optical device is mounted as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and the electro-optical device and the electric appliance are also included in the category.
[0002]
[Prior art]
In recent years, a technique for crystallizing an amorphous semiconductor film formed on an insulating substrate such as glass by laser annealing to improve crystallinity has been widely studied. Silicon is often used for the amorphous semiconductor film.
[0003]
The glass substrate is cheaper and more workable than the synthetic quartz glass substrate that has been often used in the past, and has an advantage that a large-area substrate can be easily manufactured. This is the reason for the above research. In addition, the reason why lasers are used favorably for crystallization is that the melting point of the glass substrate is low. The laser can give high energy only to the amorphous semiconductor film without significantly increasing the temperature of the substrate.
[0004]
Since a crystalline semiconductor is made of many crystal grains, it is also called a polycrystalline semiconductor film. Since the crystalline semiconductor film formed by laser annealing has high mobility, a thin film transistor (TFT) is formed using this crystalline semiconductor film, for example, on a single glass substrate. It is actively used in monolithic liquid crystal electro-optical devices and the like for producing TFTs for driving circuits.
[0005]
Also, a pulse laser beam such as an excimer laser with a high output is processed by an optical system so that it becomes a square spot of several cm square or a linear shape with a length of 10 cm or more on the irradiated surface, and the laser beam is scanned. Therefore, a method of performing laser annealing by moving the irradiation position of the laser beam relative to the surface to be irradiated is preferred because it is highly productive and industrially excellent.
[0006]
In particular, when a linear beam is used, the laser beam is scanned over the entire irradiated surface by scanning only in the direction perpendicular to the longitudinal direction of the linear beam, unlike the case of using a spot laser beam that requires front-rear and left-right scanning. Since irradiation can be performed, productivity is high. The reason for scanning in the direction perpendicular to the longitudinal direction is that it is the most efficient scanning direction. Due to this high productivity, the use of a linear beam obtained by processing a pulsed excimer laser beam with an appropriate optical system in the laser annealing method is becoming the mainstream in the manufacturing technology of liquid crystal display devices using TFTs. The technology enables a monolithic liquid crystal display device in which a TFT (pixel TFT) for forming a pixel portion on one glass substrate and a TFT for a driving circuit provided around the pixel portion are formed.
[0007]
However, the crystalline semiconductor film manufactured by the laser annealing method is formed by aggregating a plurality of crystal grains, and the positions and sizes of the crystal grains are random. TFTs formed on a glass substrate are formed by separating the crystalline semiconductor by island patterning for element isolation. In that case, the position and size of the crystal grains could not be specified and formed. Compared with the inside of a crystal grain, the interface (crystal grain boundary) of a crystal grain has innumerable recombination centers and trap centers due to an amorphous structure or crystal defects. It is known that when carriers are trapped in this trapping center, the grain boundary potential rises and becomes a barrier against the carriers, so that the current transport characteristics of the carriers are reduced. The crystallinity of the semiconductor film in the channel formation region has a significant effect on the electrical characteristics of the TFT, but it is almost impossible to form the channel formation region with a single crystal semiconductor film by eliminating the influence of grain boundaries. It was possible.
[0008]
In order to solve such a problem, various attempts have been made to form crystal grains having a large grain size in which the position is controlled in the laser annealing method. Here, first, a solidification process of the semiconductor film after the semiconductor film is irradiated with a laser beam will be described.
[0009]
It takes a certain amount of time for solid-phase nucleation to occur in a liquid semiconductor film completely melted by laser beam irradiation, and innumerable uniform (or non-uniform) nucleation occurs in the completely melted region, resulting in crystal growth. This completes the solidification process of the liquid semiconductor film. In this case, the position and size of the crystal grains obtained are random.
[0010]
Further, in the case where the semiconductor film is not completely melted by the laser beam irradiation and the solid phase semiconductor region partially remains, crystal growth starts from the solid phase semiconductor region immediately after the laser beam irradiation. . As already described, it takes some time for nucleation to occur in the complete melting region. For this reason, a solid-liquid interface (completely coupled with the solid-state semiconductor region) that is the tip of crystal growth in a direction parallel to the film surface of the semiconductor film (hereinafter referred to as a lateral direction) until nucleation occurs in the complete melting region. The crystal grain grows to a length of several tens of times the film thickness by moving the interface with the molten region, which corresponds to the tip of the growth of the crystal nucleus. Such growth is terminated when crystallographic growth occurs with innumerable uniform (or non-uniform) nucleation in the complete melting region. Hereinafter, this phenomenon is referred to as super lateral growth.
[0011]
Even in an amorphous semiconductor film or a crystalline semiconductor film, there is an energy region of a laser beam that realizes the super lateral growth. However, the energy range is very narrow, and the position where large crystal grains are obtained cannot be controlled. Further, the region other than the large crystal grains was a microcrystalline region or an amorphous region where innumerable nucleation occurred.
[0012]
As explained above, if the temperature gradient in the lateral direction can be controlled in the energy region of the laser beam in which the semiconductor film is completely melted (a heat flow in the lateral direction is generated), the growth position and growth direction of the crystal grains Can be controlled. Various attempts have been made to realize this method.
[0013]
For example, in “R. Ishihara and A. Burtsev: AM-LCD '98., P153-p156, 1998”, a refractory metal film is formed between a substrate and an underlying silicon oxide film. An amorphous silicon film is formed above the substrate, and the laser beam of the excimer laser is defined as the surface side of the substrate (in this specification, the surface on which the film is formed) and the back side (in this specification, the film is There is a report on a laser annealing method that irradiates from both sides of a surface (defined as a surface opposite to a surface that is formed). The laser beam irradiated from the surface side of the substrate is absorbed by the silicon film and changed into heat. On the other hand, the laser beam irradiated from the back side of the substrate is absorbed by the refractory metal film and converted into heat, and the refractory metal film is heated at a high temperature. Since the heated silicon oxide film between the refractory metal film and the silicon film functions as a heat accumulation layer, the cooling rate of the molten silicon film can be reduced. Here, it has been reported that by forming a refractory metal film at an arbitrary location, crystal grains having a maximum diameter of 6.4 μm can be obtained at the desired location.
[0014]
In addition, James S. Im and others of Columbia University have shown a Sequential Lateral Solidification method (hereinafter referred to as SLS method) that can achieve super lateral growth in any place. In the SLS method, crystallization is performed by shifting the slit-shaped mask by about a distance (about 0.75 μm) at which super lateral growth is performed for each shot.
[0015]
[Problems to be solved by the invention]
The present inventors have described in Japanese Patent Application No. 11-35060 a method of increasing the grain size of a crystal grain by providing a step on the base. Here, the method will be described.
[0016]
FIG. 1A shows a first sample in the case where a step is provided in the base insulating film. In the first sample, a silicon nitride oxide film (A-type) is formed on a synthetic quartz glass substrate, and an amorphous silicon film having a thickness of 55 nm is formed on the silicon nitride oxide film (A-type). Yes. The silicon nitride oxide film (A-type) which is the base insulating film is provided with a step, and has a thin portion and a thick portion. Here, in this specification, a silicon nitride oxide film (A-type) is a silicon oxynitride film having a composition ratio of Si = 32%, O = 59%, N = 7%, and H = 2%. The silicon oxide film (B-type) is a silicon oxynitride film having a composition ratio of Si = 32%, O = 27%, N = 24%, and H = 17%. The first sample was irradiated with a laser beam from the surface side of the substrate, and a heat conduction analysis simulation was performed when the amorphous silicon film was crystallized. The result is shown in FIG. However, as conditions used for the calculation, the wavelength of the laser beam is 308 nm, and the irradiation energy is 400 mJ / cm. ² The pulse width (laser beam output time) was 30 ns, and the laser beam was irradiated in a vacuum. Other parameters used in the calculation are shown in Table 1.
[0017]
[Table 1]

[0018]
The result shown in FIG. 1B is obtained because a temperature gradient is generated by the base insulating film acting as a heat capacity. In the region B of FIG. 1A, there are both (1) the underlying insulating film directly below and (2) the underlying insulating film present in the lateral direction as places where heat escapes. Cooling. Conversely, in the C region, there is heat that escapes from the B region to the underlying insulating film immediately below the C region, and thus the temperature is unlikely to decrease. Therefore, a temperature gradient is generated between the B region and the C region or between the B region and the A region. When the temperature gradient is generated, crystal growth starts from the B region having a low temperature, and the solid-liquid interface moves to the C region or A region having a high temperature, so that crystal grains having a large grain size can be obtained.
[0019]
In other words, the structure used in a conventional TFT manufactured on a glass substrate, that is, the same structure as a structure in which a base insulating film is formed on a glass substrate and a semiconductor film is formed on the base insulating film, In Japanese Patent Application No. 11-35060, a step is provided by etching the base insulating film at a desired position. When such a sample is irradiated with a laser beam from the surface side of the substrate, a temperature distribution is generated inside the semiconductor film corresponding to the shape of the step of the base insulating film, and the location and direction of lateral growth are controlled. be able to.
[0020]
It is structurally possible to fabricate a top gate type TFT using a semiconductor film formed by the method of R. Ishihara et al. As an active layer. However, parasitic capacitance is generated by the silicon oxide film provided between the semiconductor film and the refractory metal film, so that power consumption increases and it is difficult to realize high-speed operation of the TFT. On the other hand, by using a refractory metal film as a gate electrode, it is considered that the present invention can be effectively applied to a bottom gate type or an inverted stagger type TFT. However, in a structure in which a silicon oxide film is formed on a substrate, a refractory metal film is formed on the silicon oxide film, and an amorphous silicon film is formed on the refractory metal film, the amorphous silicon film Even when excluding the film thickness, the film thickness of the refractory metal film and the silicon oxide film does not necessarily match the film thickness suitable for the crystallization process and the film thickness suitable for the electrical characteristics as the TFT element. Therefore, both the optimum design in the crystallization process and the optimum design of the element structure cannot be satisfied at the same time.
[0021]
In addition, if a refractory metal film having no translucency is formed on the entire surface of the glass substrate, it becomes impossible to manufacture a transmissive liquid crystal display device. Since the chromium (Cr) film and the titanium (Ti) film used as the refractory metal material have high internal stress, there is a high possibility that a problem occurs in adhesion to the glass substrate. Further, the influence of the internal stress extends to the semiconductor film formed in the upper layer, and it is highly likely that the internal stress acts as a force that distorts the formed crystalline semiconductor film.
[0022]
On the other hand, in order to control the threshold voltage (hereinafter referred to as Vth), which is an important parameter in the TFT, within a predetermined range, in addition to controlling the valence electrons in the channel formation region, the insulating film is closely connected to the active layer Therefore, it is necessary to reduce the density of charged defects in the base film and the gate insulating film formed in step (1) and to balance the internal stress. In response to such a demand, a material containing silicon as a constituent element, such as a silicon oxide film or a silicon oxynitride film, was suitable. Therefore, there is a concern that the provision of a refractory metal film between the substrate and the base film will break the balance.
[0023]
In addition, the SLS method requires precise control in units of microns in the relative positioning technique between the mask and the substrate, and becomes a complicated device as compared with a normal laser irradiation device. Further, there is a problem in throughput when used for manufacturing a TFT applied to a liquid crystal display having a large area.
[0024]
The present invention is a technique for solving these problems. A crystalline semiconductor film in which the position and size of crystal grains are controlled is fabricated, and the crystalline semiconductor film is further used as a channel formation region of a TFT. By using it, a TFT capable of high-speed operation is realized. It is another object of the present invention to provide a technique in which such TFT can be applied to various semiconductor devices such as a transmissive liquid crystal display device and a display device using an electroluminescent material.
[0025]
[Means for Solving the Problems]
A silicon nitride film is formed on a synthetic quartz glass substrate, a silicon nitride oxide film (A-type) is formed on the silicon nitride film, and an amorphous film having a thickness of 55 nm is formed on the silicon nitride oxide film (A-type). A simulation is performed using the second sample for forming the porous silicon film. FIGS. 2 to 3 show the results obtained by irradiating the second sample with a laser beam from the back side of the substrate and calculating the reflectance of the laser beam with respect to the amorphous silicon film. 2A shows a calculation result depending on the thickness of the silicon nitride oxide film (A-type) when the thickness of the silicon nitride film is fixed to 50 nm, and FIG. 2B shows the calculation result of the silicon nitride oxide film (A−). (type) shows the calculation result depending on the film thickness of the silicon nitride film when the film thickness is fixed to 100 nm. When performing the calculation, the wavelength of the laser beam was 308 nm, and the other parameters shown in Table 1 were used.
[0026]
As shown in FIG. 2A, the reflectance with respect to the amorphous silicon film changes periodically by changing the film thickness of the silicon nitride oxide film (A-type) even with the same laser beam irradiation energy. I understand that. Further, FIG. 2B shows that the reflectance with respect to the amorphous silicon film changes periodically by changing the film thickness of the silicon nitride film even with the same laser beam irradiation energy. .
[0027]
Next, FIG. 3 shows the result of calculation for the second sample with the wavelength of the laser beam set to 532 nm. 3A shows a calculation result depending on the thickness of the silicon nitride oxide film (A-type) when the thickness of the silicon nitride film is fixed to 50 nm, and FIG. 3B shows the silicon nitride oxide film (A -Type) shows a calculation result depending on the film thickness of the silicon nitride film when the film thickness is fixed to 100 nm. Table 2 shows the parameters used for the calculation.
[0028]
[Table 2]

[0029]
As shown in FIG. 3A, the reflectance with respect to the amorphous silicon film changes periodically by changing the film thickness of the silicon nitride oxide film (A-type) even with the same laser beam irradiation energy. I understand that. Further, FIG. 3B shows that the reflectance with respect to the amorphous silicon film is periodically changed by changing the film thickness of the silicon nitride film.
[0030]
That is, when the laser beam is irradiated from the back side of the substrate, the amorphous silicon film is changed by changing the film thickness of at least one of the base insulating films having a different refractive index. It can be seen that the effective irradiation intensity of the laser beam can be changed. Further, it can be seen that the periodic change of the reflectance with respect to the amorphous silicon film appears even if the wavelength of the laser beam is changed. However, the change period of the reflectance varies depending on the wavelength of the laser beam, the thickness of the base insulating film, and the like.
[0031]
Next, a lower silicon nitride oxide film is formed on the synthetic quartz glass substrate, a 100 nm-thick silicon nitride oxide film (A-type) is formed on the lower silicon nitride oxide film, and the silicon nitride oxide film (A A simulation is performed using a third sample that forms an amorphous silicon film having a thickness of 55 nm on -type). Note that the lower silicon nitride oxide film is used for differentiation from the silicon nitride oxide film (A-type) and the silicon nitride oxide film (B-type). In this simulation, the composition ratio of the lower silicon nitride oxide film is used. By changing the refractive index of the lower silicon nitride oxide film. FIG. 10A shows the reflectance with respect to the amorphous silicon film when such a third sample is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate. FIG. 10A shows that the reflectance with respect to the amorphous silicon film also changes as the refractive index of the lower silicon nitride oxide film changes.
[0032]
On the other hand, a silicon nitride oxide film (A-type) having a thickness of 100 nm is formed on a synthetic quartz glass substrate, and an amorphous silicon film having a thickness of 55 nm is formed on the silicon nitride oxide film (A-type). When the sample 4 is irradiated with a laser beam having a wavelength of 308 nm, the reflectance of the amorphous semiconductor film is 42.5% when the film thickness of the silicon nitride film in FIG. I understand that there is. That is, when the ratio of nitrogen in the composition ratio of the lower silicon nitride oxide film is increased and the film quality of the lower silicon nitride oxide film is brought closer to the silicon nitride oxide film (A-type), the reflection of the laser beam with respect to the amorphous silicon film The rate is approximately the same as when the base insulating film is a stacked layer of a lower silicon nitride oxide film and a silicon nitride oxide film (A-type) and when only the silicon nitride oxide film (A-type) is used. In other words, even if a base insulating film having a refractive index close to one another is stacked and a step is provided in one of the base insulating films to increase the thickness, the intensity distribution of the laser beam in the semiconductor film does not occur and the stacking is performed. You can see that there is not much meaning.
[0033]
Subsequently, a third sample is irradiated with a laser beam having a wavelength of 532 nm from the back side of the substrate, and the composition ratio of the lower layer silicon nitride oxide film is changed to change the refractive index of the lower layer silicon nitride oxide film. The reflectance with respect to the porous silicon film is changed. The result is shown in FIG. On the other hand, the reflectance of the amorphous semiconductor film when the fourth sample is irradiated with a laser beam having a wavelength of 532 nm is 10% when the film thickness of the silicon nitride film in FIG. I understand that there is. Even in the case of a laser beam having a wavelength of 532 nm, if the composition ratio of the lower silicon nitride oxide film is changed to bring the film quality of the lower silicon nitride oxide film closer to the silicon nitride oxide film (A-type), the amorphous silicon film The reflectance is approximately the same as when the base insulating film is a stacked layer of a lower silicon nitride oxide film and a silicon nitride oxide film (A-type) and when only the silicon nitride oxide film (A-type) is used. That is, even when a laser beam having a wavelength of 532 nm is used, even if a base insulating film having a close refractive index is stacked and a step is provided in one layer of the base insulating film, It can be seen that the effective intensity distribution of the laser beam does not occur in the porous silicon film, and that there is not much meaning in stacking.
[0034]
Further, from Table 2, the refractive index of the silicon nitride oxide film (A-type), the Corning 1737 substrate, and the synthetic quartz glass substrate with respect to the wavelength of 532 nm are approximately the same. Therefore, a 1737 glass substrate or a synthetic quartz glass substrate is used as a substrate, a silicon nitride oxide film (A-type) having a step is provided on the substrate to form a stepped film thickness, and the silicon nitride oxide film (A An amorphous silicon film is formed on (type), and a laser beam is irradiated from the back side of the substrate. However, since the unevenness on the surface of the substrate is rougher than the step provided on the silicon nitride oxide film (A-type), the amorphous silicon film is not affected even when the laser beam is irradiated from the back side of the substrate. In this case, an effective laser beam intensity distribution hardly occurs. In other words, for the wavelength of the laser beam to be used, the base insulating film formed on the substrate is meaningless at the same refractive index as that of the substrate, and needs to have a refractive index different from that of the substrate. I understand.
[0035]
As described above, the reflectance with respect to the amorphous semiconductor film changes due to the interference effect of the thin films of the plurality of stacked base insulating films, and a combination of the film thickness and the refractive index of the plurality of stacked base insulating films. Thus, an arbitrary laser beam intensity distribution can be obtained. From the above, the present invention uses a plurality of base insulating films, and at least one layer of the plurality of base insulating films is provided with a step so that the film thickness is increased, and the grain size is increased. It is possible to form a crystalline semiconductor film having position-controlled crystal grains. Note that at least two types of insulating films having different refractive indexes are used for the plurality of base insulating films, and laser beam irradiation is performed from the back side of the substrate or from both the front side and the back side of the substrate.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
This embodiment will be described with reference to FIG. In FIG. 4A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used for the substrate 1001. For example, Corning 7059 glass or 1737 glass can be suitably used.
[0037]
A first base insulating film 1002 is formed on the substrate 1001 by a known means (LPCVD method, plasma CVD method, etc.), a silicon nitride film, a silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%). In this embodiment, a silicon nitride film is formed to a thickness of 50 nm using a plasma CVD method.
[0038]
A second base insulating film 1003 having a refractive index different from that of the first base insulating film 1002 is formed thereon by a known means (LPCVD method, plasma CVD method, or the like) using a silicon oxide film, a silicon oxynitride film, or the like. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed in a thickness of 130 to 150 nm by using a plasma CVD method.
[0039]
After the second base insulating film 1003 is formed, a resist mask is formed using a photolithography technique, and unnecessary portions are etched to form a third portion having a thickness of 130 to 150 nm and a thickness of 78 to 98 nm. A base insulating film 1004 is obtained (FIG. 4B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0040]
The reason why the third base insulating film 1004 has a two-stage film thickness is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2A, the film thickness corresponding to the maximum value of 62.5% of the reflectance for the amorphous silicon film periodically appearing is 130 to 150 nm, and the minimum value for the amorphous silicon film is 22.7. The film thickness corresponding to about% is 78 to 98 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, it is desirable that the difference in film thickness in two steps of the third base insulating film 1004 is smaller than the film thickness of the amorphous semiconductor film to be formed later. Further, the side wall angle at the step of the second base insulating film 1004 is 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and is etched into a tapered shape. It is desirable to ensure step coverage of the film to be laminated.
[0041]
The amorphous semiconductor film 1005 shown in FIG. 4B is formed into a third base insulation having a step with a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known method such as a plasma CVD method or a sputtering method. It is formed along the film 1004. In this embodiment, an amorphous silicon film is formed with a film thickness of 55 nm. However, as the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0042]
FIG. 4C illustrates a crystallization process in which a laser beam is irradiated from the back side, and FIG. 4D illustrates a crystallization process in which the laser beam is irradiated from both the front side and the back side of the substrate. It is a figure to do. In the present invention, any method is used. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0043]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0044]
Using one of the laser oscillators described above, the amorphous semiconductor film is crystallized by any one of the irradiation methods shown in FIGS. As already described, since the thickness of the third base insulating film 1004 is in two stages, the reflectance of the laser beam with respect to the amorphous semiconductor film 1005 when irradiated with a laser beam from the back surface side. Is about 22.7% in region A and about 62.5% in region B, and the effective intensity of the laser beam is different.
[0045]
Further, the step edge (the boundary between the region A and the region B) in the third base insulating film 1004 of FIG. 4C or FIG. 4D is used as a place for heat to escape from the base insulating film immediately below (1). {Circle around (2)} Since both of the underlying insulating films exist in the horizontal direction, it cools faster than other places. For this reason, solidification starts from the semiconductor film on the step end in the second base insulating film whose temperature first falls, and crystal nuclei 1006 are generated. This crystal nucleus becomes the center of crystal growth, and the crystal growth proceeds toward the region A or the region B in a molten state at a high temperature. However, since the region A has a higher absorption rate of the laser beam than the region B, the crystal nucleus grows in the direction indicated by 1007, so that a crystal grain having a larger grain size is formed in the semiconductor film in the region A. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed. (Fig. 4 (e))
[0046]
After irradiation with the laser beam, the crystalline semiconductor film is heated at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. The remaining defects can be neutralized by the heat treatment. By manufacturing the TFT using the region A of the crystalline semiconductor film thus manufactured as a channel formation region, the electrical characteristics of the TFT can be improved.
[0047]
[Embodiment 2]
This embodiment will be described with reference to FIG. In FIG. 5A, a non-alkali glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used as the substrate 1001. For example, Corning 7059 glass or 1737 glass can be suitably used.
[0048]
A first base insulating film 1009 is formed on the substrate 1001 by a known means (LPCVD method, plasma CVD method, etc.), a silicon nitride film, a silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%). In the present embodiment, a silicon nitride film is formed with a thickness of 55 to 85 nm using a plasma CVD method.
[0049]
After the first base insulating film 1009 is formed, a resist mask is formed using a photolithography technique, unnecessary portions are etched, and a second portion having a thickness of 55 to 85 nm and a portion of 25 to 45 nm is formed. A base insulating film 1010 is obtained (FIG. 5B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0050]
A third base insulating film 1011 having a refractive index different from that of the second base insulating film 1010 is formed using a silicon oxide film, a silicon oxynitride film, or the like by a known means (LPCVD method, plasma CVD method, or the like). . In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to 100 nm by using plasma CVD.
[0051]
The reason why the second base insulating film 1010 is formed in two stages is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2B, the film thickness corresponding to the maximum value of 42.5% for the amorphous silicon film periodically appearing is 55 to 85 nm, and the minimum value for the amorphous silicon film is about 20%. Is equivalent to 25 to 45 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, the difference in film thickness between the two steps of the second base insulating film 1010 is preferably smaller than the film thickness of the amorphous semiconductor film to be formed later. In addition, the side wall angle at the step of the second base insulating film 1010 is 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and is etched into a tapered shape. It is desirable to ensure step coverage of the film to be laminated.
[0052]
The amorphous semiconductor film 1012 shown in FIG. 5B is formed along the third base insulating film 1011 to a thickness of 25 to 200 nm (preferably 30 to 100 nm) by a known method such as a plasma CVD method or a sputtering method. Form. In this embodiment, an amorphous silicon film is formed to 55 nm. However, as the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0053]
FIG. 5C is a diagram for explaining a crystallization process for irradiating a laser beam from the back surface side, and FIG. 5D illustrates a crystallization process for irradiating a laser beam from both the front surface side and the back surface side of the substrate. It is a figure to do. In the present invention, any method is used. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0054]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0055]
Using one of the laser oscillators described above, the amorphous semiconductor film is crystallized by the irradiation method of either FIG. 5C or 5D. As described above, since the thickness of the second base insulating film 1010 has two stages, the reflectance of the laser beam with respect to the amorphous semiconductor film 1012 when irradiated with a laser beam from the back surface side. Is about 20% in the region A and about 42.5% in the region B, and the effective intensity of the laser beam is different.
[0056]
Further, the step edge (the boundary between the region A and the region B) in the second base insulating film 1010 in FIG. 5C or FIG. 5D is used as a place for heat to escape from the base insulating film immediately below (1). {Circle around (2)} Since both of the underlying insulating films exist in the horizontal direction, it cools faster than other places. For this reason, solidification starts from the semiconductor film on the step end in the second base insulating film whose temperature first falls, and crystal nuclei 1006 are generated. This crystal nucleus becomes the center of crystal growth, and the crystal growth proceeds toward the region A or the region B in a molten state at a high temperature. However, since the region A has a higher absorption rate of the laser beam than the region B, the crystal nucleus grows in the direction indicated by 1007, so that a crystal grain having a larger grain size is formed in the semiconductor film in the region A. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed. (Fig. 5 (e))
[0057]
After irradiation with the laser beam, the crystalline semiconductor film is heated at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. The remaining defects can be neutralized by the heat treatment. By manufacturing the TFT using the region A of the crystalline semiconductor film thus manufactured as a channel formation region, the electrical characteristics of the TFT can be improved.
[0058]
[Embodiment 3]
This embodiment will be described with reference to FIG. In FIG. 6A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used for the substrate 1001. For example, Corning 7059 glass or 1737 glass can be suitably used.
[0059]
A first base insulating film 1016 is formed on the substrate 1001 by a known means (LPCVD method, plasma CVD method, etc.), a silicon nitride film, a silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%). In this embodiment, a silicon nitride film is formed to a thickness of 50 nm using a plasma CVD method.
[0060]
On this, a second base insulating film 1017 having a refractive index different from that of the first base insulating film 1016 is formed of a silicon oxide film, a silicon oxynitride film, or the like by a known means (LPCVD method, plasma CVD method or the like). . In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to 78 to 98 nm using plasma CVD.
[0061]
After the second base insulating film 1017 is formed, a resist mask is formed using a photolithography technique, unnecessary portions are etched, and a third portion having a thickness of 25 to 45 nm and a portion of 78 to 98 nm is formed. A base insulating film 1018 is obtained (FIG. 6B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0062]
The reason why the third base insulating film 1018 has a two-stage film thickness is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2A, the film thickness corresponding to the maximum value of 62.5% of the reflectance for the amorphous silicon film periodically appearing is 25 to 45 nm, and the minimum value for the amorphous silicon film is 22.7. The film thickness corresponding to about% is 78 to 98 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, it is preferable that the difference in film thickness in two steps of the third base insulating film 1018 is smaller than the film thickness of the amorphous semiconductor film to be formed later. In addition, the side wall angle at the step of the third base insulating film 1018 is tapered to be 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and the upper side thereof. It is desirable to ensure step coverage of the film to be laminated.
[0063]
A third base insulating film having a step with a thickness of 25 to 200 nm (preferably 30 to 100 nm) is formed on the amorphous semiconductor film 1019 shown in FIG. 6B by a known method such as plasma CVD or sputtering. It is formed along the film 1018. In this embodiment, an amorphous silicon film is formed to 55 nm. However, as the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0064]
FIG. 6C is a diagram for explaining a crystallization process for irradiating a laser beam from the back surface side, and FIG. 6D illustrates a crystallization process for irradiating a laser beam from both the front surface side and the back surface side of the substrate. It is a figure to do. In the present invention, any method is used. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0065]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0066]
Using one of the laser oscillators described above, the amorphous semiconductor film is crystallized by one of the irradiation methods shown in FIGS. As already described, since the thickness of the third base insulating film 1018 is in two stages, the reflectance of the laser beam with respect to the amorphous semiconductor film 1019 when irradiated with a laser beam from the back surface side. Is about 22.7% in region A and about 62.5% in region B, and the effective intensity of the laser beam is different.
[0067]
Further, the step edge (the boundary between the region A and the region B) in the third base insulating film 1018 of FIG. 6C or FIG. 6D is used as a place for heat to escape from the base insulating film immediately below (1). {Circle around (2)} Since both of the underlying insulating films exist in the horizontal direction, it cools faster than other places. For this reason, solidification starts from the semiconductor film on the step end in the third base insulating film whose temperature first falls, and crystal nuclei 1006 are generated. This crystal nucleus becomes the center of crystal growth, and the crystal growth proceeds toward the region A or the region B in a molten state at a high temperature. However, since the region A has a higher absorption rate of the laser beam than the region B, the crystal nucleus grows in the direction indicated by 1007, so that a crystal grain having a larger grain size is formed in the semiconductor film in the region A. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed. (Fig. 6 (e))
[0068]
After irradiation with the laser beam, the crystalline semiconductor film is heated at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. The remaining defects can be neutralized by the heat treatment. By manufacturing the TFT using the region A of the crystalline semiconductor film thus manufactured as a channel formation region, the electrical characteristics of the TFT can be improved.
[0069]
【Example】
[Example 1]
Here, the simulation result of this invention is demonstrated using FIGS.
[0070]
In FIG. 7A, a non-alkali glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used for the substrate 1001. In this embodiment, a synthetic quartz glass substrate is used.
[0071]
A first base insulating film 1023 is formed of a silicon nitride film, a silicon oxynitride film, or the like on the substrate 1001 by a known means (LPCVD method, plasma CVD method, or the like). In this embodiment, a silicon nitride film is formed to a thickness of 50 nm using a plasma CVD method.
[0072]
A second base insulating film 1024 having a refractive index different from that of the first base insulating film is formed on the first base insulating film 1023 by a known means (LPCVD method, plasma CVD method, or the like) using a silicon oxynitride film or the like. Form. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to 140 nm by plasma CVD.
[0073]
After the second base insulating film 1024 is formed, a resist mask is formed using a photolithography technique, and unnecessary portions are etched to form a third base insulating film having a 140 nm portion and a 88 nm portion. 1025 is obtained (FIG. 7B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0074]
The reason why the third base insulating film 1025 has a two-stage film thickness is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2A, the film thickness corresponding to the maximum value of 62.5% for the amorphous silicon film periodically appearing is 140 nm, which corresponds to the minimum value of 22.7% for the amorphous silicon film. The film thickness is 88 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, it is desirable that the difference in film thickness in two stages of the third base insulating film 1025 is smaller than the film thickness of a semiconductor film to be formed later. In addition, the side wall angle at the step of the third base insulating film 1025 is 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and is etched into a tapered shape. Step coverage of the film to be laminated is ensured.
[0075]
A third base insulating film having a step with a thickness of 25 to 200 nm (preferably 30 to 100 nm) is formed on the amorphous semiconductor film 1026 shown in FIG. 7B by a known method such as plasma CVD or sputtering. 1025 is formed. In this embodiment, a plasma CVD method is used to form an amorphous silicon film with a thickness of 50 nm. As the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0076]
FIG. 7C is a diagram for explaining a crystallization process in which a laser beam is irradiated from the back side. In the present invention, either the irradiation from the back surface side of the substrate or the irradiation from both the front surface side and the back surface side of the substrate is used. In this embodiment, the irradiation was performed from the back surface side of the substrate. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0077]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0078]
In this embodiment, the amorphous silicon film was crystallized by an irradiation method shown in FIG. 7C using an excimer laser (wavelength 308 nm, pulse width 30 ns). As already described, since the thickness of the third base insulating film 1025 has two stages, when the laser beam is irradiated from the back surface side, the reflectance of the laser beam with respect to the amorphous silicon film becomes a region. A is about 22.7%, and the region B is about 62.5%, and the effective intensity of the laser beam is different.
[0079]
Further, the step edge (the boundary between the region A and the region B) in the third base insulating film 1025 in FIG. 7C is a place where heat is released as (1) the base insulating film immediately below and (2) the lateral direction. Since both of the underlying insulating films are present, it cools faster than other places. Therefore, solidification starts from the step end of the third base insulating film 1025 where the temperature first decreases, and crystal nuclei 1006 are generated. This crystal nucleus becomes the center of crystal growth, and the crystal growth proceeds toward the region A or the region B in a molten state at a high temperature. However, since the region A has a higher absorption rate of the laser beam than the region B, the crystal nucleus grows in the direction indicated by 1007, so that a crystal grain having a larger grain size is formed in the semiconductor film in the region A. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed.
[0080]
For comparison, for a sample in which a silicon nitride oxide film (A-type) is formed on a synthetic quartz glass substrate and an amorphous silicon film having a thickness of 55 nm is formed on the silicon nitride oxide film (A-type). FIG. 8 shows a comparison of the solid phase start time after simulation. However, the silicon nitride oxide film (A-type) has two thicknesses of 88 nm and 140 nm as already described in this embodiment. FIG. 8 shows the relationship between the distance from the base step edge (the boundary between the region A and the region B in FIG. 7C) to the region A and the solid phase start time. From FIG. 8, even if a base film having a step is used, the solidification of the semiconductor film after laser beam irradiation proceeds more slowly in the crystallization in the configuration of the present invention than in the case where the base film is a single layer. Therefore, it can be seen that large crystal grains can be obtained.
[0081]
After irradiation with the laser beam, the crystalline semiconductor film is heated at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. The remaining defects can be neutralized by the heat treatment. By manufacturing the TFT using the region A of the crystalline semiconductor film thus manufactured as a channel formation region, the electrical characteristics of the TFT can be improved.
[0082]
[Example 2]
Here, a method of performing laser annealing after using the structure of the present invention to partially crystallize an amorphous silicon film by heat treatment will be described. In FIG. 9A, a non-alkali glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used as the substrate 1001. In this embodiment, a synthetic quartz glass substrate is used.
[0083]
A first base insulating film 1028 is formed on the substrate 1001 by a known means (LPCVD method, plasma CVD method, or the like) using a silicon nitride film, a silicon oxynitride film, or the like. In this embodiment, a silicon nitride film is formed to a thickness of 50 nm using a plasma CVD method.
[0084]
On this, a second base insulating film 1029 having a refractive index different from that of the first base insulating film 1028 is formed using a silicon oxynitride film or the like by a known means (LPCVD method, plasma CVD method, or the like). In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to 140 nm by plasma CVD.
[0085]
After the second base insulating film 1029 is formed, a resist mask is formed by using a photolithography technique, unnecessary portions are etched, and a third base insulating film having a thickness of 140 nm and a thickness of 88 nm 1030 is obtained (FIG. 9B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0086]
The reason why the third base insulating film 1030 has a two-stage film thickness is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2A, the film thickness corresponding to the maximum value of 62.5% for the amorphous silicon film periodically appearing is 140 nm, which corresponds to the minimum value of 22.7% for the amorphous silicon film. The film thickness is 88 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, it is desirable that the difference in film thickness in two steps of the third base insulating film 1030 is smaller than the film thickness of a semiconductor film to be formed later. In addition, the side wall angle in the step of the third base insulating film 1030 is 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and is etched into a tapered shape. Step coverage of the film to be laminated is ensured.
[0087]
A third base insulating film having a step with a thickness of 25 to 200 nm (preferably 30 to 100 nm) is formed on the amorphous semiconductor film 1031 shown in FIG. 9B by a known method such as plasma CVD or sputtering. 1030 is formed. In this embodiment, a plasma CVD method is used to form an amorphous silicon film with a thickness of 50 nm. As the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0088]
Next, the amorphous silicon film is partially crystallized by the method described in JP-A-7-183540. Here, the method will be briefly described. First, a trace amount of an element such as nickel, palladium, or lead is added to the amorphous semiconductor film. As the addition method, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. After the addition, for example, when an amorphous semiconductor film is placed in a nitrogen atmosphere at 550 ° C. for 4 hours, a crystalline semiconductor film with good electrical characteristics can be obtained. The optimum heating temperature, heating time, etc. for crystallization depend on the amount of the element added and the state of the amorphous semiconductor film. For example, when the solution coating method is applied and a nickel acetate solution is used as the solution, 5 ml of a 10 ppm concentration by weight conversion is applied to the entire surface of the film by spin coating to form the metal-containing layer 1032. (FIG. 9B) Next, the substrate was partially crystallized by heating in a nitrogen atmosphere at a temperature of 500 ° C. for 1 hour and further continuously in a nitrogen atmosphere at a temperature of 550 ° C. for 4 hours. A first crystalline silicon film 1033 is obtained. (Fig. 9 (c))
[0089]
FIG. 9D is a diagram for explaining a crystallization process in which a laser beam is irradiated from the back side. In the present invention, either the irradiation from the back surface side of the substrate or the irradiation from both the front surface side and the back surface side of the substrate is used. In this embodiment, the irradiation was performed from the back surface side of the substrate. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0090]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0091]
In this embodiment, the amorphous silicon film was crystallized by using the excimer laser (wavelength 308 nm, pulse width 30 ns) by the irradiation method shown in FIG. As already described, since the film thickness of the third base insulating film 1030 has two stages, when the laser beam is irradiated from the back surface side, the reflectance of the laser beam in the region A is 22.7%. In the region B, it is about 62.5%, and the effective intensity of the laser beam with respect to the first crystalline silicon film 1033 is different.
[0092]
Further, the step edge (the boundary between the region A and the region B) in the third base insulating film 1030 in FIG. 9D is a place where heat is released as (1) the base insulating film immediately below and (2) the lateral direction. Since both of the underlying insulating films are present, it cools faster than other places. Therefore, the solidification of the semiconductor film starts from the step end in the third base insulating film 1030 where the temperature first decreases, and crystal nuclei 1006 are generated. This crystal nucleus becomes the center of crystal growth, and the crystal growth proceeds toward the region A or the region B in a molten state at a high temperature. However, since the region A has a higher absorption rate of the laser beam than the region B, the crystal nucleus grows in the direction indicated by 1007, so that a crystal grain having a larger grain size is formed in the semiconductor film in the region A. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed.
[0093]
After irradiation with the laser beam, the crystalline semiconductor film is heated at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. The remaining defects can be neutralized by the heat treatment. By manufacturing the TFT using the region A of the crystalline semiconductor film thus manufactured as a channel formation region, the electrical characteristics of the TFT can be improved.
[0094]
[Example 3]
Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail with reference to FIGS. .
[0095]
In FIG. 11A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass or a synthetic quartz glass substrate is used for the substrate 1001. In this embodiment, a synthetic quartz glass substrate is used.
[0096]
A first base insulating film 100a is formed on the substrate 1001 by a known means (LPCVD method, plasma CVD method, etc.) using a silicon nitride film, a silicon oxynitride film, or the like. In this embodiment, a silicon nitride film is formed to a thickness of 50 nm using a plasma CVD method.
[0097]
On this, a second base insulating film 100b having a refractive index different from that of the first base insulating film is formed of a silicon oxynitride film or the like by a known means (LPCVD method, plasma CVD method or the like). In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is formed to 140 nm by plasma CVD.
[0098]
After the second base insulating film is formed, a resist mask is formed by using a photolithography technique, and unnecessary portions are etched to form a third base insulating film 100c having a thickness of 140 nm and a thickness of 88 nm. Is obtained (FIG. 11B). For the etching, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the wet etching method is selected, for example, ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) may be etched with a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa).
[0099]
The reason why the third base insulating film 100c is formed in two stages is to form an effective intensity distribution of the laser beam with respect to the semiconductor film. In FIG. 2A, the film thickness corresponding to the maximum value of 62.5% for the amorphous silicon film periodically appearing is 140 nm, which corresponds to the minimum value of 22.7% for the amorphous silicon film. The film thickness is 88 nm. As already described, since the reflectance for the amorphous silicon film has periodicity, if the film thickness corresponds to about the maximum value and the minimum value of the reflectance for the amorphous silicon film, It is not restricted to the above-mentioned film thickness. However, it is desirable that the difference in film thickness between the two steps of the third base insulating film 100b is smaller than the film thickness of the semiconductor film to be formed later. In addition, the side wall angle at the step of the third base insulating film 100b is 5 ° or more and less than 85 ° (preferably 30 ° to 60 °) with respect to the substrate 1001, and is etched into a tapered shape. Step coverage of the film to be laminated is ensured.
[0100]
A third base insulating film having a step with a thickness of 25 to 200 nm (preferably 30 to 100 nm) is formed on the amorphous semiconductor film 101 shown in FIG. 11C by a known method such as plasma CVD or sputtering. It is formed along 100c. In this embodiment, a plasma CVD method is used to form an amorphous silicon film with a thickness of 50 nm. As the amorphous semiconductor film, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0101]
FIG. 11C is a diagram illustrating a crystallization process in which a laser beam is irradiated from the back side. In the present invention, either the irradiation from the back surface side of the substrate or the irradiation from both the front surface side and the back surface side of the substrate is used. In this embodiment, the irradiation was performed from the back surface side of the substrate. In the crystallization by the laser annealing method, it is desirable to first release the hydrogen contained in the amorphous semiconductor film. The hydrogen content is reduced to 5 atom% or less by exposing it to a nitrogen atmosphere at 400 to 500 ° C. for about 1 hour. It is good to keep. This significantly improves the laser resistance of the film.
[0102]
A laser oscillator used in the laser annealing method will be described. Excimer lasers are widely used because they have a large output and can oscillate a high repetition pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used.
[0103]
In this embodiment, the amorphous silicon film was crystallized by an irradiation method shown in FIG. 11C using an excimer laser (wavelength 308 nm, pulse width 30 ns). As described above, since the thickness of the third base insulating film 100c is two steps, when the laser beam is irradiated from the back side, the reflectance of the laser beam with respect to the amorphous semiconductor film is a region. A is about 62.5%, and the region B is about 22.7%, and the effective intensity of the laser beam is different.
[0104]
Further, the step edge in the third base insulating film in FIG. 11C has both (1) the base insulating film immediately below and (2) the base insulating film present in the lateral direction as places where heat escapes. Cool faster than other places. For this reason, solidification starts from the semiconductor film on the step end in the third base insulating film 100c that first falls in temperature, and crystal nuclei are generated. This nucleus serves as the center of crystal growth, and crystal growth proceeds toward a region having a high temperature and a molten state. In this manner, a crystalline semiconductor film having a large grain size and position-controlled crystal grains can be formed.
[0105]
After the laser beam irradiation, the semiconductor layers 102 to 106 were formed by patterning the crystalline semiconductor film using a photolithography method.
[0106]
Further, after forming the semiconductor layers 102 to 106, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0107]
Next, a gate insulating film 107 that covers the semiconductor layers 102 to 106 is formed. The gate insulating film 107 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0108]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good electrical characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.
[0109]
Next, as illustrated in FIG. 11D, a first conductive film 108 with a thickness of 20 to 100 nm and a second conductive film 109 with a thickness of 100 to 400 nm are stacked over the gate insulating film 107. In this example, a first conductive film 408 made of a TaN film with a thickness of 30 nm and a second conductive film 109 made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, a sputtering method using a target of high purity W (purity 99.9999%) is used, and the W film is formed with sufficient consideration so that impurities are not mixed in from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.
[0110]
In this embodiment, the first conductive film 108 is TaN and the second conductive film 109 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0111]
Next, resist masks 110 to 115 are formed using a photolithography method, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ Each gas flow rate ratio was 25/25/10 (sccm), and 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0112]
Thereafter, the resist masks 110 to 115 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ Each gas flow ratio is set to 30/30 (sccm), and plasma is generated by applying 500 W RF (13.56 MHz) power to the coil type electrode at a pressure of 1 Pa, and etching is performed for about 30 seconds. Went. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0113]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 117 to 122 (first conductive layers 117 a to 122 a and second conductive layers 117 b to 122 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 116 denotes a gate insulating film, and a region that is not covered with the first shape conductive layers 117 to 122 is etched and thinned by about 20 to 50 nm.
[0114]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. (FIG. 12A) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ atoms / cm ² The acceleration voltage is set to 60 to 100 keV. In this embodiment, the dose is 1.5 × 10 ¹⁵ atoms / cm ² The acceleration voltage was 80 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 117 to 121 serve as a mask for the impurity element imparting n-type, and the high-concentration impurity regions 123 to 127 are formed in a self-aligning manner. The high concentration impurity regions 123 to 127 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0115]
Next, a second etching process is performed without removing the resist mask. Here, CF is used as an etching gas. _Four And Cl ₂ And O ₂ Then, the W film is selectively etched. At this time, the first conductive layers 128b to 133b are formed by the second etching process. On the other hand, the second conductive layers 117a to 122a are hardly etched, and the second conductive layers 128a to 133a are formed. Next, a second doping process is performed to obtain the state of FIG. Doping is performed using the second conductive layers 117a to 122a as masks against the impurity element so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. Thus, impurity regions 134 to 138 overlapping with the first conductive layer are formed. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Note that in the semiconductor layer overlapping the tapered portion of the first conductive layer, the impurity concentration is slightly lower from the end of the tapered portion of the first conductive layer to the inside, but the concentration is almost the same. . An impurity element is also added to the first impurity regions 123 to 127 to form impurity regions 139 to 143.
[0116]
Next, a third etching process is performed without removing the resist mask. In the third etching process, the tapered portion of the first conductive layer is partially etched to reduce a region overlapping with the semiconductor layer. In the third etching, CHF is used as an etching gas. _Three And using a reactive ion etching method (RIE method). First conductive layers 144 to 149 are formed by the third etching. At this time, the insulating film 116 is also etched to form insulating films 150a to 150e and 151.
[0117]
By the third etching, impurity regions (LDD regions) 134a to 138a that do not overlap with the first conductive layers 144 to 148 are formed. Note that the impurity regions (GOLD regions) 134b to 138b remain overlapped with the first conductive layers 144 to 148.
[0118]
Thus, in this embodiment, the impurity concentration in the impurity regions (GOLD regions) 134b to 138b that overlap with the first conductive layers 144 to 148 and the impurity region that does not overlap with the first conductive layers 144 to 148 ( The difference from the impurity concentration in the LDD regions 134a to 138a can be reduced, and the reliability can be improved.
[0119]
Next, after removing the resist mask, new resist masks 152 to 154 are formed, and a third doping process is performed. By this third doping treatment, impurity regions 155 to 160 are formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes the active layer of the p-channel TFT. The second conductive layers 128a to 132a are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity regions 155 to 160 are diborane (B ₂ H ₆ ) Using an ion doping method. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 152 to 154 made of resist.
By the first doping process and the second doping process, phosphorus is added to the impurity regions 155 to 160 at different concentrations, and the concentration of the impurity element imparting p-type in each of the regions is 2 ×. 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added.
[0120]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0121]
Next, the resist masks 152 to 154 are removed, and a first interlayer insulating film 161 is formed. The first interlayer insulating film 161 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 161 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0122]
Next, as shown in FIG. 13B, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0123]
In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered to impurity regions 139, 141, 142, 155, and 158 containing high-concentration phosphorus, and mainly the channel. The nickel concentration in the semiconductor layer that becomes the formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-state current value and good crystallinity, so that high field-effect mobility can be obtained and good electrical characteristics can be achieved.
[0124]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring as in this embodiment. It is preferable to perform the conversion process.
[0125]
Furthermore, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0126]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after the hydrogenation.
[0127]
Next, a second interlayer insulating film 162 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 161. In this example, an acrylic resin film having a film thickness of 1.6 μm was formed, but a film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp, and having an uneven surface formed. Alternatively, a film whose surface is planarized may be used as the second interlayer insulating film 162.
[0128]
In this embodiment, in order to prevent specular reflection, the surface of the pixel electrode is formed with the unevenness by forming the second interlayer insulating film having the unevenness on the surface. In addition, a convex portion may be formed in a region below the pixel electrode in order to make the surface of the pixel electrode uneven to achieve light scattering. In that case, since the convex portion can be formed using the same photomask as that of the TFT, the convex portion can be formed without increasing the number of steps. In addition, this convex part should just be suitably provided on the board | substrate of pixel part area | regions other than wiring and a TFT part. Thus, irregularities are formed on the surface of the pixel electrode along the irregularities formed on the surface of the insulating film covering the convex portions.
[0129]
Then, wirings 163 to 167 that are electrically connected to the respective impurity regions are formed in the driver circuit. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
[0130]
In the pixel portion, a pixel electrode 170, a gate wiring 169, and a connection electrode 168 are formed. (FIG. 13C) With this connection electrode 168, the source wiring (lamination of 143b and 149) is electrically connected to the pixel TFT. The gate wiring 169 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 170 is electrically connected to the drain region of the pixel TFT, and is further electrically connected to the semiconductor layer 158 functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 170, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.
[0131]
As described above, a CMOS circuit including an n-channel TFT 501 and a p-channel TFT 502, a driver circuit 506 having an n-channel TFT 503, and a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.
[0132]
The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 171, a low concentration impurity region 134 b (GOLD region) that overlaps with the first conductive layer 144 that forms part of the gate electrode, and a low concentration formed outside the gate electrode. An impurity region 134a (LDD region) and a high concentration impurity region 139 functioning as a source region or a drain region are provided. The p-channel TFT 502, which is connected to the n-channel TFT 501 and the electrode 166 to form a CMOS circuit, has a channel formation region 172, an impurity region 157 overlapping with the gate electrode, an impurity region 156 formed outside the gate electrode, and a source region Alternatively, the high-concentration impurity region 155 functioning as a drain region is provided. The n-channel TFT 503 includes a channel formation region 173, a low concentration impurity region 136b (GOLD region) overlapping with the first conductive layer 146 that forms part of the gate electrode, and a low concentration impurity formed outside the gate electrode. A region 137a (LDD region) and a high concentration impurity region 141 functioning as a source region or a drain region are provided.
[0133]
The pixel TFT 504 in the pixel portion includes a channel formation region 174, a low concentration impurity region 137 b (GOLD region) that overlaps with the first conductive layer 147 that forms part of the gate electrode, and a low concentration impurity region formed outside the gate electrode. 137a (LDD region) and a high concentration impurity region 142 functioning as a source region or a drain region. In addition, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 158 to 160 functioning as one electrode of the storage capacitor 505. The storage capacitor 505 is formed of an electrode (stack of 148 and 132b) and semiconductor layers 158 to 160 using the insulating film 151 as a dielectric.
[0134]
In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.
[0135]
A top view of a pixel portion of an active matrix substrate manufactured in this embodiment is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIGS. 11-13. A chain line AA ′ in FIG. 13 corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. 13 corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.
[0136]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing the active matrix substrate can be five. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0137]
[Example 4]
In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below. FIG. 15 is used for the description.
[0138]
First, after obtaining an active matrix substrate in the state of FIG. 13C according to the third embodiment, an alignment film 470 is formed on at least the pixel electrode 170 on the active matrix substrate of FIG. . In this embodiment, before forming the alignment film 470, columnar spacers (not shown) for holding the substrate interval are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0139]
Next, a counter substrate 471 is prepared. Next, colored layers 472 and 473 and a planarization film 474 are formed over the counter substrate 471. The red colored layer 472 and the blue colored layer 473 are overlapped to form a light shielding portion. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.
[0140]
In this embodiment, the substrate shown in Embodiment 3 is used. Therefore, in FIG. 14 showing a top view of the pixel portion of Example 3, at least the gap between the gate wiring 169 and the pixel electrode 170, the gap between the gate wiring 169 and the connection electrode 168, and the gap between the connection electrode 168 and the pixel electrode 170 are shown. It is necessary to shield the light. In this example, the respective colored layers were arranged so that the light-shielding portions formed by the lamination of the colored layers overlapped at the positions where light shielding should be performed, and the counter substrate was bonded.
[0141]
As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.
[0142]
Next, a counter electrode 475 made of a transparent conductive film was formed over the planarization film 474 in at least the pixel portion, an alignment film 476 was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0143]
Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 477. A filler is mixed in the sealing material 477, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 478 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 478. In this way, the reflection type liquid crystal display device shown in FIG. 15 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.
[0144]
The liquid crystal display panel manufactured as described above can be used as a display portion of various electronic devices.
[0145]
[Example 5]
The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EC display, active matrix EL display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.
[0146]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). Examples of these are shown in FIGS. 16, 17 and 18.
[0147]
FIG. 16A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. The present invention can be applied to the image input unit 3002, the display unit 3003, and other signal control circuits.
[0148]
FIG. 16B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. The present invention can be applied to the display portion 3102 and other signal control circuits.
[0149]
FIG. 16C illustrates a mobile computer, which includes a main body 3201, a camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205 and other signal control circuits.
[0150]
FIG. 16D illustrates a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302 and other signal control circuits.
[0151]
FIG. 16E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet. The present invention can be applied to the display portion 3402 and other signal control circuits.
[0152]
FIG. 16F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 3502 and other signal control circuits.
[0153]
FIG. 17A illustrates a front type projector, which includes a projection device 3601, a screen 3602, and the like. The present invention can be applied to a liquid crystal display device 3808 constituting a part of the projection device 3601 and other signal control circuits.
[0154]
FIG. 17B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 3702 and other signal control circuits.
[0155]
Note that FIG. 17C illustrates an example of the structure of the projection devices 3601 and 3702 in FIGS. 17A and 17B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0156]
FIG. 17D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 17D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0157]
However, the projector shown in FIG. 17 shows a case where a transmission type electro-optical device is used, and an application example in a reflection type electro-optical device is not shown.
[0158]
FIG. 18A illustrates a mobile phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. The present invention can be applied to the audio output unit 3902, the audio input unit 3903, the display unit 3904, and other signal control circuits.
[0159]
FIG. 18B illustrates a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003 and other signal circuits.
[0160]
FIG. 18C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0161]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the electronic device of the present embodiment can be realized by using any combination of the first to fourth embodiments.
[0162]
【The invention's effect】
By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) A simple structure perfectly adapted to the conventional TFT manufacturing process.
(B) The film thickness and refractive index of the base insulating film can be controlled easily and precisely. Therefore, it is easy to precisely control the position of the intensity distribution of the laser beam.
(C) For positioning of the slits and the like, the laser irradiation apparatus does not require any special micron-order precision positioning technology, and a normal laser irradiation apparatus can be used as it is.
(D) It is a method capable of producing crystal grains having a large grain size with position control while satisfying the above advantages.
[Brief description of the drawings]
FIG. 1A is a view showing an example of the invention disclosed by the present inventors in Japanese Patent Application No. 11-35060.
(B) The figure which shows the temperature history in each point of (A).
2A shows a laser beam having a wavelength of 308 nm from the back side of the substrate with respect to the second sample by fixing the thickness of the silicon nitride film and changing the thickness of the silicon nitride oxide film (A-type). The figure which shows the reflectance and absorption factor with respect to an amorphous silicon film when irradiated.
(B) When the thickness of the silicon nitride oxide film (A-type) is fixed and the thickness of the silicon nitride film is changed, and the second sample is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate The figure which shows the reflectance and absorption factor with respect to an amorphous silicon film.
FIG. 3A shows a laser beam having a wavelength of 532 nm from the back side of the substrate with respect to the second sample by fixing the thickness of the silicon nitride film and changing the thickness of the silicon nitride oxide film (A-type). The figure which shows the reflectance and absorption factor with respect to an amorphous silicon film when irradiated.
(B) When the thickness of the silicon nitride oxide film (A-type) is fixed and the thickness of the silicon nitride film is changed, and the second sample is irradiated with a laser beam having a wavelength of 532 nm from the back side of the substrate The figure which shows the reflectance and absorption factor with respect to an amorphous silicon film.
FIG. 4 is a diagram showing an example of base film formation and laser beam irradiation disclosed in the present invention.
FIG. 5 is a diagram showing an example of underlayer formation and laser beam irradiation disclosed in the present invention.
FIG. 6 is a diagram showing an example of underlayer formation and laser beam irradiation disclosed in the present invention.
FIGS. 7A and 7B are diagrams illustrating an example of base film formation and laser beam irradiation disclosed in the present invention. FIGS.
FIG. 8 is a diagram showing a comparison between the solid-phase crystallization start time in the configuration disclosed in the present invention and an example of the invention disclosed in Japanese Patent Application No. 11-35160.
FIG. 9 is a diagram showing an example of underlayer formation and laser beam irradiation disclosed in the present invention.
FIG. 10A shows the reflectivity with respect to an amorphous silicon film when the refractive index of the lower silicon oxynitride film is changed and the third sample is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate. The figure which shows an absorption rate.
(B) Changing the refractive index of the lower silicon oxynitride film, the reflectance and absorption rate for the amorphous silicon film when the third sample is irradiated with a laser beam having a wavelength of 532 nm from the back side of the substrate. FIG.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
12 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit. FIG.
13 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit. FIG.
FIG. 14 is a top view illustrating a pixel in a pixel portion.
FIG. 15 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG 16 illustrates an example of a semiconductor device.
FIG 17 illustrates an example of a semiconductor device.
FIG 18 illustrates an example of a semiconductor device.

Claims (7)

In a method for manufacturing a semiconductor device including a light-transmitting substrate, a first base insulating film, a second base insulating film having a first region and a second region, and a crystalline silicon film,
A first film thickness of the first base insulating film; a wavelength of the laser beam; a first refractive index of the first base insulating film with respect to the laser beam; and the second base insulating with respect to the laser beam. A first step for determining a second refractive index of the film;
Using the first film thickness determined in the first step, the wavelength of the laser beam, the first refractive index, and the second refractive index, the laser beam is applied to the amorphous silicon film. A second calculation is performed to obtain a graph in which the reflectance changes periodically with respect to the film thickness of the second base insulating film by performing a calculation of the reflectance on the film thickness of the second base insulating film. Steps,
A third step of determining a second film thickness that is the maximum value of the reflectivity from the graph obtained from the second step and determining a third film thickness that is the minimum value of the reflectivity; Have
Forming the first base insulating film on the substrate so as to have the first thickness determined in the first step;
Forming the second base insulating film on the first base insulating film;
The second base insulating film is partially etched, the first region is determined to be the second film thickness determined in the third step, and the second region is determined in the third step. Forming the third film thickness,
Forming the amorphous silicon film on the second base insulating film in which the first region and the second region are formed;
The amorphous silicon film is irradiated with the laser beam having the wavelength of the laser beam determined in the first step from the back side of the substrate or from both the front side and the back side of the substrate. Form the
A method for manufacturing a semiconductor device, wherein a TFT is formed using the crystalline silicon film formed on the second region as a channel formation region. In a method for manufacturing a semiconductor device, which includes a light-transmitting substrate, a first base insulating film having a first region and a second region, a second base insulating film, and a crystalline silicon film.
A first film thickness of the second base insulating film; a wavelength of the laser beam; a first refractive index of the first base insulating film with respect to the laser beam; and the second base insulating with respect to the laser beam. A first step for determining a second refractive index of the film;
Using the first film thickness determined in the first step, the wavelength of the laser beam, the first refractive index, and the second refractive index, the laser beam is applied to the amorphous silicon film. A second calculation is performed to calculate the dependence of the reflectance on the thickness of the first base insulating film, and to obtain a graph in which the reflectance changes periodically with respect to the thickness of the first base insulating film. Steps,
A third step of determining a second film thickness that is the maximum value of the reflectivity from the graph obtained from the second step and determining a third film thickness that is the minimum value of the reflectivity; Have
Forming the first base insulating film on the substrate;
The first base insulating film is partially etched, the first region is determined to be the second film thickness determined in the third step, and the second region is determined in the third step. Forming the third film thickness,
The second base insulating film is formed on the first base insulating film in which the first region and the second region are formed so as to have the first film thickness determined in the first step. Forming,
Forming the amorphous silicon film on the second base insulating film;
The amorphous silicon film is irradiated with the laser beam having the wavelength of the laser beam determined in the first step from the back side of the substrate or from both the front side and the back side of the substrate. Form the
A method for manufacturing a semiconductor device, wherein a TFT is formed using the crystalline silicon film formed on the second region as a channel formation region. In a method for manufacturing a semiconductor device in which an amorphous silicon film is crystallized using a laser beam,
Forming a first base insulating film made of silicon nitride on a light-transmitting substrate so as to have a first film thickness;
Forming a second base insulating film made of silicon nitride oxide on the first base insulating film;
The second base insulating film is partially etched to form a first region with a second thickness and a second region with a third thickness,
Forming the amorphous silicon film on the second base insulating film in which the first region and the second region are formed;
The amorphous silicon film is irradiated with the laser beam from the back side of the substrate or from both the front side and the back side of the substrate to form a crystalline silicon film,
Forming a TFT using the crystalline silicon film formed on the second region as a channel formation region;
The second film thickness is the amorphous film when the first film thickness and the second film thickness are stacked and the laser beam is irradiated through the first film thickness and the second film thickness. It is a film thickness at which the reflectance with respect to the porous silicon film becomes the maximum value,
The third film thickness is the amorphous film when the first film thickness and the third film thickness are stacked, and the laser beam is irradiated through the first film thickness and the third film thickness. A method for manufacturing a semiconductor device, characterized in that the film thickness is such that the reflectance with respect to a silicon film is a minimum value. In a method for manufacturing a semiconductor device in which an amorphous silicon film is crystallized using a laser beam,
Forming a first base insulating film made of silicon nitride over a light-transmitting substrate;
The first base insulating film is partially etched to form a first region having a first thickness and a second region having a second thickness,
Forming a second base insulating film made of silicon nitride oxide on the first base insulating film in which the first region and the second region are formed to have a third film thickness;
Forming the amorphous silicon film on the second base insulating film;
The amorphous silicon film is irradiated with the laser beam from the back side of the substrate or from both the front side and the back side of the substrate to form a crystalline silicon film,
Forming a TFT using the crystalline silicon film formed on the second region as a channel formation region;
The second film thickness is the amorphous film when the first film thickness and the second film thickness are stacked and the laser beam is irradiated through the first film thickness and the second film thickness. It is a film thickness at which the reflectance with respect to the silicon film is a minimum value,
The third film thickness is the amorphous film when the first film thickness and the third film thickness are stacked, and the laser beam is irradiated through the first film thickness and the third film thickness. A method for manufacturing a semiconductor device, characterized in that the film thickness has a maximum reflectance with respect to a silicon film. Forming a first base insulating film made of silicon nitride on a light-transmitting substrate so as to have a thickness of 50 nm ;
Forming a second base insulating film made of silicon nitride oxide on the first base insulating film;
The second base insulating film is partially etched so that the first region has a thickness of 130 nm to 150 nm and the second region has a thickness of 78 nm to 98 nm ,
Forming an amorphous silicon film on the second base insulating film in which the first region and the second region are formed;
The amorphous silicon film is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate or both the front side and the back side of the substrate to form a crystalline silicon film,
A method for manufacturing a semiconductor device, wherein a TFT is formed using the crystalline silicon film formed over the second region as a channel formation region. Forming a first base insulating film made of silicon nitride over a light-transmitting substrate;
The first base insulating film is partially etched to form a first region having a thickness of 55 nm to 85 nm and a second region having a thickness of 25 nm to 45 nm ,
A second base insulating film made of silicon nitride oxide having a refractive index different from that of the first base insulating film is formed to 100 nm on the first base insulating film in which the first region and the second region are formed. formed in such a way that,
Forming an amorphous silicon film on the second base insulating film;
The amorphous silicon film is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate or both the front side and the back side of the substrate to form a crystalline silicon film,
A method for manufacturing a semiconductor device, wherein a TFT is formed using the crystalline silicon film formed over the second region as a channel formation region. Forming a first base insulating film made of silicon nitride on a light-transmitting substrate so as to have a thickness of 50 nm ;
Forming a second base insulating film made of silicon nitride oxide on the first base insulating film;
The second base insulating film is partially etched so that the first region has a thickness of 78 nm to 98 nm and the second region has a thickness of 25 nm to 45 nm .
Forming an amorphous silicon film on the second base insulating film in which the first region and the second region are formed;
The amorphous silicon film is irradiated with a laser beam having a wavelength of 308 nm from the back side of the substrate or both the front side and the back side of the substrate to form a crystalline silicon film,
A method for manufacturing a semiconductor device, wherein a TFT is formed using the crystalline silicon film formed over the first region as a channel formation region.

Images