JP4673008B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device.

  Conventionally, for example, Patent Document 1 discloses a semiconductor memory that enables reading and writing in one cycle in the same cell, and further performs two-port operations of reading and writing simultaneously in one cycle necessary for reading. . In this semiconductor memory, since there is one CK terminal, a read operation is performed at the rising edge of CK and a write operation is performed at the falling edge of CK, read / write is performed in one common cycle.

  Further, Patent Document 2 discloses a pipelined dual circuit equipped with an arbitration circuit that can be started with priority even when two clocks of a dual-port memory having a single-port bit cell are input almost simultaneously. A port integrated circuit memory (SRAM) is disclosed.

  Patent Document 3 discloses a pseudo dual port memory in which a single port memory is converted into a dual port memory by an external circuit.

  Patent Document 4 discloses a pseudo dual-port memory in which a plurality of single-port memories are made into a dual-port memory by an external circuit.

  Patent Document 5 discloses a semiconductor memory device which is a single-port SRAM and has a write-only address decoder and a read-only address decoder and is configured to perform writing and reading simultaneously. .

  Further, Patent Document 6 discloses a semiconductor memory device that uses a single-port SRAM memory cell to perform two operations of reading or writing, which are realized by a 2-port SRAM, in the same cycle.

JP 2000-173270 A JP 2000-30460 A Japanese Utility Model Publication No. 5-20139 Japanese Utility Model Publication No. 5-66751 JP-A-10-11969 Japanese Patent Laid-Open No. 11-297073

  Since the single port SRAM used conventionally has one port as a matter of course, it cannot access different addresses at the same time.

  Further, in the case of a conventional dual port SRAM, it is possible to access different addresses at the same time, but a dual port bit cell (for example, see FIG. 10) as compared with a single port bit cell (for example, see FIG. 9). Has a large number of gates, two word lines, and two pairs of bit lines, and a dual port SRAM using this has a large area.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can simultaneously access different addresses using a single-port bit cell.

In order to solve the above-mentioned problem, the invention described in claim 1 is a divided word line type synchronous semiconductor memory device (SRAM) having a memory array using a single-port bit cell, and is controlled by SRAM. There are two ports 1 and 2 having a data input terminal, a data input terminal, and a data output terminal, and only one or two word lines are set up in each row of the memory array. A plurality of column gates corresponding to port 1 and port 2 are connected to the bit line, and each port has a sense amplifier and a write buffer, and a data input / output circuit connected thereto; two transfer gates, have a single transistor, the block of the column that contains the bit lines of the word line and the word unit Leading a divided word line selector which connects the divided word line, the two transfer gates and outputting an inverted signal, the block of the column that contains the bit lines of the divided word line and word units connected thereto, the port 1 and port in response to the input of each column address 2, with the respective bit line and a divided word line control circuit outputs a bit line cell selection signal for selecting two blocks is the same, different addresses from a common memory array Can be accessed simultaneously.

  The invention described in claim 2 is characterized in that, in the invention described in claim 1, a circuit for operating only the port 1 when the column addresses of the port 1 and the port 2 coincide is provided. And

  According to the semiconductor memory device of the present invention, different addresses can be accessed simultaneously using the single-port bit cell.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor memory device (SRAM) of the present invention. Here, a description will be given of a synchronous SRAM provided with CK at each port. The CK of the two ports may be asynchronous. For simplicity, a schematic diagram of the present invention of 16 words × 4 bits is shown.

  The SRAM 1 in FIG. 1 has two ports each having a clock input PXCK, an address input PXADD, a chip access control input PXCEB, a read / write control input PXWEB, a data input PXDI, and a data output PXDO. Here, PX means P1 and P2 indicating port 1 or port 2. The following description is also the same.

  The memory array section includes a single-port bit cell SBC and a divided word line (DWL) selector. Four SBCs are connected to the divided word line DWL connected to the DWL selector, and this is a unit of 1 word (4 bits). In addition, four rows of circuits each consisting of one DWL selector, one DWL, and four SBCs are arranged. A portion surrounded by a dotted line including these is called a divided word line (DWL) column block DB. In FIG. 1, four DBs are shown.

  The operation of each circuit will be described below. The internal control circuit 2 controls the operation of the SRAM. If either PXCEB is L, the corresponding port is enabled. If either PXCEB is H, the corresponding port is disabled. If both PXCEBs are L, both ports are enabled. If both PXCEBs are H, the entire chip is disabled. In the following description, both PXCEBs are L.

  If PXWEB is H, the corresponding port can be read-accessed. At this time, when PXCK becomes H, PXSE becomes H and the corresponding sense amplifiers 11 and 13 are enabled. When PXCK is L, PXSE is also L, and the sense amplifiers 11 and 13 are disabled.

  If PXWEB is L, the corresponding port is write-accessible. At this time, when PXCK becomes H, PXWE becomes H and the corresponding write buffers 10 and 12 are enabled. When PXCK is L, PXWE is also L, and the write buffer is disabled.

  PXINCK output from the internal control circuit is an internal clock generated from PXCK and PXCEB. Circuits other than the internal control circuit are controlled by this PXINCK.

  The address input circuit 3, the row decoder 4 and the column decoder 5 are shown in FIG. In the address input circuit 3, an address latch is connected to each address terminal PXADD. This address latch latches the address when PXINCK becomes H and holds it until PXINCK becomes L. The output of each address latch is input to the row decoder 4 and the column decoder 5. In FIGS. 1 and 2, PXADD [2] -PXADD [3] is a row address and is input to the row decoder 4, and PXADD [0] -PXADD [1] is a column address and is input to the column decoder 5. The row decoder decodes P1ADD [2] -P1ADD [3] into P1AX [0] -P1AX [3] via the address latch.

P1AX [0] -P1AX [3] is when P1INCK is H
When (P1ADD [3], P1ADD [2]) = (0,0) P1AX [0] = H,
When (P1ADD [3], P1ADD [2]) = (0,1) P1AX [1] = H,
When (P1ADD [3], P1ADD [2]) = (1,0) P1AX [2] = H,
When (P1ADD [3], P1ADD [2]) = (1,1) P1AX [3] = H,
And L otherwise.

  Similarly, P2ADD [2] -P2ADD [3] is decoded into P2AX [0] -P2AX [3] via the address latch.

P2AX [0] -P2AX [3] is when P2INCK is H
When (P2ADD [3], P2ADD [2]) = (0,0) P2AX [0] = H,
When (P2ADD [3], P2ADD [2]) = (0,1) P2AX [1] = H,
When (P2ADD [3], P2ADD [2]) = (1,0) P2AX [2] = H,
When (P2ADD [3], P2ADD [2]) = (1,1) P2AX [3] = H,
And L otherwise.

  Furthermore, P1AX [0] and P2AX [0] are input to the 2-input OR and output WL [0]. Similarly, P1AX [1] and P2AX [1], P1AX [2] and P2AX [2], P1AX [3] and P2AX [3] are also input to the 2-input OR, and WL [1] and WL [2] respectively. , WL [3] is output.

  In this OR circuit, when one of P1AX and P2AX becomes H, if the numbers in [] do not match, two WLs are started up and the numbers in [] match. If there is, launch one common WL.

  The column decoder decodes P1ADD [0] -P1ADD [1] into P1YG [0] -P1YG [3] via the address latch.

P1YG [0] -P1YG [3] is when P1INCK is H
When (P1ADD [1], P1ADD [0]) = (0,0) P1YG [0] = H
When (P1ADD [1], P1ADD [0]) = (0,1) P1YG [1] = H,
When (P1ADD [1], P1ADD [0]) = (1,0) P1YG [2] = H,
When (P1ADD [1], P1ADD [0]) = (1,1) P1YG [3] = H,
And L otherwise.

  Similarly, P2ADD [0] -P2ADD [1] is decoded into P2YG [0] -P2YG [3] via the address latch.

P2YG [0] -P2YG [3] is when P2INCK is H
When (P2ADD [3], P2ADD [2]) = (0,0) P2YG [0] = H
When (P2ADD [3], P2ADD [2]) = (0,1) P2YG [1] = H
When (P2ADD [3], P2ADD [2]) = (1,0) P2YG [2] = H,
When (P2ADD [3], P2ADD [2]) = (1,1) P2YG [3] = H,
And L otherwise.

  P1YG [0] -P1YG [3] and P2YG [0] -P2YG [3] are input to a predetermined column gate and a divided word line (DWL) control circuit.

  One circuit of the column gate is connected to one pair of BL-BLB of the memory array. The column gate is composed of four transfer gates and two inverters as shown in FIG. Two transfer gates are connected to each of BL and BLB. Of the two transfer gates connected to BL or BLB, one is a column gate for port 1 and the other is a column gate for port 2.

  The transfer gate is turned on / off by the PXYG signal output from the column decoder. When P1YG becomes H, the transfer gate connected to P1YG and its inverted signal is turned on, and BL and P1DL, and BLB and P1DLB become conductive. When P2YG becomes H, the transfer gate connected to P2YG and its inverted signal is turned on, and BL and P2DL, and BLB and P2DLB become conductive. When PXYG is L, each corresponding transfer gate is turned off.

  P1DL and P1DLB are connected to the port 1 sense amplifier and the write buffer, and P2DL and P2DLB are connected to the port 2 sense amplifier and the write buffer to exchange data between the BL and the input / output circuits 14 and 15.

  Four column gates are installed in each column block DB [0] -DB [3] of the divided word line, and the output PXYG [0] from the column decoder is connected to all the column gates in DB [0]. Has been. PXYG [1] -PXYG [3] are similarly connected to all the column gates of DB [1] -DB [3], respectively.

  A divided word line (DWL) control circuit is shown in FIG. One is installed in each column block DB of the divided word line. When PXYG is H, set PXYGA to H and PXYGB to L. These signals are signals for controlling the rise and fall of the divided word lines. When both PXYG are L, the output terminal DBSELB is H. When one of PXYG is H, DBSELB is L. This signal is a signal for selecting a column block DB of divided word lines. If both PXYG are H, the data for the access address on the port 1 side and the access address on the port 2 side may collide at BL-BLB, so the user controls the column address and two PXYGs Both must not be H.

  FIG. 5 shows a divided word line (DWL) selector and a single port bit cell (SBC) connected thereto. In FIG. 1, one DWL selector is installed for four SBC columns. In FIG. 1, four DWL selectors are connected to one WL. One divided word line (DWL) is connected from the DWL selector, and four SBCs are connected to the DWL. Details of the SBC are shown in FIG.

  The DWL selector consists of two transfer gates and one Nch transistor. WL is connected to two transfer gates and their outputs are connected to the same DWL. As shown in FIG. 4, P1YGA and P1YGB and P2YGA and P2YGB input to the transfer gate are in an inverted relationship. When P1YGA is H and P1YGB is L, or when P2YGA is H and P2YGB is L, the transfer gate is turned on and WL and DWL are connected. At this time, since either P1YG or P2YG in FIG. 4 is H, DBSELB is L, and the Nch transistor in FIG. 5 is turned off. Since WL and DWL are connected, DWL is H if WL is H, and DWL is L if WL is L. Only when DWL is H, the access gate of the SBC connected to it opens, so data is transferred between the SBC and BL-BLB.

  As described above, the user controls the signals P1YG and P2YG for selecting the same DWL column block DB not to rise at the same time.

  When both PXYGA is L and both PXYGB are H, both transfer gates are off, so WL and DWL are blocked. This is a case where both P1YG and P2YG in FIG. 4 are L, and DBSELB becomes H, so that the Nch transistor in FIG. 5 is turned on and DWL becomes L. Since DWL is L, the access gate of the SBC connected thereto is turned off, and the SBC and BL-BLB are blocked.

The precharge circuit 9 is shown in FIG. When DBSELB is L, that is, when either P1YG or P2YG in FIG. 4 is H, the three Pch transistors are turned off. When DBSELB is H, that is, when P1YG and P2YG in FIG. 4 are L, the three Pch transistors are turned on, and BL-BLB is precharged to H. When DBSELB is L, the column block DB of DWL is selected. Since DWL in the same DB rises and SCB and BL-BLB exchange data, it is necessary to stop precharge. is there. For this reason, the three Pch transistors are turned off. When DBSELB is H, all DWLs in the same DB are L, so the three Pch transistors are turned on to precharge BL-BLB.
As described above, the column gate 6 for each port is connected to the write buffer and sense amplifier for each port, which are further connected to the data input / output circuits 14 and 15 for each port.

  The data input / output circuits 14 and 15, the write buffers 10 and 12, and the sense amplifiers 11 and 13 are shown in FIG.

  When PXWE is H, data is sent from the input latch to the write buffers 10 and 12, and the write buffers 10 and 12 send data to the column gate 6. When PXSE is H, data is sent from the sense amplifier to the output latch. When each signal is L, the corresponding write buffer and sense amplifier are disabled.

  As described above, by controlling the column address so that the signals P1YG and P2YG for selecting the column block DB of the DWL do not select the same DB at the same time, Only one DWL starts up at DB. By preparing column gates for port 1 and port 2, the column gate in one DB turns on only port 1 and the column gate in the other DB. By turning on only the port 2 side and connecting each data line to each port gate, two addresses can be accessed simultaneously.

  Although the synchronous circuit has been described with reference to FIG. 1, even in an asynchronous SRAM, different addresses can be accessed at the same time if the column addresses are input so as not to be the same.

  In the description so far, the column address in FIG. 2 is based on the condition that the user controls the column address so that the signals P1YG and P2YG for selecting the column block DB of DWL do not select the same DB at the same time. In addition, by adding the circuit of FIG. 8, when P1YG and P2YG select the same DB, it is possible to give priority to access on the port 1 side and not operate the port 2 side.

  Although FIG. 8 illustrates only P1YG [0] and P2YG [0], the same circuit is added to [1], [2], and [3]. This circuit forces P2YGQ [0] to L when both P1YG [0] and P2YG [0] are H. P2YGQ [0] is input instead of P2YG [0], which is the output P2YG [0] of FIG. 2 input in FIG. The same applies to P2YGQ [1], P2YGQ [2], and P2YGQ [3]. Since P2YGQ is L, neither the column gate nor the DWL selector is turned on on the port 2 side, so that the port 1 can be accessed without hitting the data on the port 2 side.

  As described above, in the above-described embodiment, by configuring an SRAM having two ports with a single-port bit cell, the number of transistors, the number of word lines, and the bit line can be compared with an SRAM using a dual-port bit cell. Since the number of pairs can be reduced, access to addresses is limited, but a dual-port memory can be configured with a small area. Compared to a single-port memory, twice the amount of data can be accessed in the same cycle with only an increase in the area of the control circuit.

  In addition, even when the column addresses of port 1 and port 2 are the same, only port 1 access can be performed as usual, so that the trouble of considering column addresses to be the same is reduced, and the design period can be shortened. is there.

  As described above, the present invention proposes a dual-port SRAM that can simultaneously access different addresses using a single-port bit cell as shown in FIG. Compared to a dual port SRAM having a bit cell as shown in FIG. 10, the degree of freedom of address access is reduced, but the area is reduced, and double data access is possible in the same cycle as compared to a single port SRAM.

In addition, below, the effect of this invention is demonstrated compared with the patent documents 1-6 mentioned above. When the present invention and Patent Document 1 are compared, they are common in that a single-port bit cell is used to make a dual port, but in Patent Document 1, the timing of reading and writing is shifted in the same cycle. The present invention allows simultaneous access to different column addresses by using divided word lines.
When the present invention and Patent Document 2 are compared, they are common in that a single port bit cell is used to make a dual port. However, Patent Document 2 is an invention related to SRAM clock control, and the present invention is an SRAM divided word. The present invention relates to the configuration of a line, a decoder, a column decoder, and the like.
When the present invention and Patent Document 3 are compared, it is different from Patent Document 3 because it relates to a dual port SRAM using a single port bit cell.
When the present invention and Patent Document 4 are compared, it is different from Patent Document 4 because it relates to a dual port SRAM using single port bit cells.
When the present invention is compared with Patent Document 5, they are similar in that writing and reading are performed at the same time. However, in the present invention, simultaneous writing and simultaneous reading are possible as long as they have different column addresses.
When the present invention and Patent Document 6 are compared, they are similar in that simultaneous writing, simultaneous reading, and simultaneous writing / reading are possible, but Patent Document 6 targets addresses on the same word line. In the present invention, different word lines may be used as long as they have different column addresses.

1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention. It is a circuit diagram of an address input circuit, a row decoder, and a column decoder. It is a circuit diagram of a column gate. FIG. 6 is a divided word line control circuit diagram. It is a circuit diagram of a single port bit cell (SBC). It is a circuit diagram of a precharge circuit. It is a figure which shows a PX data input / output circuit. It is a figure which shows a column decoder addition circuit. It is a figure which shows the detail of SBC. It is a figure which shows the detail of DBC.

Explanation of symbols

10, 12 Write buffer 11, 13 Sense amplifier 14, 15 Data input / output circuit P1 Port 1
P2 port 2

Claims (2)

A divided wordline synchronous SRAM having a memory array using a single-port bit cell,
Two ports 1 and 2 having an input terminal for SRAM control, a data input terminal, and a data output terminal;
Only one or two word lines can be set up in each row of the memory array,
A plurality of column gates corresponding to port 1 and port 2 are connected to the bit line, and each port has a sense amplifier and a write buffer, and a data input / output circuit connected to them,
Further, two transfer gates, have a single transistor, and divided word line selector which connects the divided word line connected to the block of the column that contains the bit lines of the word line and the word unit,
The two transfer gates outputs an inverted signal, the block of the column that contains the bit lines of the divided word line and word units connected thereto, in response to the input of each column address ports 1 and 2, each bit for the line and a divided word line control circuit outputs a bit line cell selection signal for selecting the two blocks are the same,
A semiconductor memory device, wherein different addresses can be simultaneously accessed from a common memory array. 2. The semiconductor memory device according to claim 1, further comprising a circuit that operates only port 1 when the column addresses of port 1 and port 2 match.

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