JP4662745B2 - Gradation data generation circuit and gradation data generation method - Google Patents

Description

  The present invention relates to a gradation data generation circuit and a gradation data generation method that can be applied to a liquid crystal panel display control circuit or the like using gradation expression by an FRC (Fame Rate Control) method.

  Conventionally, as a gradation control method for a simple matrix liquid crystal panel, an FRC system is known that expresses a plurality of gradations by changing the number of blinks of n-bit image data with a plurality of frames as one period. Here, the FRC method for displaying gradation of 5-bit image data will be specifically described.

  The 5-bit image data includes 32 kinds of data of 00000b (0), 00001b (1) to 11110b (1E), and 11111b (1F), and can express 32 gradations at the maximum. When displaying 32 gradations, the number of appearances of ON (output 1) and OFF (output 0) is changed in a cycle of 32 frames.

  For example, when the image data is 00000b (0), the number of occurrences of [00000000000000000000000000000000] b and ON (output 1) is 32 in 32 frames, and in the case of 01000b (8), [ [00010001000100010001000100010001] The number of appearances of b and ON (output 1) is 8 times, and in the case of 10110b (22), the number of appearances of [11101110111010101110111011101010] b and ON (output 1) is 22 in 32 frames. , 11111b (31), the number of occurrences of [11111111111111111111111111111111] b and ON (output 1) in 32 frames is 32 times. The ON / OFF blinking pattern data is configured as a gradation table (register) of 32 gradations × 32 bits wide, and 32 gradation tables (registers) according to the input 5-bit image data value. One is selected and becomes thinned data, and is sequentially output as 1-bit display data for each frame period.

  This blinking pattern data causes a so-called flicker because the apparent frame frequency decreases when ON (1 is output) / OFF (0 is output) is concentrated in time. Therefore, it is desirable that the blinking pattern data is dispersed as much as possible. For example, when the image data is 01000b (8), if the blinking pattern data is set to [00000000000000000000000000011111111] b, the OFF (output 0) time continues for 24 frame periods and is turned ON (output 1). Since the remaining time is continuous for 8 frames, ON (output 1) / OFF (output 0) is easily recognized by human eyes, which causes flicker. Therefore, it is desirable to use a pattern in which ON (1 is output) / OFF (0 is output) is distributed as in [00010001000100010001000100010001] b.

  Further, even if the same blinking pattern data is spatially concentrated, it causes flickering. Therefore, it is desirable that the blinking pattern data is dispersed as spatially as possible. For example, when a certain dot coordinate and the neighboring dot coordinate are the same image data 01000b (8), the same blinking pattern data [00010001000100010001000100010001] b is selected as each dot coordinate, and ON (1 is set at each coordinate). Since (output) / OFF (output 0) occurs at the same time, ON (output 1) / OFF (output 0) is easily recognized by human eyes, resulting in flicker. Therefore, even with the blinking pattern data [00010001000100010001000100010001] b of the same image data 01000b (8), the coordinates are changed to [00100010001000100010001000100010] b, [01000100010001000100010001000100] b, [10001000100010001000100010001000] b for each coordinate, and a certain dot coordinate and its neighboring dots It is desirable to disperse the coordinates so that ON (1 is output) / OFF (0 is output) does not occur simultaneously.

  Therefore, for example, in Patent Document 1, the blinking pattern data output from the gradation table (register) is made to have different blinking phases at the odd-numbered pixels and the even-numbered pixels and between the odd-numbered lines and the even-numbered lines in the thinning control unit. A method for reducing flicker is described. Patent Document 2 describes a method of reducing flicker by mounting a position correction table (register) that outputs a phase correction value of each dot and making the blinking phase different for each coordinate. .

Japanese Patent No. 2679595 JP 2000-10528 A

  However, in the conventional gradation data generation circuit and the like, a memory circuit such as a gradation table (register) for storing blinking pattern data and a position correction table (register) for outputting the phase correction value of each dot, There is a problem that a circuit for converting the data of the gradation table (register) into display data that reduces flicker is required, which increases the circuit scale.

  Therefore, the present invention has been made in view of the above-described problems in the prior art, and can suppress flicker with a small circuit scale without using a memory circuit such as a gradation table (register). An object is to provide a gradation data generation circuit and a gradation data generation method.

In order to achieve the above object, the present invention provides a grayscale data generation circuit for generating grayscale data expressing a plurality of grayscales by changing the number of blinks with a plurality of frames as one cycle, and counting with a display frame cycle. A frame counter, an X coordinate counter that counts in the display horizontal coordinate period, a Y coordinate counter that counts in the display vertical coordinate period, and a frame count value output from the frame counter. a frame counter select means for different frame count value at different pixels based on the values, the frame count value output from the frame counter select means, and X-coordinate counted value output from the X-coordinate counter, the Y-coordinate Different frame counts for each pixel depending on the Y coordinate count value output from the counter A frame counter conversion means for converting the preparative value, each bit of the converted frame count value in the frame counter conversion means, display of one bit by bit operation based on the arithmetic expression selected by the multi-valued input image data And display data generating means for outputting as data.

  According to the present invention, since the gradation data is generated by using the frame count value as a parameter, the gradation data is generated without using a memory circuit such as a gradation table (register) as in the prior art. In addition, since the frame count value is converted into a different frame count value for each pixel depending on the X coordinate count value and the Y coordinate count value, the gradation data is dispersed temporally and spatially and is small. Flicker can be suppressed by the circuit scale.

  In the gradation data generation circuit, the frame counter conversion means and / or the frame counter selection means are connected to the calculation control means via a bus, and from the calculation control means, a predetermined conversion method and / or a predetermined division method. One conversion method and / or division method may be selectable. As a result, the flicker reduction pattern or the like can be changed, and adjustment corresponding to the input image can be performed.

In addition, the present invention is a method for generating gradation data expressing a plurality of gradations by changing the number of blinks with a plurality of frames as one period, and generating a first count value with a display frame period and displaying A count value is generated in a horizontal coordinate cycle, a count value is generated in a display vertical coordinate cycle, the first count value in the display frame cycle is divided into a plurality of pixels, and different pixels are based on each divided count value A different second count value is generated at, and the second count value is converted into a different frame count value for each pixel depending on the count value in the display horizontal coordinate cycle and the count value in the display vertical coordinate cycle. and, especially to output each bit of the converted frame count value, and the bit operation based on the arithmetic expression selected by the multi-valued input image data as a 1-bit display data To. Thus, as described above, the gradation data is dispersed temporally and spatially, and flicker can be suppressed.

  As described above, according to the present invention, it is possible to provide a gradation data generation circuit and a gradation data generation method that can suppress flicker with a small circuit scale.

  Next, as an embodiment of the present invention, detailed description will be given by taking as an example a case where 5-bit input image data is displayed in gradation. In this case, the maximum gradation is 32 and gradation is expressed with 32 frames as one cycle.

  FIG. 1 shows the configuration of a first embodiment of a gradation data generation circuit according to the present invention. The frame counter 1 is a 5-bit free-run counter that counts in the display frame cycle. The count value repeats from 0 to 31. The X coordinate counter 2 is a 4-bit free-run counter that counts in the display horizontal coordinate cycle. The count value repeats from 0 to 15. The Y coordinate counter 3 is a 4-bit free-run counter that counts in the display vertical coordinate cycle. The count value repeats from 0 to 15. The frame counter conversion circuit 4 converts the frame count value S1 into a different frame count value for each pixel using the X coordinate count value S2 and the Y coordinate count value S3 as parameters. The frame counter conversion circuit 4 is connected to the CPU bus 6 and can select an arbitrary conversion method via a CPU (not shown). The display data generation circuit 5 performs a bit operation on the frame counter conversion value S4 output from the frame counter conversion circuit 4 and the input image data S5 and outputs the result as 1-bit display data S6.

  FIG. 2 is a diagram showing what 1-bit data is output in each frame with respect to the input image data S5 (0 to 31). The relationship between the input image data S5 and the frame count value S1 will be described below.

  For example, when the input image data S5 is 04h (4), it is necessary to turn the output data ON (output 1) four times during 32 frames. Which frame is turned ON (outputs 1) is ON (outputs 1) when the frame count value S1 shown in FIG. 2 is obtained by performing an operation of bit 0 & bit 1 & bit 2 using the frame count value S1 as a parameter. can do. That is, when the input image data S5 is 04h (4), the seventh frame (frame count value S1 is 00111b), the fifteenth frame (frame count value S1 is 01111b), and the twenty-third frame (frame count value S1). 1011b) and 31st frame (frame count value S1 is 11111b), it is turned ON (1 is output) by the arithmetic expression of bit 0 & bit 1 & bit 2, and is OFF (0 is output) in the other frames.

  As another example, when the input image data S5 is 08h (8), it is necessary to turn ON output data (output 1) 8 times during 32 frames. Which frame is turned on (outputs 1) can be turned on (output 1) when the frame count value S1 shown in FIG. 2 is obtained by performing the calculation of bit 0 & bit 1 using the frame count value S1 as a parameter. it can. That is, when the input image data S5 is 08h (8), the third frame (frame count value S1 is 0111b), the seventh frame (frame count value S1 is 00111b), and the 11th frame (frame count value S1). 01011b), 15th frame (frame count value S1 is 01111b), 19th frame (frame count value S1 is 10011b), 23rd frame (frame count value S1 is 10111b), and 27th frame (frame count). The value S1 is 11011b) and the 31st frame (the frame count value S1 is 11111b), which is ON (1 is output) by the arithmetic expression of bit 0 & bit 1, and is OFF (0 is output) in the other frames.

  Similarly, in the case of the other input image data S5, a gradation data table (flashing pattern data) as shown in FIG. 2 can be realized by giving a bit operation expression of each frame count value. In this blinking pattern data, if ON (1 is output) / OFF (0 is output) is concentrated in time, the apparent frame frequency decreases and causes flicker. ON (1 is output) / OFF (0 is output) appears evenly. Note that the blinking pattern data shown in FIG. 2 is an example, and other blinking pattern data can be adopted depending on the arithmetic expression given.

  Next, the frame counter conversion circuit 4 will be described. If only the above-mentioned gradation data table (flashing pattern data) generation process is used, if a certain dot coordinate and the neighboring dot coordinate are the same image data, the same data ON (1 is output) / OFF (0 is set). Output) occur at the same time, causing flicker. In order to prevent this, the X count value S2 and the Y count value S3 are added as parameters, and the frame count value S1 is converted to a different frame count value at each dot coordinate. FIG. 3 shows a calculation result when the X weight value of the X count value S2 and the Y count value S3 is simply XORed (exclusive OR operation) in a 16 dot × 16 dot region. By adding to the count value S1, the frame counter conversion value S4 is output.

  For example, when the input image data S5 is 04h (4) for all dots, the above-described gradation data table (flashing pattern data) generation process is performed using the frame count value S1 as it is. Dot turns ON (outputs 1) at the 7th, 15th, 23rd, and 31st frames at the same time, causing flicker. Therefore, when the above-described gradation data table (flashing pattern data) generation process is performed using the frame counter conversion value S4, the timing when the dot is turned on (outputs 1) changes, and flicker can be reduced. it can.

  As shown in FIG. 3, when the X coordinate count value S2 is 5h (5) and the Y coordinate count value S3 is 1h (1), that is, the dot coordinate (5, 1) is 11 as the frame count value S1 + 4. ON (output 1) at the 19th frame, the 27th frame, and the 3rd frame, when the X coordinate count value S2 is 6h (6) and the Y coordinate count value S3 is 4h (4) That is, at the dot coordinates (6, 4), the frame count value S1 + 2 is turned on (outputs 1) at the ninth frame, the 17th frame, the 25th frame, and the first frame.

  As another example, FIG. 4 shows a calculation result when XOR is performed by rearranging the bit arrangement of the X count value S2 in 130 dots and the bit arrangement of the Y count value S3 into 3210 in a 16 dot × 16 dot region, When the coordinate count value S2 is 5h (5) and the Y coordinate count value S3 is 1h (1), that is, for the dot coordinates (5, 1), as the frame count value S1 + 2, the 9th frame, the 17th frame, ON (output 1) in the 25th frame and the 1st frame, when the X coordinate count value S2 is 6h (6) and the Y coordinate count value S3 is 4h (4), that is, the dot coordinates (6, 4) The frame count value S1 + D is simultaneously turned ON (outputs 1) in the 20th frame, the 28th frame, the 4th frame, and the 12th frame.

  Furthermore, as another example, in FIG. 5, only the lower 3 bits of the X coordinate count value S2 and the lower 3 bits of the Y coordinate count value S3 are used, and the arrangement of the bits of the X count value S2 in an 8 dot × 8 dot region is shown. 210 shows the calculation result when the bit count of the Y count value S3 is rearranged to 102 and XORed.

  A CPU bus 6 is connected to the frame counter conversion circuit 4, and the bit width referred to by the X count value S2 and the Y count value S3 and the arrangement of bits for calculation can be selected via the CPU. According to the input image, it is possible to select an optimum application area and conversion pattern that most reduces flicker.

  When the input image data S5 of a certain dot coordinate is input, the display data generation circuit 5 selects one arithmetic expression from the arithmetic expressions having 32 patterns by the input image data S5, and the frame counter conversion value S4 at that time Is substituted into the arithmetic expression and output as 1-bit display data S6.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a block diagram showing the configuration of the second embodiment of the gradation data generation circuit according to the present invention. In the present embodiment, a frame counter select circuit 7 is provided between the frame counter 1 and the frame counter conversion circuit 4. The frame counter selection circuit 7 refers to the lower 1 bit of each of the X coordinate count value S2 and the Y coordinate count value S3, and selects the use range of the frame count value S1 to be used in the 2 dot × 2 dot region. And output to the frame counter conversion circuit 4.

  FIG. 7 is a diagram showing the relationship between the dot coordinates and the range of the frame count value S1 to be used in the frame counter select circuit 7. In the coordinates indicated by A, 0 to 15 of the frame count value S1 are repeated ( 2), at the coordinates indicated by B, 16 to 31 of the frame count value S1 are repeatedly output to the frame counter conversion circuit 4. In this case, if different blink patterns are generated for the portion A and the portion B in FIG. 7, the frame counter select circuit 7 blinks ON (outputs 1) / OFF (outputs 0). Further, it can be spatially dispersed, and the number of gradations is reduced, but flicker can be reduced.

  A CPU bus 6 is connected to the frame counter select circuit 7, and it is possible to select whether or not to apply this circuit via the CPU, and which range of frame count values S1 is applied to which dot coordinates. Can also be selected, and can be configured to make a selection suitable for the image.

  For example, as shown in FIGS. 8 and 2, when the coordinates are indicated by C, 0 to 7 of the frame count value S1 are repeated, and when the coordinates are indicated by D, 8 to 15 of the frame count value S1 are repeated. When the coordinates are indicated, the frame count value S1 16-23 is repeated, and when the coordinates are indicated by F, the frame count value S1 24-31 is repeatedly output to the frame counter conversion circuit 4, or FIG. As shown, only the frame count values 0 to 15 are repeatedly output to the frame counter conversion circuit 4 for all the coordinates (A), and the number of gradations decreases, but ON (1 is output) / OFF ( The blinking of (output 0) can be further dispersed spatially.

1 is a block diagram showing a configuration of a first embodiment of a gradation data generation circuit according to the present invention. FIG. FIG. 3 is a diagram illustrating data output to each frame with respect to input image data in the gradation data generation circuit of FIG. 1. FIG. 7 is a diagram showing a calculation result when the same weight bits of the X count value and the Y count value are simply XORed in the 16 dot × 16 dot region in the gradation data generation circuit of FIG. 1. In the gradation data generation circuit of FIG. 1, in the 16 dot × 16 dot region, the X count value bit arrangement is changed to 1302, and the Y count value bit arrangement is changed to 3210 to perform the XOR. is there. In the gradation data generation circuit of FIG. 1, the calculation result when XOR is performed by rearranging the X count value bit sequence to 210 and the Y count value bit sequence to 102 in the 8 dot × 8 dot region. is there. It is a block diagram which shows the structure of 2nd Embodiment of the gradation data generation circuit concerning this invention. FIG. 7 is a diagram showing a relationship between dot coordinates and a range of frame count values to be used in the frame counter selection circuit of the gradation data generation circuit of FIG. 6. FIG. 7 is a diagram showing a relationship between dot coordinates and a range of frame count values to be used in the frame counter selection circuit of the gradation data generation circuit of FIG. 6. FIG. 7 is a diagram showing a relationship between dot coordinates and a range of frame count values to be used in the frame counter selection circuit of the gradation data generation circuit of FIG. 6.

Explanation of symbols

1 Frame Counter 2 X Coordinate Counter 3 Y Coordinate Counter 4 Frame Counter Conversion Circuit 5 Display Data Generation Circuit 6 CPU Bus 7 Frame Counter Select Circuit S1 Frame Count Value S2 X Coordinate Count Value S3 Y Coordinate Count Value S4 Frame Counter Conversion Value S5 Input Image data S6 Display data

Claims (3)

A gradation data generation circuit that generates gradation data that represents a plurality of gradations by changing the number of blinks with a plurality of frames as one cycle,
A frame counter that counts in the display frame period
An X coordinate counter that counts in the display horizontal coordinate period;
A Y coordinate counter that counts in the display vertical coordinate period;
A frame counter selection unit that divides the frame count value output from the frame counter into a plurality of frames and sets different frame count values for different pixels based on the divided count values;
The frame count value output from the frame counter selection means is changed to a different frame count value for each pixel between the X coordinate count value output from the X coordinate counter and the Y coordinate count value output from the Y coordinate counter. Frame counter conversion means for converting;
Display data generation means for performing bit operation on each bit of the frame count value converted by the frame counter conversion means based on an arithmetic expression selected by multi-valued input image data and outputting the result as 1-bit display data. A gradation data generation circuit characterized by the above. The frame counter conversion means and / or the frame counter selection means are connected to the arithmetic control means via a bus, and the predetermined conversion method and / or the predetermined division method to the single conversion method and / or the division from the arithmetic control means. 2. The gradation data generation circuit according to claim 1, wherein a method can be selected. A method of generating gradation data representing a plurality of gradations by changing the number of blinks with a plurality of frames as one cycle,
Generating a first count value in a display frame period;
Generate a count value in the display horizontal coordinate cycle,
Generate a count value with the display vertical coordinate period,
Dividing the first count value in the display frame period into a plurality of numbers, and generating different second count values for different pixels based on the divided count values;
Converting the second count value into a different frame count value for each pixel in the count value in the display horizontal coordinate cycle and the count value in the display vertical coordinate cycle;
A gradation data generation method characterized in that each bit of the converted frame count value is bit-calculated based on an arithmetic expression selected by multi-value input image data and output as 1-bit display data.

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