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JP4649825B2 - Driving method of plasma display device - Google Patents

Driving method of plasma display device Download PDF

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JP4649825B2
JP4649825B2 JP2003283760A JP2003283760A JP4649825B2 JP 4649825 B2 JP4649825 B2 JP 4649825B2 JP 2003283760 A JP2003283760 A JP 2003283760A JP 2003283760 A JP2003283760 A JP 2003283760A JP 4649825 B2 JP4649825 B2 JP 4649825B2
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sustain
electrode
discharge
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voltage
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JP2005049749A (en
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兼司 小川
実 武田
泰明 武藤
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Description

本発明はプラズマディスプレイ装置の駆動方法に関するものである。   The present invention relates to a driving method of a plasma display apparatus.

AC型プラズマディスプレイパネル(以下、パネルという)の構成を図3に示す。図3に示すように、透明な前面側のガラス基板からなる基板1上には、第1の電極である走査電極4と第2の電極である維持電極5とで対をなすストライプ状の表示電極が複数対形成されている。この走査電極4および維持電極5は、それぞれ透明電極4a、5aおよびこの透明電極4a、5aに電気的に接続された銀等の母線4b、5bとから構成されている。また、前記前面側の基板1には、前記複数対の電極群を覆うように誘電体層2が形成され、その誘電体層2上には保護膜3が形成されている。   The structure of an AC type plasma display panel (hereinafter referred to as a panel) is shown in FIG. As shown in FIG. 3, a striped display in which a scanning electrode 4 as a first electrode and a sustaining electrode 5 as a second electrode are paired on a substrate 1 made of a transparent front glass substrate. A plurality of pairs of electrodes are formed. The scan electrode 4 and the sustain electrode 5 are respectively composed of transparent electrodes 4a and 5a and buses 4b and 5b made of silver or the like electrically connected to the transparent electrodes 4a and 5a. A dielectric layer 2 is formed on the front substrate 1 so as to cover the plurality of pairs of electrodes, and a protective film 3 is formed on the dielectric layer 2.

背面側のガラス基板からなる基板6上には、絶縁体層7で覆われたデータ電極8が配設され、データ電極8の間の絶縁体層7上にデータ電極8と平行して隔壁9が設けられ、その絶縁体層7の表面と隔壁9の側面にかけて蛍光体10が設けられている。また、走査電極4および維持電極5とデータ電極8とが直交するように、基板1と基板6とを放電空間11を挟んで対向して配置し、その放電空間11に、放電ガスとして、ヘリウム、ネオン、アルゴン、キセノンの内の少なくとも1種類の希ガスを封入することにより、隣接する二つの隔壁9に挟まれ、データ電極8と、走査電極4および維持電極5との交差部の放電空間に放電セル12が構成されている。   A data electrode 8 covered with an insulator layer 7 is disposed on a substrate 6 made of a glass substrate on the back side, and a partition wall 9 is formed in parallel with the data electrode 8 on the insulator layer 7 between the data electrodes 8. The phosphor 10 is provided over the surface of the insulator layer 7 and the side surface of the partition wall 9. Further, the substrate 1 and the substrate 6 are arranged to face each other with the discharge space 11 interposed therebetween so that the scan electrode 4 and the sustain electrode 5 and the data electrode 8 are orthogonal to each other, and helium is used as the discharge gas in the discharge space 11. , Neon, argon, or xenon, by sealing at least one kind of rare gas, sandwiched between two adjacent barrier ribs 9, and a discharge space at the intersection of the data electrode 8, the scan electrode 4 and the sustain electrode 5 A discharge cell 12 is formed.

このパネルの電極配列は、図4に示すように、M行×N列の放電セルからなるマトリックス構成であり、行方向にはM行の走査電極SCN1〜SCNMおよび維持電極SUS1〜SUSMが配列され、列方向にはN列のデータ電極D1〜DNが配列されている。   As shown in FIG. 4, the electrode arrangement of this panel has a matrix configuration including M rows × N columns of discharge cells, and M rows of scan electrodes SCN <b> 1 to SCNM and sustain electrodes SUS <b> 1 to SUSM are arranged in the row direction. In the column direction, N columns of data electrodes D1 to DN are arranged.

ところで、プラズマディスプレイ装置の発光を考えるにあたり、非常に重要になってくるのが、壁電荷という概念である。パネルの各電極間には、ある一定の電圧(Vf)以上の電圧をかけることはできず、もしこのVf以上の電圧が電極間にかかれば、放電を開始してしまう。この放電によって、各電極に蓄えられるのが壁電荷である。電極間電圧Vcは、外部印加電圧Vaと壁電荷Vwとによって表現され、
Vc=Va+Vw、Vc>Vfで放電開始
となる。この放電には大きく2種類あり、一つは、急激に外部印加電圧Vaが変化して、電極間電圧VcがVfを超えてしまうことによって発生する強放電であり、セルの電位状態を中和するように各電極に壁電荷がたまる。もう一つは、徐々に外部印加電圧Vaが変化することによって、徐々に電極間電圧VcがVfを超えることによって発生する弱放電である。この弱放電では、電極間電圧VcがVfの状態を保ったまま、壁電荷Vwがたまっていく。
By the way, the concept of wall charge becomes very important when considering the light emission of a plasma display device. A voltage higher than a certain voltage (Vf) cannot be applied between the electrodes of the panel, and if a voltage higher than Vf is applied between the electrodes, discharge starts. The wall charges are stored in each electrode by this discharge. The interelectrode voltage Vc is expressed by the externally applied voltage Va and the wall charge Vw,
The discharge starts when Vc = Va + Vw and Vc> Vf. There are two main types of discharge. One is a strong discharge that occurs when the externally applied voltage Va suddenly changes and the interelectrode voltage Vc exceeds Vf, neutralizing the potential state of the cell. As a result, wall charges accumulate on each electrode. The other is weak discharge that occurs when the externally applied voltage Va gradually changes and the interelectrode voltage Vc gradually exceeds Vf. In this weak discharge, the wall charges Vw accumulate while the interelectrode voltage Vc is kept at Vf.

ここで、プラズマディスプレイ装置の駆動方法の一例(特許文献1)について、図5により説明する。   Here, an example of the driving method of the plasma display device (Patent Document 1) will be described with reference to FIG.

初期化期間21では、走査電極4に印加する正の徐々に変化する電圧波形Vset1と、維持電極5に印加される負の徐々に変化する電圧波形Vset2とにより、弱放電が発生し、走査電極に負の壁電荷が蓄積し、維持電極5には正の壁電荷が蓄積される。次に維持電極5に電圧がGNDレベルまで上がった後、走査電極4をGNDへ、維持電極5をVsusへ偏移させる。この時、走査電極4の負の壁電荷と、維持電極5の正の壁電荷によって、強放電が発生し、走査電極4には正、維持電極5には負の壁電荷が蓄積され、セル内の電界強度が0になった時点で放電が終了する。さらに、維持電極5の印加電圧がGNDへ、走査電極4の電圧が維持電圧Vsusまで上昇する。すでに蓄えられていた壁電荷とともに強放電を起こし、壁電荷が反転する。つまり、走査電極4には先ほどとは逆の負の壁電荷が蓄積し、維持電極5に正の壁電荷が蓄積する。   In the initialization period 21, a weak discharge is generated by the positive gradually changing voltage waveform Vset 1 applied to the scan electrode 4 and the negative gradually changing voltage waveform Vset 2 applied to the sustain electrode 5. Negative wall charges are accumulated in the storage electrode 5, and positive wall charges are accumulated in the sustain electrode 5. Next, after the voltage of the sustain electrode 5 rises to the GND level, the scan electrode 4 is shifted to GND and the sustain electrode 5 is shifted to Vsus. At this time, a strong discharge is generated by the negative wall charge of the scan electrode 4 and the positive wall charge of the sustain electrode 5, and the positive wall charge is accumulated in the scan electrode 4 and the negative wall charge is accumulated in the sustain electrode 5. Discharge is terminated when the electric field strength of the inside becomes zero. Furthermore, the voltage applied to sustain electrode 5 rises to GND, and the voltage on scan electrode 4 rises to sustain voltage Vsus. A strong discharge is caused with the wall charges already stored, and the wall charges are inverted. In other words, negative wall charges opposite to the above are accumulated in scan electrode 4, and positive wall charges are accumulated in sustain electrode 5.

ここで、セル内の電圧は強放電が発生する、とこれを中和するように壁電荷を蓄積して放電動作を終了するため、データ電極8も放電の影響を受け、VsusとGNDレベルの中間的な電圧の壁電荷が蓄積される。これにより、次に走査電極4をGNDへ落とし、書き込み放電が発生しないときには、維持期間において、維持電極5の電位をVsusまで上げることにより、再び壁電荷を反転させることができ、維持動作が可能となる。つまり、初期化期間21により、全セルを点灯状態にすることができる。   Here, the voltage in the cell generates a strong discharge, and the wall charges are accumulated so as to neutralize this, and the discharge operation is terminated. Therefore, the data electrode 8 is also affected by the discharge, and the Vsus and GND levels Intermediate voltage wall charges accumulate. As a result, when the scan electrode 4 is then dropped to GND and no writing discharge occurs, the wall charge can be inverted again by raising the potential of the sustain electrode 5 to Vsus during the sustain period, and a sustain operation is possible. It becomes. That is, all the cells can be turned on by the initialization period 21.

書き込み期間22では、全ての維持電極5をGNDに保持し、第1行目の表示する放電セルに対応する所定のデータ電極D1〜DNに正の書き込みパルス電圧(+Vd)を、第1行目の走査電極SCN1に負の走査パルス電圧(−Vsc)をそれぞれに印加すると、所定のデータ電極D1〜DNと第1行目の走査電極SCN1との交点部において、書き込み放電が起こる。次に、第2行目の表示する放電セルに対応する所定のデータ電極D1〜DNに正の書き込みパルス電圧(+Vd)を、第2行目の走査電極SCN2に負の走査パルス電圧(−Vsc)をそれぞれに印加すると、所定のデータ電極D1〜DNと第2行目の走査電極SCN2との交点部において書き込み放電が起こる。   In the write period 22, all sustain electrodes 5 are held at GND, and a positive write pulse voltage (+ Vd) is applied to the predetermined data electrodes D1 to DN corresponding to the discharge cells to be displayed on the first row. When a negative scan pulse voltage (−Vsc) is applied to each of the scan electrodes SCN1, write discharge occurs at the intersections of the predetermined data electrodes D1 to DN and the scan electrode SCN1 in the first row. Next, a positive write pulse voltage (+ Vd) is applied to predetermined data electrodes D1 to DN corresponding to discharge cells to be displayed in the second row, and a negative scan pulse voltage (−Vsc) is applied to scan electrode SCN2 in the second row. ) Is applied to each, an address discharge occurs at the intersection of predetermined data electrodes D1 to DN and scan electrode SCN2 in the second row.

上記同様の動作が順次に行われて、最後に第M行目の表示する放電セルに対応する所定のデータ電極D1〜DNに正の書き込みパルス電圧(+Vd)を、第M行目の走査電極SCNMに負の走査パルス電圧(−Vsc)をそれぞれ印加すると、所定のデータ電極D1〜DNと第M行目の走査電極SCNMとの交点部において書き込み放電が起こる。この放電は、負の壁電荷を持つ走査電極に負の電圧を加え、正の壁電荷を持つデータ電極に正の電圧を加えることで放電を起こし、放電後にはセル内の壁電荷は、ほぼ消滅する。ここで、走査パルス電圧Vscは、GNDレベルよりアドレス電圧Vadだけ嵩上げされている。これは、もし、Vadが0であれば書き込み放電が発生しづらくなり、逆にVad=Vscnだと書き込み動作をしない状態でも走査パネルを印加することにより、書き込みを行ってしまうため、書き込み放電をスムーズに行うことができるようにするためである。   The same operation as described above is sequentially performed, and finally, a positive write pulse voltage (+ Vd) is applied to predetermined data electrodes D1 to DN corresponding to discharge cells to be displayed in the Mth row, and the Mth row scanning electrode. When a negative scan pulse voltage (-Vsc) is applied to SCNM, an address discharge occurs at the intersection of predetermined data electrodes D1 to DN and Mth scan electrode SCNM. This discharge is caused by applying a negative voltage to the scan electrode having a negative wall charge and applying a positive voltage to the data electrode having a positive wall charge. After the discharge, the wall charge in the cell is almost equal. Disappear. Here, the scan pulse voltage Vsc is raised by the address voltage Vad from the GND level. This is because if Vad is 0, writing discharge is difficult to occur. Conversely, if Vad = Vscn, writing is performed by applying the scanning panel even when the writing operation is not performed. This is so that it can be performed smoothly.

次の維持期間23では、書き込み動作がなかったセルに対しては、走査電極4に負、維持電極5に正の壁電荷がたまっているため、走査電極4をGNDに、維持電極5にVsusを加えることにより放電し、走査電極4に正、維持電極5に負の壁電荷がたまる。次に、それぞれの電圧に逆の電圧を加えることにより、逆の壁電荷がたまり、これを反復して行くことにより、放電が持続する。維持期間の最後は、走査電極4をVsusにして、負の壁電荷を蓄積して終了する。これは、初期化期間と同じことであり、次の維持期間において、書き込み放電を発生しない場合には、放電を持続させることができる。一方、書き込み放電を行った場合には、壁電荷がほとんどなくなってしまうために、維持動作ができなくなる。   In the next sustain period 23, for the cells that have not performed the write operation, negative wall charges are accumulated in the scan electrode 4 and positive wall charges are accumulated in the sustain electrode 5, so that the scan electrode 4 is GND and the sustain electrode 5 is Vsus. As a result, the scan electrode 4 is positively charged and the sustain electrode 5 is negatively charged. Next, reverse wall charges are accumulated by applying reverse voltages to the respective voltages, and the discharge is continued by repeating this. At the end of the sustain period, the scan electrode 4 is set to Vsus, and the negative wall charges are accumulated to end the sustain period. This is the same as the initialization period. In the next sustain period, if no write discharge is generated, the discharge can be sustained. On the other hand, when the write discharge is performed, the wall charges are almost lost, so that the sustain operation cannot be performed.

例えば、図6に示すような1フィールドを8サブフィールドに分割した場合には、第1サブフィールドは、初期化期間21と書き込み期間22と維持期間23からなり、後の2から8のサブフィールドは、書き込み期間22と維持期間23のみで構成される。はじめの初期化期間で全セルを点灯状態とし、書き込み放電が起こるまでは、維持期間での放電を持続させ、書き込み期間で書き込まれたセルは以降点灯しない。よって、図6に示すように、全く維持発光しない場合を含めて全部で9階調を表現することが可能となる。なお、図中の○は、維持発光をするサブフィールド、×は書き込み放電をするサブフィールドである。
特開2000−227778号公報
For example, when one field as shown in FIG. 6 is divided into 8 subfields, the first subfield includes an initialization period 21, a writing period 22, and a sustain period 23, and the subsequent 2 to 8 subfields Consists of a writing period 22 and a sustaining period 23 only. All cells are lit in the initial initialization period, and the discharge in the sustain period is continued until the write discharge occurs, and the cells written in the write period are not lit thereafter. Therefore, as shown in FIG. 6, it is possible to express a total of nine gradations including the case where no sustain light emission is performed. In the figure, o is a subfield for sustaining light emission, and x is a subfield for writing discharge.
JP 2000-227778 A

ここで、初期化終了後、書き込み期間で書き込み放電が行われた場合のセルについて説明すると、図7(a)に初期化終了後(図5のA点)の壁電荷状態を示す。図に示すように、走査電極4に負、維持電極5に正の壁電荷が蓄積しており、壁電荷は書き込み期間まで保持される。続く書き込み期間で書き込み放電を行う場合(図5のB点)、走査電極4にVad(V)のパルスを、データ電極8には書き込みパルスVd(V)を印加する(図7(b))。走査電極4の電圧Vad(V)とデータ電極8の電圧Vd(V)に壁電荷分が上乗せされ、走査電極4とデータ電極8間の放電開始電圧を超えて、書き込み放電が発生し、図7(c)のようにセル内で壁電荷の再形成が行われる。続く維持期間では、走査電極4と維持電極5に交互にVsus(V)振幅の維持パルスが印加されるが、走査電極4にVsus(V)電圧が印加された場合(図5のC点)、Vsus電圧に書き込み終了後の壁電荷分が上乗せされる。書き込み終了後の走査電極4とデータ電極8間の壁電荷量が十分少なかった場合、上記維持パルス印加時に放電が発生することはないが、書き込み放電をスムーズにするためにVad電圧を小さくするや、Vd電圧を大きくするなどを行った場合、書き込み終了後の壁電荷は大きくなり、維持期間中に走査電極4に維持パルスが印加された時に、走査電極4とデータ電極8間でのセル内電圧が放電開始電圧を超えて、放電が発生する(図7(d))。図5のC点での走査電極4とデータ電極8間での放電が発生することにより、走査電極4と維持電極5間での放電も発生して、続く維持パルスでも放電が発生することとなり、書き込み期間中に消去放電を行った場合でも、維持期間中に放電が発生してしまい、表示不良の原因となる。   Here, the cell in the case where the write discharge is performed in the write period after completion of the initialization will be described. FIG. 7A shows the wall charge state after the completion of the initialization (point A in FIG. 5). As shown in the figure, negative wall charges are accumulated in the scan electrode 4 and positive wall charges are accumulated in the sustain electrode 5, and the wall charges are held until the writing period. When writing discharge is performed in the subsequent writing period (point B in FIG. 5), a pulse of Vad (V) is applied to the scanning electrode 4 and a writing pulse Vd (V) is applied to the data electrode 8 (FIG. 7B). . A wall charge is added to the voltage Vad (V) of the scan electrode 4 and the voltage Vd (V) of the data electrode 8, and the discharge discharge voltage is generated exceeding the discharge start voltage between the scan electrode 4 and the data electrode 8. As shown in FIG. 7 (c), wall charges are reformed in the cell. In the subsequent sustain period, sustain pulses having an amplitude of Vsus (V) are alternately applied to scan electrode 4 and sustain electrode 5, but when a Vsus (V) voltage is applied to scan electrode 4 (point C in FIG. 5). , The wall charge after writing is added to the Vsus voltage. When the amount of wall charges between the scan electrode 4 and the data electrode 8 after writing is sufficiently small, no discharge occurs when the sustain pulse is applied, but the Vad voltage is reduced to make the writing discharge smooth. When the Vd voltage is increased, the wall charge after the writing is increased, and when the sustain pulse is applied to the scan electrode 4 during the sustain period, the cell charge between the scan electrode 4 and the data electrode 8 is increased. The voltage exceeds the discharge start voltage, and discharge occurs (FIG. 7 (d)). When a discharge is generated between the scan electrode 4 and the data electrode 8 at the point C in FIG. 5, a discharge is generated between the scan electrode 4 and the sustain electrode 5, and a discharge is generated even in the subsequent sustain pulse. Even when the erasing discharge is performed during the writing period, a discharge occurs during the sustain period, which causes a display defect.

本発明はこのような課題を解決し、書き込み放電を行ったセルが維持期間中に放電するのを防ぎ、表示不良を無くすものである。   The present invention solves such a problem, prevents a cell that has undergone a write discharge from being discharged during the sustain period, and eliminates display defects.

上記目的を達成するために本発明のプラズマディスプレイ装置の駆動方法は、走査電極および維持電極が対になるように配置され、前記走査電極および維持電極と交差するようにデータ電極が配列され、走査電極および維持電極とデータ電極との交差部に放電セルを形成してなるプラズマディスプレイ装置の駆動方法において、1フィールドまたは少なくとも書き込み期間を有する複数のサブフィールドによって構成されたサブフィールド群の最初に全ての放電セルを点灯状態にする初期化期間と、サブフィールド群内のサブフィールド毎に放電セルに選択的に書き込み放電を行い非点灯状態にする書き込み期間と、前記書き込み放電を行っていない放電セルの走査電極および維持電極に対してのみ維持パルスを印加して維持電極を行う維持期間とを有し、維持期間中において、維持電極に最初の維持パルスが印加されてから最後の維持パルスが印加されるまでの間、データ電極に維持パルスと同極性の電圧を印加し、かつ維持期間中の最後の維持パルスを走査電極に印加するとともに、走査電極に最後に印加される維持パルスの振幅電圧は、維持期間中のその他の維持パルスの振幅電圧に比べて小さくし、前記最後の維持パルスを印加する間は前記データ電極の電位をGNDにするものである。

In order to achieve the above object, a driving method of a plasma display apparatus according to the present invention includes a scan electrode and a sustain electrode arranged in pairs, a data electrode arranged so as to cross the scan electrode and the sustain electrode, and a scan. In a driving method of a plasma display device in which discharge cells are formed at intersections of electrodes, sustain electrodes, and data electrodes, all of the first subfield groups formed by one field or a plurality of subfields having at least a writing period An initialization period in which the discharge cells are turned on, an address period in which the discharge cells are selectively subjected to write discharge for each subfield in the subfield group, and a discharge cell in which the write discharge is not performed maintaining the by the application of only sustain pulses to scan electrodes and sustain electrodes performing sustain electrodes And a while, during the sustain period, during the time between the first sustain pulse applied to the sustain electrode before the last sustain pulse is applied, the pulse voltage of the same polarity sustain the data electrodes is applied, and with the last sustain pulse in the sustain period is applied to the scan electrodes, the amplitude voltage of the sustain pulse applied to the last scan electrode, and smaller than the other of the amplitude voltage of the sustain pulse during the sustain period, the While the last sustain pulse is applied, the potential of the data electrode is set to GND .

以上の説明から明らかなように本発明によれば、維持期間中において、維持電極に最初の維持パルスが印加されてから最後の維持パルスが印加されるまでの間、データ電極に維持パルスと同極性の電圧を印加し、かつ維持期間中の最後の維持パルスは走査電極に印加するとともに、前記走査電極に最後に印加される維持パルスの振幅電圧は、維持期間中のその他の維持パルスの振幅電圧に比べて小さく設定することにより、書き込み放電を行ったセルにおける不要な維持期間での誤放電を防ぐことができる。 As is clear from the above description, according to the present invention, during the sustain period, the first sustain pulse is applied to the sustain electrode and the last sustain pulse is applied until the last sustain pulse is applied to the data electrode. A polarity voltage is applied, and the last sustain pulse during the sustain period is applied to the scan electrode, and the amplitude voltage of the last sustain pulse applied to the scan electrode is the amplitude of the other sustain pulses during the sustain period. By setting the voltage smaller than the voltage, it is possible to prevent erroneous discharge in an unnecessary sustain period in a cell in which write discharge has been performed.

以下、本発明の一実施の形態によるプラズマディスプレイ装置の駆動方法について図1、図2を用いて説明する。   Hereinafter, a method for driving a plasma display apparatus according to an embodiment of the present invention will be described with reference to FIGS.

図1に本発明の一実施の形態におけるプラズマディスプレイ装置の動作タイミングを示しており、初期化期間21と書き込み期間22については図5に示す例と同じである。   FIG. 1 shows the operation timing of the plasma display device according to the embodiment of the present invention. The initialization period 21 and the writing period 22 are the same as those shown in FIG.

本発明においては、維持期間23で維持電極、走査電極のそれぞれに交互に振幅電圧Vsus(V)の維持パルスを印加し、かつ維持期間の最初のパルスが印加されてから維持期間の最後のパルスが印加される前までの間、図1のP1に示すように、データ電極にVda1(V)の電圧を印加し、また維持期間の最後のパルスを印加する期間ではデータ電極の電位はGNDとし、走査電極の振幅電圧をVdk(V)としている。また、前記振幅電圧Vbk(V)は維持期間のその他の維持パルスの振幅電圧Vsus(V)よりも小さい電圧としている。   In the present invention, the sustain pulse of the amplitude voltage Vsus (V) is alternately applied to the sustain electrode and the scan electrode in the sustain period 23, and the last pulse of the sustain period after the first pulse of the sustain period is applied. 1 is applied, the voltage of Vda1 (V) is applied to the data electrode as indicated by P1 in FIG. 1, and the potential of the data electrode is set to GND during the last pulse of the sustain period. The amplitude voltage of the scan electrode is Vdk (V). The amplitude voltage Vbk (V) is smaller than the amplitude voltage Vsus (V) of other sustain pulses in the sustain period.

前述したように、書き込み期間で書き込み放電を行ったセルには、走査電極とデータ電極間には壁電荷が形成される。この壁電荷により走査電極とデータ電極にかかる電圧を壁電荷Vw(sc−dt)とすると、従来の維持期間では、走査電極がVsus(V)となり、データ電極がGNDであったために、走査電極とデータ電極間のセル内にかかる電圧は、Vsus(V)+Vw(sc−dt)(V)となる。この電圧が放電開始電圧を超えることで、維持期間に誤放電が発生していた。   As described above, wall charges are formed between the scan electrode and the data electrode in the cell in which the write discharge is performed in the write period. If the voltage applied to the scan electrode and the data electrode by the wall charge is the wall charge Vw (sc-dt), the scan electrode becomes Vsus (V) and the data electrode is GND in the conventional sustain period. And the voltage applied to the cell between the data electrodes is Vsus (V) + Vw (sc−dt) (V). When this voltage exceeds the discharge start voltage, erroneous discharge occurred during the sustain period.

しかし、走査電極にVsus(V)が印加される時にデータ電極にVda1(V)の電圧を印加することにより、走査電極とデータ電極間にかかる電圧はVsus(V)−Vdal(V)+Vw(sc−dt)(V)となり、従来よりも走査電極とデータ電極間の電位差は小さくなるため、誤放電は発生しにくくなる。   However, by applying the voltage Vda1 (V) to the data electrode when Vsus (V) is applied to the scan electrode, the voltage applied between the scan electrode and the data electrode is Vsus (V) −Vdal (V) + Vw ( sc-dt) (V), and the potential difference between the scan electrode and the data electrode is smaller than in the prior art, so that erroneous discharge is less likely to occur.

なお、全ての維持パルスにおいて、データ電極の電位をVda1(V)にしてしまうと、書き込み放電を行ったセルでは、誤放電現象は発生しないのであるが、書き込み放電を行わないセル(維持期間中に維持放電を行うセル)ではデータ電極の電位が上がっていることにより、維持期間終了後にデータ側に壁電荷を十分に貯めることができなくなる。これにより、続く書き込み放電が正常に行われないなどの不具合が生じる。本発明では、維持期間の最終パルスでは、データ電極の電位をGNDとし、最終パルスの振幅電圧をVbk(V)とすることで、書き込み放電を行ったセルは、最終パルスでの走査電極とデータ電極間のセル内電圧はVbk(V)+Vw(sc−dt)(V)となり、Vbk(V)<Vsus(V)であるから、走査電極とデータ電極間での誤放電は起こりにくい。また、書き込み放電を行わないセルに対しても、維持期間の最終パルスで走査電極とデータ電極間に壁電荷を貯めることが可能となり、続く書き込み動作もスムーズに行うことができる。   In all sustain pulses, if the potential of the data electrode is set to Vda1 (V), a cell in which write discharge is performed does not cause a false discharge phenomenon, but a cell in which no write discharge is performed (during the sustain period). In the cell which performs the sustain discharge at the same time, since the potential of the data electrode is increased, the wall charges cannot be sufficiently stored on the data side after the end of the sustain period. As a result, problems such as subsequent writing discharge not being performed normally occur. In the present invention, in the final pulse of the sustain period, the potential of the data electrode is set to GND, and the amplitude voltage of the final pulse is set to Vbk (V). The in-cell voltage between the electrodes is Vbk (V) + Vw (sc−dt) (V), and Vbk (V) <Vsus (V), so that an erroneous discharge is unlikely to occur between the scan electrode and the data electrode. Further, it becomes possible to store wall charges between the scan electrode and the data electrode with the last pulse of the sustain period even for a cell that does not perform the write discharge, and the subsequent write operation can be performed smoothly.

ここで、上記最終パルスの振幅電圧Vbk(V)は、Vbk(V)<Vsus(V)であると共に、維持放電を持続させるだけの電圧値である必要がある。具体的にはVbk(V)はVsus(V)−10V以下であり、Vsus(V)−30V以上の範囲で設定することが望ましい。また、このとき最終維持パルスのパルス幅(Tbk)は、維持期間のその他の維持パルスの維持パルス幅(Tsus)よりも広く設定することにより、維持パルスの振幅電圧が小さい場合でも、書き込み期間で書き込みを行わなかったセルが維持放電を正常に行うことが可能となる。   Here, the amplitude voltage Vbk (V) of the final pulse needs to be a voltage value sufficient to sustain the sustain discharge while Vbk (V) <Vsus (V). Specifically, Vbk (V) is Vsus (V) −10V or less, and is desirably set in a range of Vsus (V) −30V or more. At this time, the pulse width (Tbk) of the last sustain pulse is set wider than the sustain pulse width (Tsus) of the other sustain pulses in the sustain period, so that even in the case where the amplitude voltage of the sustain pulse is small, A cell that has not been written can normally perform a sustain discharge.

このように維持期間中の誤放電を減らすためには、データ電極に電位を与えるタイミングは走査電極に振幅電圧Vsus(V)の維持パルスが印加された時にデータ電極の電位をあげてやればよい。しかしながら、走査電極の維持パルスと同期してデータ電極の電位を変化させた場合、相当量の無効電力が発生してしまう。本発明においては、維持期間中において、維持電極に最初のパルスが印加されてから最後のパルスが印加される前までの間に、データ電極に維持パルスと同極性の電圧を印加している。この構成により、上述した走査電極とデータ電極間での誤放電だけでなく、維持電極と走査電極間での誤放電現象を抑えることができる。また、図2に本発明の他の実施の形態におけるプラズマディスプレイ装置の動作タイミング図を示す。図1と異なっているのは、維持期間中にデータ電極に印加する電圧Vda1(V)が書き込み期間中にデータ電極に印加する電圧Vd(V)と同様である点と、初期化期間と書き込み期間の間、維持期間と書き込み期間の間に壁電荷調節期間24を有する点である。維持期間中にデータ電極に印加する電圧Vda1(V)を書き込み期間中にデータ電極に印加する電圧Vd(V)と同じにすることで、上記実施の形態で得られた効果をほとんど損なうことなく、データ電極を駆動させるために用いる電源や駆動回路を簡略化でき、コストを下げることができる。また初期化期間と書き込み期間の間、維持期間と書き込み期間の間に壁電荷調節期間を有する駆動波形を印加することで、パネル面内の壁電荷状態を壁電荷調節期間で調節し、パネル内のセル間のばらつきを少なくすることができ、書き込み電圧Vd(V)を下げることができる。 Thus, in order to reduce erroneous discharge during the sustain period, the potential of the data electrode may be increased when the sustain pulse of the amplitude voltage Vsus (V) is applied to the scan electrode. . However, if the potential of the data electrode is changed in synchronization with the sustain pulse of the scan electrode, a considerable amount of reactive power is generated. In the present invention, during the sustain period, a voltage having the same polarity as the sustain pulse is applied to the data electrode after the first pulse is applied to the sustain electrode and before the last pulse is applied. With this configuration, it is possible to suppress not only the erroneous discharge between the scan electrode and the data electrode described above but also the erroneous discharge phenomenon between the sustain electrode and the scan electrode. FIG. 2 shows an operation timing chart of the plasma display device according to another embodiment of the present invention. 1 differs from FIG. 1 in that the voltage Vda1 (V) applied to the data electrode during the sustain period is the same as the voltage Vd (V) applied to the data electrode during the write period, the initialization period, and the write period. The wall charge adjustment period 24 is provided between the sustain period and the writing period during the period. By making the voltage Vda1 (V) applied to the data electrode during the sustain period the same as the voltage Vd (V) applied to the data electrode during the write period, the effect obtained in the above embodiment is hardly impaired. The power supply and driving circuit used for driving the data electrode can be simplified, and the cost can be reduced. In addition, by applying a driving waveform having a wall charge adjustment period between the initialization period and the write period, and between the sustain period and the write period, the wall charge state in the panel surface is adjusted by the wall charge adjustment period, The cell-to-cell variation can be reduced, and the write voltage Vd (V) can be lowered.

本発明の一実施の形態によるプラズマディスプレイ装置の駆動方法における動作タイミング図FIG. 4 is an operation timing chart of the method for driving the plasma display apparatus according to the embodiment of the present invention. 本発明の他の実施の形態によるプラズマディスプレイ装置の駆動方法における動作タイミング図Operation Timing Diagram in Driving Method of Plasma Display Device According to Other Embodiment of the Present Invention プラズマディスプレイパネルの一部を切り欠いて示す斜視図Perspective view showing a plasma display panel with a part cut away プラズマディスプレイパネルの電極配列を示す説明図Explanatory drawing showing the electrode arrangement of the plasma display panel 従来のプラズマディスプレイ装置の動作タイミング図Operation timing chart of conventional plasma display device 従来の駆動シーケンスを示す説明図Explanatory drawing showing a conventional drive sequence 従来の課題を示すセル内壁電荷分布図Cell inner wall charge distribution diagram showing conventional problems

符号の説明Explanation of symbols

1,6 基板
4 走査電極
5 維持電極
8 データ電極
12 放電セル
21 初期化期間
22 書き込み期間
23 維持期間
1, 6 Substrate 4 Scan electrode 5 Sustain electrode 8 Data electrode 12 Discharge cell 21 Initialization period 22 Write period 23 Sustain period

Claims (1)

走査電極および維持電極が対になるように配置され、前記走査電極および維持電極と交差するようにデータ電極が配列され、前記走査電極および維持電極とデータ電極との交差部に放電セルを形成してなるプラズマディスプレイ装置の駆動方法において、1フィールドまたは少なくとも書き込み期間を有する複数のサブフィールドによって構成されたサブフィールド群の最初に全ての放電セルを点灯状態にする初期化期間と、サブフィールド群内のサブフィールド毎に放電セルに選択的に書き込み放電を行い非点灯状態にする書き込み期間と、前記書き込み放電を行っていない放電セルの前記走査電極および維持電極に対してのみ維持パルスを印加して維持電極を行う維持期間とを有し、前記維持期間中において、前記維持電極に最初の維持パルスが印加されてから最後の維持パルスが印加されるまでの間、前記データ電極に維持パルスと同極性の電圧を印加し、かつ維持期間中の最後の維持パルス前記走査電極に印加するとともに、前記走査電極に最後に印加される維持パルスの振幅電圧は、維持期間中のその他の維持パルスの振幅電圧に比べて小さくし、前記最後の維持パルスを印加する間は前記データ電極の電位をGNDにすることを特徴とするプラズマディスプレイ装置の駆動方法。 A scan electrode and a sustain electrode are arranged in a pair, a data electrode is arranged to intersect the scan electrode and the sustain electrode, and a discharge cell is formed at an intersection of the scan electrode, the sustain electrode and the data electrode. An initializing period in which all discharge cells are turned on at the beginning of a subfield group constituted by a plurality of subfields having one field or at least a writing period, and a subfield group, The sustain pulse is applied only to the scan electrode and the sustain electrode of the discharge cell where the discharge discharge is not performed by selectively performing the discharge discharge to the discharge cell for each subfield and the discharge discharge is not performed. A sustain period for performing the sustain electrode, and during the sustain period, the sustain electrode is initially maintained Between Luz is applied before the last sustain pulse is applied, applying a voltage of the sustain pulse having the same polarity to the data electrodes, and applying a last sustain pulse in the sustain period to the scan electrodes In addition, the amplitude voltage of the sustain pulse last applied to the scan electrode is smaller than the amplitude voltage of the other sustain pulses during the sustain period, and the potential of the data electrode is applied during the last sustain pulse application. A method for driving a plasma display device, characterized in that GND is used.
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JPH10214057A (en) * 1997-01-30 1998-08-11 Pioneer Electron Corp Driving method for plasma display panel
JPH10222119A (en) * 1997-02-04 1998-08-21 Pioneer Electron Corp Driving method for plasma display panel
JP2000206929A (en) * 1999-01-14 2000-07-28 Fujitsu Ltd Driving method and driving device for display panel
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JP2003015584A (en) * 2001-06-27 2003-01-17 Pioneer Electronic Corp Drive method for plasma display panel

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JPH10214057A (en) * 1997-01-30 1998-08-11 Pioneer Electron Corp Driving method for plasma display panel
JPH10222119A (en) * 1997-02-04 1998-08-21 Pioneer Electron Corp Driving method for plasma display panel
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