JP4642552B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus that converts a gain of an imaging signal obtained by photoelectric conversion into a digital signal.

  In recent years, while the number of pixels of the image sensor has increased, the readout rate of the image sensor has been increased to ensure the frame rate. Further, miniaturization is progressing while becoming multifunctional, such as storing in a large-capacity memory and outputting video to a liquid crystal monitor while compressing an image pickup signal from the image pickup device. Furthermore, there is a demand for improved usability by shortening the time from power-on to the start of shooting. As described above, in the imaging apparatus, the processing speed is increased and the size is reduced, and it is required to reduce noise mixed in the process of converting an analog signal obtained by the imaging element into a digital signal.

  On the other hand, an image signal obtained by clamping the reference signal from the image pickup apparatus having the image pickup element and the reference signal are output to the signal processing unit side by the first and second drivers having the same characteristics. An imaging apparatus that performs subtraction processing on the side has been proposed (Patent Document 1).

  The image pickup apparatus of Patent Document 1 has a signal processing circuit such as an amplifier circuit provided on the signal processing unit side away from the image pickup device, and realizes downsizing of the image pickup device and the image pickup device substrate, and is clamped to a reference signal. The image signal and the reference signal are output from the first and second drivers, respectively, and subtracted on the signal processing unit side, thereby reducing noise mixed in the image signal being transmitted.

However, since a clamp circuit is used to clamp the image signal from the image sensor to the reference signal, noise generated in the clamp circuit is mixed into the image signal. Further, the transient response time required until the clamp circuit is stabilized has not been considered.
JP 2001-86414 A

  Therefore, in view of the conventional problems, an object of the present invention is to provide an imaging apparatus that processes a high-pixel signal at high speed.

  The imaging apparatus according to the present invention includes a first signal generation unit that generates a first signal corresponding to the received charge received from the photoelectric conversion unit that generates a charge corresponding to the amount of received light, and a first signal generation unit. First reset means for resetting the received charge and causing the first signal generating means to generate a reset signal in a reset state; and an image signal generating means for generating an image signal based on the first signal and the reset signal; To output a second signal having the same characteristics as the first output means for outputting an image signal, the second signal generating means for generating a second signal substantially the same as the reset signal, and the first output means. The second output means is provided.

  The second signal generating means preferably includes a second signal generating unit having the same characteristics as the first signal generating means and a second reset means having the same characteristics as the first reset means. The reset means switches ON / OFF the application of the reset voltage used for resetting the charge to the first signal generation means, and when it is ON, the reset signal is sent to the first signal generation means according to the reset voltage. Preferably, the second reset unit applies a reset voltage to the second signal generation unit, and the second signal generation unit generates the second signal according to the reset voltage.

  The image signal generating means includes a reset signal holding means connected to the input terminal, a first switch for switching ON / OFF of conduction between the output terminal of the reset signal holding means and the output terminal of the second signal generating means. A second switch for switching ON / OFF of conduction between the output terminal of the reset signal holding means and the output terminal of the image signal generating means, and an image signal provided between the output terminal of the image signal generating means and the second switch. Preferably, image signal holding means for holding the image signal is provided.

  Moreover, it is preferable to provide a photoelectric conversion means. Further, it is preferable that the photoelectric conversion means, the first and second signal generation means, the first reset means, and the image signal generation means are integrated on a single chip.

  The third signal generating means for generating a third signal having the same characteristics as the first signal generating means and substantially the same as the reset signal, and the image signal generating means are connected to the input terminal of the image signal generating means. Reset signal holding means, a first switch for switching ON / OFF between the output terminal of the reset signal holding means and the output terminal of the third signal generating means, the output terminal of the reset signal holding means, and the image signal generating means There may be provided a second switch for switching ON / OFF of conduction with the output end, and an image signal holding means for holding an image signal provided between the output end of the image signal generating means and the second switch. preferable.

  The third signal generating means preferably includes a third signal generating unit having the same characteristics as the first signal generating means, and a third reset means having the same characteristics as the first reset means. The reset means switches ON / OFF the application of the reset voltage used for resetting the charge to the first signal generation means, and when it is ON, a reset signal is sent to the first signal generation means according to the reset voltage. Preferably, the third reset means applies a reset voltage to the third signal generator, and the third signal generator generates the third signal according to the reset voltage.

  The photoelectric conversion means, the first to third signal generation means, the first reset means, and the image signal generation means are preferably integrated on a single chip.

  According to the present invention, it is possible to obtain a highly accurate image signal even when a high-pixel signal is processed at high speed. In addition, according to the present invention, since a clamp circuit is not required, noise does not increase and the speed at the time of startup can be increased. In addition, since a reference potential that is substantially equal to the black level of the image signal can be created, a wide range of amplification factors can be set for the amplifier used in the subsequent stage, so that high sensitivity can be set.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram schematically showing an internal configuration of an image pickup apparatus to which the first embodiment of the present invention is applied and a signal processing unit connected to the image pickup apparatus.

  The imaging device 10 and the signal processing unit 50 are connected via the first and second lines L1 and L2. The subject image received by the imaging device 10 is output as an image signal to the signal processing unit 50 through the first and second lines L1 and L2. In the signal processing unit 50, predetermined signal processing is performed on the output image signal.

  The imaging device 10 includes an image signal generation unit 11, a timing generator (TG) 12, a first output unit 13 (first output unit), and a second output unit 14 (second output unit). The image signal generation unit 11 is connected in parallel to the first output unit 13 and the second output unit 14.

  The image signal generation unit 11 generates a subject image signal corresponding to the subject image and a black image signal corresponding to black as a reference. Both image signals are output from the imaging device 10 via the first output unit 13. In addition, the image signal generation unit 11 generates a reference signal (second signal) for removing noise mixed when the image signal is transmitted from the imaging device 10 to the signal processing unit 50. The reference signal is output from the imaging device 10 via the second output unit 14.

  The signal processing unit 50 is provided with a differential output circuit 51, an amplifier circuit 52, and a clamp circuit 53. The first and second output units 13 and 14 of the imaging device 10 are connected to the differential output circuit 51 via the first and second lines L1 and L2, respectively. In the difference output circuit 51, the reference signal transmitted from the second output unit 14 is subtracted from the image signal transmitted from the first output unit 13.

  The first output unit 13 and the second output unit 14 have the same characteristics, and even if noise occurs during transmission of an image signal from the imaging device 10 to the signal processing unit 50, the first and second output units 13 and 14 are the same. The same noise component is mixed in each image signal and reference signal transmitted from the output units 13 and 14. Accordingly, the subject image signal and the black image signal from which the noise component has been removed are obtained by subtraction in the difference output circuit 51.

  The subject image signal and the black image signal from which the noise component has been removed are amplified by the amplification circuit 52. A clamp circuit 53 is provided at the output terminal of the amplifier circuit 52, and a clamp process is performed on the signal output from the amplifier circuit 52. The clamped signal is output to a signal processing circuit (not shown), subjected to predetermined signal processing such as AD conversion and color complementation processing, and then sent to an LCD (not shown). Is displayed.

  Next, the configuration of the image signal generation unit 11 will be described with reference to FIG. FIG. 2 is a diagram illustrating a schematic configuration of the imaging apparatus 10. The image signal generation unit 11 is a CMOS image pickup device, and is provided with an image pickup unit 20 and a correlated double sampling / sample hold (CDS / SH) circuit 40 (image signal generation means). The imaging unit 20 is configured by pixels arranged in a two-dimensional manner.

  The imaging unit 20 includes an imaging area PA, a black detection area BA, and a reference area SA. Signal charges are generated according to the amount of received light from the imaging pixels 21P constituting the imaging area PA. On the other hand, the imaging surface of the black pixel 21B constituting the black detection area BA is shielded from light by a light shielding film (not shown), and signal charges corresponding to black are generated from the black pixel 21B. A reference signal is generated from the reference pixel 21S (second signal generating means) constituting the reference area SA.

  A subject image signal is generated based on the signal charge generated in the imaging pixel 21P. A black image signal is generated based on the signal charge generated in the black color 21B.

  The configuration of the imaging pixel, the black pixel, and the reference pixel will be described with reference to FIGS. FIG. 3 is a diagram showing the configuration of the imaging pixel 21P and the CDS / SH circuit 40. As shown in FIG. The configuration of the arbitrary imaging pixel 21P will be described, but the configuration of the other imaging pixels 21P is the same.

  The imaging pixel 21P is provided with a photodiode (PD) 22 (photoelectric conversion means), a floating diffusion (FD) 23, a transfer transistor 24, a reset transistor 25 (first reset means), an amplification transistor 26, and a selection transistor 27. .

  In the PD 22, charges corresponding to the amount of light received by the imaging pixel 21P are generated, and the generated charges are accumulated. The PD 22 is connected to the FD 23 via the transfer transistor 24. When an ON signal is input to the transfer transistor 24, the charge accumulated in the PD 22 is transferred to the FD 23. The potential of the FD 23 changes to a potential corresponding to the transferred charge.

The FD 23 is connected via a reset transistor 25 to a power supply line V _DD maintained at a predetermined potential (reset voltage). When an ON signal is input to the reset transistor 25, the charge transferred to the FD 23 is swept out to the power supply line V _DD and reset. Further, the potential of the FD 23 is reset to the potential of the power supply line V _DD .

  The FD 23 is connected to the sub electrode of the amplification transistor 26. A signal potential corresponding to the potential of the FD 23 can be output from the imaging pixel 21P as a pixel signal. Accordingly, the FD 23 and the amplification transistor 26 function as a signal generation unit (first signal generation unit) that generates a pixel signal corresponding to the charge received from the PD 22.

  The main electrode of the amplification transistor 26 is connected to the vertical read line 28 via the selection transistor 27. When the ON signal is output to the selection transistor 27, the pixel signal is output to the vertical readout line 28.

Note that Φ _T , Φ _R , and Φ _SL that are pulsed ON / OFF signals are alternately output to the transfer transistor 24, the reset transistor 25, and the selection transistor 27. The timing of the ON / OFF signal output to each of the transistors 24, 25, and 27 is controlled by the TG 12.

  A first pixel signal (first signal) which is a pixel signal when charge is transferred from the PD 22 by switching ON / OFF of the transfer transistor 24, the reset transistor 25, and the selection transistor 27 at a timing described later. Alternatively, a reset signal which is a pixel signal when the potential of the FD 23 is reset to a predetermined potential is output to the vertical readout line 28.

  The configuration of the black pixel 21B is the same as the configuration of the imaging pixel 21P except that it is a PD (second photoelectric conversion means) shielded by a light shielding film (not shown) as described above. In the manufacturing process of the imaging unit 20, the imaging pixel 21P and the black pixel 21B are integrally formed at the same time, and the PD 22, FD 23, transfer transistor 24, reset transistor 25, amplification transistor 26, and the like constituting the imaging pixel 21P and the black pixel 21B, and The characteristics of the selection transistor 27 are the same.

  One end of the vertical read line 28 is connected to the CDS / SH circuit 40. The other end is connected to the current source Iss. The CDS / SH circuit 40 includes a clamp capacitor 41 (reset signal holding means), a sample hold (SH) capacitor 42 (image signal holding means), a clamp transistor 43 (first switch), and a sample hold (SH) transistor 44 (second second). Switch).

  One end of the clamp capacitor 41 is connected to the vertical read line 28 as an input end of the CDS / SH circuit 40. The other end of the clamp capacitor 41 is connected in parallel to the clamp transistor 43 and the SH transistor 44. When the ON signal is output to the clamp transistor 43, the reset signal is held by the clamp capacitor 41.

  The output terminal of the SH transistor 44 is connected in parallel with the SH capacitor 42 and the output terminal of the CDS / SH circuit 40. That is, the SH capacitor 42 is provided between the output side of the SH transistor 44 and the CDS / SH circuit 40. When the ON signal is output to the SH transistor 44, the image signal obtained by subtracting the reset signal from the first pixel signal is sampled and held in the SH capacitor. Therefore, the CDS / SH circuit 40 generates an image signal.

  The output terminal of the CDS / SH circuit 40 is connected to the horizontal signal line 30 via the column selection transistor 29. When the ON signal is output to the column selection transistor 29, the image signal sampled and held in the SH capacitor 42 is output from the image signal generation unit 11.

  Note that an image signal generated based on the first pixel signal output from the imaging pixel 21P and the reset signal is processed as a subject image signal in a subsequent circuit. Further, an image signal generated based on the first pixel signal and the reset signal output from the black pixel 21B is processed as a black image signal in a subsequent circuit.

It should be noted that Φ _CL , Φ _SH , and Φ _S that are pulsed ON / OFF signals are alternately output to the clamp transistor 43, the SH transistor 44, and the column selection transistor 29. The timing of the ON / OFF signal output to each of the transistors 43, 44, and 29 is controlled by the TG 12.

  FIG. 4 is a diagram illustrating the configuration of the reference pixel. The reference pixel 21S includes an FD 23S, a reset transistor 25S (second reset means), an amplification transistor 26S, a selection transistor 27S, and a current source Iss.

The main electrode of the amplification transistor 26S is connected to the power supply line V _DD and the second output unit 14. The amplification transistor 26S and the second output unit 14 are grounded via the selection transistor 27S and the current source Iss. The main electrode of the reset transistor 25S is connected to the FD 23S, and the FD 23S is connected to the sub electrode of the amplification transistor 26S.

The potential of the FD 23S becomes the potential of the power supply line V _DD via the reset transistor 25S. In the amplification transistor 26S, a signal potential corresponding to the potential of the FD 23S is output as a reference signal. That is, the FD 23S and the amplification transistor 26S function as a signal generation unit (second signal generation unit) that generates a reference signal.

The sub electrode of the reset transistor 25S and the sub electrode of the selection transistor 27S are connected to the power supply line V _DD . That is, the reference pixel 21S is different from the imaging pixel 21P in that the PD and the transfer transistor are omitted, and the sub-electrode of the reset transistor 25S and the sub-electrode of the selection transistor are connected to the power supply line V _DD .

  In the manufacturing process of the imaging unit 20, the imaging pixel 21P, the black pixel 21B, and the reference pixel 21S are formed at the same time. The characteristics of the FD 23S, the reset transistor 25S, the amplification transistor 26S, and the selection transistor 27S that constitute the reference pixel 21S are the characteristics of the FD 23, the reset transistor 25, the amplification transistor 26, and the selection transistor 27 that constitute the imaging pixel 21P or the black pixel 21B. Is the same.

From the reference pixel 21S configured as described above, the reference potential that is the potential of the power supply line V _DD via the reset transistor 25S and the amplification transistor 26S is output to the second output unit 14 as a reference signal.

  The reference potential is substantially equal to the reset potential corresponding to the reset signal output from the imaging pixel 21P or the black pixel 21B, and is the same potential as the potential obtained by removing the reset noise generated when the reset transistor 25 is turned off from the reset potential. . The potential corresponding to the black image signal is also substantially equal to the reference potential.

  Next, the operation of the imaging apparatus 10 having the above-described configuration will be described using the timing chart of FIG. The operation of the pixels in n rows j to j + m columns will be described, but the operations of the other pixels are the same. The pixels in the j + m column are black pixels 21B.

  First, an ON signal is output to the selection transistors 27 of all the pixels in the n rows at the timing t0, and the pixels in the n rows are selected. That is, a pixel signal can be output from the pixels in n rows to the j to j + m column vertical signal lines 28j to 28j + m.

  Next, at the timing t1, the ON signal is output to the transfer transistor 24 and the reset transistor 25, whereby the PD 22 and the FD 23 are reset, and the reset signal is output to the j to j + m column vertical signal lines 28j to 28j + m. . At the timing t2, an ON signal is output to the clamp transistor 43, and the reset signal is clamped by the clamp capacitor 41 in the CDS / SH circuit 40 in the j to j + m columns.

  At the timing t3, an ON signal is output to the transfer transistor 24, the electric charge accumulated in the PD 22 is transferred to the FD 23, and the first pixel signal is output to the j to j + m column vertical signal lines 28j to 28j + m. At timing t4, an ON signal is output to the SH transistor 44. When the SH transistor 44 is turned ON, the image signal from which the reset noise is removed by subtracting the reset signal from the first pixel signal is sampled and held in the SH capacitor 42.

  At timing t5, an ON signal is output to the j column selection transistor 29. When the j column selection transistor 29 is turned on, the image signal sampled and held by the SH capacitor 42 in the j column is output from the image signal generation unit 11 via the horizontal signal line 30.

  At timing t6, an ON signal is output to the j + 1 column selection transistor 29. When the j + 1 column selection transistor 29 is turned on, the image signal sampled and held in the SH capacitor 42 in the j + 1 column is output from the image signal generation unit 11. Similarly, image signals sampled and held in the SH capacitors 42 in the j + 2 column to the j + m−1 column are output.

  At the timing t7, an ON signal is output to the j + m column selection transistor 29, and a black image signal is output. The image signal output from the image signal generation unit 11 at timings t5 to t7 is output from the imaging device 10 via the first output unit 13.

  Next, at the timing of t8, an OFF signal is output to the n rows of selection transistors 27, and the selection of the pixels of the n rows is cancelled. At the timing t8, the ON signal is output to the selection transistors 27 of all the pixels in the (n + 1) th row, and the pixels in the (n + 1) th row are selected. Thereafter, processing at timings t1 to t8 is performed on pixels in the (n + 1) th row. Further, the same operation is performed for pixels in all rows, and image signals for all pixels are output from the imaging device 10.

  Further, the reference signal is output from the imaging device 10 via the second output unit 14 from the image signal generation unit 11 through timings t0 to t8.

  According to the imaging apparatus to which the present embodiment having the above-described configuration is applied, the noise component mixed in the reference signal for removing the noise component generated during the transmission of the image signal is generated using the clamp circuit. It becomes possible to reduce compared with the case where it does. This is because the reference signal can be generated without providing a circuit separately from the image sensor.

  Further, according to the present embodiment, it is possible to improve the accuracy of the image signal with respect to a manufacturing error of the imaging device or a temperature change of the imaging device. In order to improve the accuracy of the captured image signal, the accuracy of the black image signal is required to be high. In order to improve the accuracy of the black image signal, it is preferable that the difference between the potential of the reference signal and the potential of the black image signal is low.

  Since the potential of the black image signal varies depending on the imaging device or the temperature of the imaging device, the accuracy of the black image signal is reduced when a signal having a constant potential is used as a reference signal. On the other hand, according to the imaging device 10 of the present embodiment, the potential of the reference signal output from the reference pixel 21S provided in the same imaging unit 20 as the imaging pixel 21P and the black pixel 21B is the potential of the black image signal as described above. It is possible to reduce the decrease in the accuracy of the image signal caused by manufacturing errors. In addition, since the reference pixel 21S has the same temperature characteristics as the black pixel 21B, it is possible to reduce a decrease in accuracy of the image signal with respect to a temperature change of the imaging device 10.

  Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram illustrating a schematic configuration of the imaging apparatus 100 to which the present embodiment is applied. In the present embodiment, the reference potential of the clamp capacitor of the CDS / SH circuit is different from that of the first embodiment. In addition, the part which has the same function as 1st Embodiment attaches | subjects the same code | symbol.

  The imaging apparatus 100 includes the image signal generation unit 110, the TG 12, and the first and second output units 13 and 14, as in the first embodiment. Further, the image signal generation unit 110 is provided with the imaging unit 200 and the CDS / SH circuit 400 as in the first embodiment.

  The internal configuration and functions of the imaging unit 200 are also the same as those in the first embodiment. Accordingly, a signal charge corresponding to the amount of received light is generated from the imaging pixel 21P, a signal charge corresponding to black is generated from the black pixel 21B, and a reference signal is generated from the reference pixel 210S.

  The internal configuration and function of the reference pixel 210S are the same as those in the first embodiment. The reference pixel 210S is connected to the CDS / SH circuit 400 and the second output unit 14. That is, the difference from the first embodiment is that the reference pixel 210S is also connected to the CDS / SH circuit 400. The configurations of the reference pixel 210S and the CDS / SH circuit 400 will be described with reference to FIG.

  The internal configuration and functions of the CDS / SH circuit 400 are the same as those in the first embodiment. The reference signal line 31 connecting the amplification transistor 26S and the second output unit 14 is connected to one end of the clamp capacitor 41 via the clamp transistor 43. Therefore, the reference potential of the clamp capacitor 41 when the clamp transistor 43 is turned on is the reference potential.

  According to the imaging device of the present embodiment having the above-described configuration, the same effect as that of the imaging device of the first embodiment can be obtained. In addition, since the reference potential of the clamp capacitor 41 is the reference potential, the potential difference between both ends of the clamp capacitor 41 is small when the reset signal is clamped by the clamp capacitor 41, and the transient current at the start of operation can be reduced. It becomes possible.

  Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram illustrating a schematic configuration of the imaging apparatus 101 to which the present embodiment is applied. In addition, the part which has the same function as 1st or 2nd embodiment attaches | subjects the same code | symbol.

  In the second embodiment, a single reference pixel is used to output a reference signal to the second output unit 14 and generate a reference potential for the clamp capacitor 41. In the present embodiment, A reference signal is output and a potential is generated separately from different reference pixels.

  The imaging apparatus 101 includes the image signal generation unit 111, the TG 12, and the first and second output units 13 and 14, as in the first and second embodiments. In addition, the image signal generation unit 11 is provided with the imaging unit 201 and the CDS / SH circuit 400 as in the first and second embodiments.

  In the reference area SA provided on the imaging surface of the imaging unit 201, a reference pixel 21S connected to the second output unit 14 and a reference pixel 211S connected to the CDS / SH circuit 40 are provided. The configuration and function of the reference pixel 21S are the same as those in the first embodiment.

  The reference pixel 211S includes an FD having the same characteristics as the FD, reset transistor, and amplification transistor (not shown) included in the reference pixel 21S, a reset transistor (third reset means), and an amplification transistor (not shown). Provided. Similar to the second embodiment, the FD and the amplification transistor provided in the reference pixel 211S function as a signal generation unit (third signal generation unit) that generates a reference signal.

  Even if the output of the reference signal from the different reference pixels and the generation of the reference potential are performed as in the imaging apparatus 101 having the above-described configuration, the same effect as in the second embodiment can be obtained.

  In the first to third embodiments, the image signal generation unit is a CMOS image sensor, that is, an image sensor manufactured based on a CMOS / LSI manufacturing process. However, as a CMOS image sensor in which TG is also integrated. It is also possible to manufacture. According to the imaging device integrated on a single chip in this way, it is possible to reduce the noise component mixed in the image signal generation unit and the TG, and further reduce the size of the entire imaging device. To do.

  Next, a modification of the first embodiment will be described. In the first embodiment, the image signal generation unit is a CMOS image sensor, but this modification is different in that a CCD is used for the image signal generation unit.

  FIG. 9 is a diagram illustrating the imaging device 102 according to this modification. The image signal generation unit 112 includes an imaging unit 202 and a CDS / SH circuit 402. The imaging unit 202 is a CCD image sensor. In addition, the part which has the same function as 1st Embodiment attaches | subjects the same code | symbol.

  On the light receiving surface of the imaging unit 202, imaging pixels 21P and black pixels 21B are arranged in a matrix. A vertical CCD 32 is provided for each column of pixels. Each vertical CCD 32 is connected to the horizontal CCD 33 at the lower end. The output end of the horizontal CCD 33 is connected to the FD 232.

  The imaging pixel 21P is provided with a PD (not shown), and charges corresponding to the amount of received light are generated and the generated charges are accumulated. The black pixel 21B is provided with a PD that has the same characteristics as the PD of the imaging pixel 21P and whose light receiving surface is shielded from light. The charges accumulated in the PD of the imaging pixel 21P and the PD of the black pixel 21B are output to the FD 232 via the vertical CCD 32 and the horizontal CCD 33. The vertical CCD 32 and the horizontal CCD 33 are driven so as to transfer electric charges from each pixel to the FD 232 by a driving pulse emitted from the TG 122.

The FD 232 is connected to the power supply line V _DD via the reset transistor 252. When an ON signal is input to the reset transistor 252, the charge transferred to the FD 232 is swept out to the power supply line V _DD and reset. Further, the potential of the FD 232 is reset to the potential of the power supply line V _DD .

  The FD 232 is connected to the sub electrode of the amplification transistor 262. A signal voltage corresponding to the potential of the FD 232 is output to the CDS / SH circuit 402 as a pixel signal. A first pixel signal that is a pixel signal when charge is transferred to the FD 232 or a reset signal that is a pixel signal when the FD 232 is reset is output to the CDS / SH circuit 402.

The imaging unit 202 is provided with a reference pixel 212S. The reference pixel 212S includes an FD 232S, a reset transistor 252S, and an amplification transistor 262S. The main electrode of the amplification transistor 262S is connected to the power supply line V _DD and the second output unit 14. The main electrode of the reset transistor 252S is connected to the power supply line V _DD and the FD 232S, and the FD 232S is connected to the sub electrode of the amplification transistor 262S.

The potential of the FD 232S becomes the potential of the power supply line V _DD through the reset transistor 252S. In the amplification transistor 262S, a signal potential corresponding to the potential of the FD232S is output as a reference signal.

  In the manufacturing process of the imaging unit 202, the reset transistor 252, the FD 232, and the amplification transistor 262 are integrally formed simultaneously with the reference pixel 212S. The characteristics of the FD 232S, the reset transistor 252S, and the amplification transistor 262S constituting the reference pixel 212S are FD 232 connected to the horizontal CCD 33, the reset transistor 252 connected to the FD 232, and the amplification transistor connected to the output terminal of the imaging unit 202, respectively. It is the same as the characteristic of H.262.

  The image pickup apparatus according to the present modification generates and outputs an image signal based on the first pixel signal and the reset signal as in the first embodiment. The configurations and functions of the first and second output units 13 and 14 are the same as those in the first embodiment. As described above, the CCD can be used in the first embodiment, and the same effect can be obtained.

  Also, the second embodiment can be modified in the same manner as the modification of the first embodiment. That is, if a configuration is adopted in which a reference signal is output to the second output unit and a potential serving as a reference for the clamp capacitor is generated using the reference pixel, the same effect as in the first embodiment can be obtained. .

  Further, the third embodiment can be modified in the same manner as the modification of the first embodiment. That is, if two or more reference pixels are provided, one reference pixel and the clamp transistor are connected, and the other reference pixel and the second output unit are connected, the same effect as the first embodiment can be obtained. Is possible.

  Although the CMOS image sensor in the first and second embodiments and the CCD in the modification are used, any image sensor may be used. The photoelectric conversion means for receiving a subject image, the charge output from the photoelectric conversion means As long as the image pickup device includes an output unit that outputs the signal as a signal and a reset unit that resets the output electric charge and outputs the signal in the reset state, the same effects as those of the embodiment or the modification can be obtained. .

  In the first to third embodiments and the modification, the black pixel is provided for each row. However, a single black pixel may be provided to output a black image signal.

  In the first and second embodiments, the pixel arrangement on the imaging surface is a matrix, but may be any two-dimensional arrangement.

  Further, like the modified CCD, a circuit subsequent to PD and FD, that is, a circuit constituted by FD, reset transistor, amplification transistor, CDS / SH circuit, first and second output units, and reference pixel is provided. It can be formed separately, and the same effect as this modification can be obtained as long as the signal charge corresponding to the amount of received light is transferred from the FD to the FD of the circuit constituted by the subsequent circuit.

It is a figure which shows schematically the internal structure of the signal processing part connected to the imaging device and imaging device to which the 1st Embodiment of this invention is applied. It is a figure which shows schematic structure of the imaging device to which 1st Embodiment is applied. It is a figure which shows the structure of an imaging pixel and a CDS / SH circuit. It is a figure which shows the structure of a reference | standard pixel. It is a timing chart which shows operation in an imaging device. It is a figure which shows schematic structure of the imaging device to which 2nd Embodiment is applied. It is a figure which shows the structure of a reference | standard pixel and a CDS / SH circuit. It is a figure which shows schematic structure of the imaging device to which 3rd Embodiment is applied. It is a figure which shows the modification of 1st Embodiment.

Explanation of symbols

10, 100, 101, 102 Imaging device 11, 110, 111, 112 Image signal generation unit 12, 122 Timing generator (TG)
13 First output unit 14 Second output unit 21P Imaging pixel 21B Black pixel 21S, 210S, 211S, 212S Reference pixel 22 Photodiode (PD)
23, 232, 232S Floating diffusion (FD)
25, 252, 252S Reset transistor 26, 262, 262S Amplification transistor 40, 400, 402 Correlated double sampling / sample and hold (CDS / SH) circuit 41 Clamp capacitor 42 Sample and hold (SH) capacitor 43 Clamp transistor 44 Sample and hold (SH) ) Transistor 50 Signal processor 51 Difference output circuit L1, L2 First and second lines BA Black detection area SA Reference area PA Imaging area

Claims (5)

Photoelectric conversion means for generating a charge according to the amount of light received, a first signal generating means for generating a first signal corresponding to the accumulated possible the charges generated electric charge in the photoelectric conversion means, before Symbol first signal An imaging pixel having first reset means for causing the first signal generation means to generate a first reset signal corresponding to the reset voltage by switching application of the reset voltage to the generation means from ON to OFF ;
The second signal generating means having the same characteristics as the first signal generating means, and the reset voltage having the same characteristics as the first reset means by applying the reset voltage to the second signal generating means. A reference pixel having second reset means for causing the second signal generation means to generate a second signal in response,
Image signal generating means for generating an image signal that is a difference between the first signal and the reset signal;
First output means for outputting the image signal to a non-inverting input terminal of a differential output circuit ;
An imaging apparatus comprising: second output means having the same characteristics as the first output means, and outputting the second signal to the inverting input terminal of the differential output circuit simultaneously with the image signal. . The image signal generating means includes
A reset signal holding means connected to an input terminal of the image signal generating means;
A first switch for switching ON / OFF of conduction between the output terminal of the reset signal holding unit and the output terminal of the second signal generation unit;
A second switch for switching ON / OFF of conduction between the output terminal of the reset signal holding unit and the output terminal of the image signal generation unit;
Wherein provided between the output end of the image signal generation means and said second switch, the imaging apparatus according to claim 1 in which the image signal holding means for holding the image signal is characterized in that it is provided. The imaging pixel, the reference pixel, and an image pickup apparatus according to claim 1 or claim 2 wherein the image signal generating means, characterized in that it is integrated on a single chip. The third signal generating means having the same characteristics as the first signal generating means, and the reset voltage having the same characteristics as the first reset means by applying the reset voltage to the third signal generating means. A second reference pixel having a third reset means for causing the third signal generation means to generate a corresponding third signal.
The image signal generating means includes
A reset signal holding means connected to an input terminal of the image signal generating means;
A first switch for switching ON / OFF of conduction between the output terminal of the reset signal holding unit and the output terminal of the third signal generating unit;
A second switch for switching ON / OFF of conduction between the output terminal of the reset signal holding unit and the output terminal of the image signal generating unit;
The imaging apparatus according to claim 1, further comprising an image signal holding unit that is provided between an output terminal of the image signal generation unit and the second switch and holds the image signal. 5. The imaging apparatus according to claim 4 , wherein the imaging pixel , the reference pixel , the second reference pixel , and the image signal generation unit are integrated on a single chip.

Images